JPH05343427A - Manufacture of stagger type thin film transistor - Google Patents

Abstract

PURPOSE:To prevent that a leak current flows into a channel region, in a method of manufacturing a stagger type thin film transistor, by impeding generation of a conductive part on a transparent insulated substrate between the source electrode and drain electrode with a simplified means. CONSTITUTION:A source electrode 2S and a drain electrode 2D are formed on a transparent insulated substrate 1, it is then exposed to plasma including elements of the group III or V or to radical species of these elements to deposit elements of the group III or V on the source electrode 2S and drain electrode 2D and thereafter it is exposed to the plasma of reduction gas. Otherwise, it is heated to remove the elements of the group III or V on the transparent insulated substrate 1 and thereafter an operation semiconductor layer 4 is formed and simultaneously an ohmic contact layer 3 is then formed by mixing the elements of the group III or V into the operation semiconductor layer 4. Moreover, a gate insulating film 5 is formed on the operation semiconductor layer 4 and then a gate electrode 6 is formed to complete the stagger type thin film transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stagger type thin film transistor forming a matrix used for driving a liquid crystal display.
r: TFT).

At present, a TFT matrix drive liquid crystal display is put to practical use in a small television and the like, and it is expected that demand for a display of a laptop personal computer and a large television will increase in the future. ..

By the way, the structure of the TFT in the TFT matrix driving the liquid crystal display is divided into an inverted stagger type and a stagger type. Of these, the stagger type is simple in structure, and thus is manufactured. It is known that it is relatively easy to improve the manufacturing yield because the number of steps for manufacturing is small, but there is a problem associated with the ease of manufacturing, so it is necessary to solve it. I have to.

[0004]

2. Description of the Related Art FIGS. 3 to 6 are side sectional views showing essential parts of a stagger type TFT in a process step for explaining a conventional example.

See FIG. 3 3- (1) An ITO (indium tin oxide) film having a thickness of, for example, 500 [Å] is formed on the transparent insulating substrate 1 made of SiO ₂ by applying the sputtering method. ..

3- (2) By patterning the ITO film formed in the step 3- (1) by applying a resist process in the lithography technique and a wet etching method using an etchant as a hydrochloric acid etching solution. Then, the source electrode 2S and the drain electrode 2D are formed.

See FIG. 4 4- (1) The transparent insulating substrate 1 on which the source electrode 2S and the drain electrode 2D are formed is subjected to parallel plate plasma CVD (plasm).
a chemical vapor deposit
ion: P-CVD) device, and 1 [%] PH ₃
/ Ar 200 [sccm], pressure 0.2 [Tor
r], the substrate temperature is 250 [° C.], and the substrate is exposed to a plasma atmosphere with a high frequency power of 100 W to deposit phosphorus (P) only on the source electrode 2S and the drain electrode 2D made of the ITO film.

4- (2) 20 [%] SiH ₄ / H ₂ 200 [sccm], pressure 0.5 [Torr], substrate temperature 250 [° C.], high frequency power 50 [W] By applying the P-CVD method, the operating semiconductor layer 4 made of a-Si: H having a thickness of 500 [Å] is grown.

At this time, P deposited on the source electrode 2S and the drain electrode 2D made of the ITO film in the step B- (1) is taken in during the formation of the operating semiconductor layer 4 made of a-Si: H. Therefore, the source electrode 2S made of the ITO film
In addition, at the interface between the drain electrode 2D and the operating semiconductor layer 4 made of a-Si: H, n ⁺ -a doped with P is formed.
The ohmic contact layer 3 made of -Si: H is thin and is surely formed.

4- (3) Subsequently, 20 [%] SiH ₄ / H ₂ is added to 200 [sc]
cm], NH ₃ 450 [sccm], pressure 1 [To
rr], the substrate temperature is 250 [° C.], and the high frequency power is 50
By applying the P-CVD method under the condition of [W], the gate insulating film 5 made of SiN _x having a thickness of 3000 [Å] is grown.

5 (1) By applying the resist process in the lithography technique and the RIE method using CF ₄ + O ₂ as an etching gas, the gate insulating film 5, the operating semiconductor layer 4 and the ohmic contact are formed. -Pattern the contact layer 3. This completes the element isolation between the TFTs.

See FIG. 6 6- (1) By applying the sputtering method, the thickness 3000
An Al film of [Å] is formed.

6- (2) By applying a resist process in the lithography technique and a wet etching method using a phosphoric acid-based etching solution as an etchant, the Al formed in the step 6- (1) is used. The film is patterned to form the gate electrode 6. The staggered TFT is completed by the above steps.

[0014]

In the conventional technique described above, the source electrode 2S and the drain electrode 2D and a-S made of the ITO film are formed in the process described with reference to FIG.
At the interface with the operating semiconductor layer 4 made of i: H, the ohmic contact layer 3 made of n ⁺ -a-Si: H exhibiting good contact characteristics can be formed. This n
⁺ -A-Si: H ohmic contact layer 3
Needless to say, the generation of P is caused by P deposited on the source electrode 2S and the drain electrode 2D made of the ITO film.

By the way, it is generally said that P is deposited only on the source electrode 2S and the drain electrode 2D made of an ITO film, but in reality, although it is a very small amount, it is formed on the transparent insulating substrate 1 made of SiO _2. Will also be deposited, which will cause problems. FIG. 7 is a side sectional view showing a staggered TFT for explaining the problems in the conventional technique. The same symbols as those used in FIGS. 3 to 6 represent the same portions, or They have the same meaning.

In the figure, 3A shows a conductive portion made of n-a-Si generated due to a slight amount of P deposited on the transparent insulating substrate 1 made of SiO ₂ . Although the conductive portion 3A shown in the figure has a lower impurity concentration than the ohmic contact layer 3, it is sufficient to pass a sufficient current to cause an increase in off current.

According to the present invention, by a simple means, a conductive portion is not formed on the transparent insulating substrate between the source electrode and the drain electrode, and as a result, leak current is prevented from flowing in the channel region.

[0018]

FIG. 1 is a diagram for explaining a change in TFT characteristics due to the presence or absence of P on a transparent insulating substrate between a source electrode and a drain electrode, and the vertical axis represents Is the drain-source current I _d [A], and
The horizontal axis represents the gate voltage V _g [V].

In the figure, the abundance ratio of P on the transparent insulating substrate between the source electrode and the drain electrode is 3%, 2
The change in the TFT characteristics when [%], 1 [%], and 0 [%] is shown, and it is obvious that the OFF current decreases as the P deposition amount decreases, and the presence of P exists. Ratio is 1
If it is less than [%], it is considered to be preferable from a practical point of view at a gate voltage V _g = −10 [V] of 1 × 10 ^−13.
[A] The off current value below can be achieved.

The inventors of the present invention have conducted many experiments, and as a result, in order to generate an ohmic contact layer,
When P is deposited on the source electrode and the drain electrode made of the O film, P is also deposited on the transparent insulating substrate.
It was confirmed that this occurs in the presence of oxygen (O).

FIG. 2 is a photoelectron spectrum of P on a transparent insulating substrate made of SiO ₂ obtained by applying X-ray photoelectron spectroscopy (XPS) after exposure to a 1% PH ₃ / Ar atmosphere. Is a diagram showing the photoelectron spectrum intensity [A. U. ], And the horizontal axis represents the binding energy [eV].

XPS irradiates a sample with X-rays,
By measuring the energy of the emitted electron, it is possible to know the bonding state of the original atom.
Peaks are seen at 34 [eV] to 135 [eV], which indicates that P and oxygen (O) are bonded. The oxygen (O) in this case is supplied from water vapor or oxygen (O) in the plasma atmosphere, or when the transparent insulating substrate is SiO ₂ , the oxygen (O) is supplied. Is done.

Quantifying the value of P based on this data,
About 3% of P is present in all atoms. Here, all atoms refer to Si, O, and P, and Si is contained because the transparent insulating substrate is SiO ₂ . In this case, it is clear that P is not bound to another element, namely Si.

From the above knowledge, the deposition of P on the transparent insulating substrate occurs in the presence of oxygen (O),
Therefore, as a countermeasure, for example, a parallel plate type PC
When performing PH ₃ / Ar plasma treatment with a VD apparatus and performing P deposition, the total of the partial pressure of water vapor and oxygen remaining in the plasma atmosphere is 1/10 of the partial pressure of PH ₃
00 or less (for example, 2 × 10 ⁻⁶ [Torr] or less), or (P + O) is removed after P is deposited, and the transparent insulating substrate is made of SiO _2. In some cases, transparent insulation between the source electrode and the drain electrode is performed by taking measures such that ionic molecules in the plasma atmosphere do not collide with each other to break the bond between O and Si in SiO _2. The abundance ratio of P on the flexible substrate is 1
[%] Must be less than or equal to

From the above, in the method of manufacturing the stagger type TFT according to the present invention, (1) the channel region is formed on the transparent insulating substrate (for example, the transparent insulating substrate 1 made of SiO ₂ ). A source electrode (eg, ITO
Source electrode 2S) and drain electrode (eg I
Forming a drain electrode 2D) made of TO, and then exposing the source electrode and the drain electrode to a plasma containing a Group 3 or Group 5 element to deposit the Group 3 or Group 5 element. Then, the element of Group 3 or Group 5 on the transparent insulating substrate is removed by exposing to plasma of a reducing gas, and then an operating semiconductor layer (for example, operating semiconductor layer 4 made of a-Si) is laminated and formed. A Group 3 or Group 5 element deposited on the source electrode and the drain electrode is mixed into the operating semiconductor layer to form an ohmic contact layer (for example, an ohmic contact layer 3 made of n ⁺ a-Si). Process, and then, a gate insulating film (for example, the gate insulating film 5 made of SiN _x ) is laminated on the operating semiconductor layer, and then the gate electrode (for example, A
and a step of forming a gate electrode 6) made of a 1-layer film to complete it, or

(2) A step of forming a source electrode and a drain electrode whose edges are opposed to each other while maintaining a gap for forming a channel region on a transparent insulating substrate, and then adding a Group 3 or Group 5 element A step of depositing a Group 3 or Group 5 element on the source electrode and the drain electrode by exposing to a plasma containing the same, and then removing the Group 3 or Group 5 element on the transparent insulating substrate. A step of heating to a temperature (for example, 350 [° C.] or higher), and then forming an operating semiconductor layer in a laminated manner and adding a Group 3 or Group 5 element deposited on the source electrode and the drain electrode in the operating semiconductor layer. To form an ohmic contact layer and then form a gate insulating film on the operating semiconductor layer and then form a gate electrode to complete the operation. Or wherein the Rukoto, or,

(3) A step of forming a source electrode and a drain electrode whose edges face each other while maintaining a gap in which a channel region should be formed on a transparent insulating substrate made of a material containing oxygen (O). Then, a step of depositing an element of Group 3 or Group 5 on the source electrode and the drain electrode using only a radical species of Group 3 element or Group 5 element, and then forming an operating semiconductor layer in a laminated manner. A step of mixing an element of Group 3 or Group 5 deposited on the source electrode and the drain electrode into the operating semiconductor layer to form an ohmic contact layer, and then forming a gate insulating film on the operating semiconductor layer. And a step of forming a gate electrode and then completing the formation.

[0028]

By adopting the above means, the abundance ratio of P on the transparent insulating substrate exposed between the source electrode and the drain electrode can be reduced to 1% or less. The off current that causes the above problem is passed na-
Since Si: H is not generated and the on / off ratio is sufficiently high, when used in a liquid crystal display, its display characteristics are good and the manufacturing yield is improved.

[0029]

EXAMPLES Before explaining the examples, the basic experiments conducted by the present inventor will be described. As mentioned above, I
Since it is only necessary that oxygen (O) does not exist when P is deposited on the TO film, a transparent insulating substrate having a source electrode and a drain electrode made of an ITO film is used as a P-CV film.
It is effective to use a means that has been widely used in the past when setting it in the D apparatus and to purify oxygen (O) as much as possible.

For this purpose, for example, parallel plate type P-CVD is used.
When introducing a transparent insulating substrate into the system, a large displacement exhaust system is used to perform PH ₃ / Ar plasma processing using an ultra-high vacuum chamber that passes through a chamber dedicated to charging, which is different from the chamber for discharge. By using means such as using

1 [%] PH ₃ / Ar: 200 [sccm] Pressure: 0.2 [Torr] Substrate temperature: 250 [° C.] High frequency power: 100 [W]

The total of the partial pressure of water vapor and the partial pressure of oxygen remaining in the plasma atmosphere is set to 1/1000 or less of the partial pressure of PH ₃ and P deposited on the transparent insulating substrate between the source electrode and the drain electrode. It is possible to make the abundance ratio of 1% or less.

Thereafter, the P-CVD method is applied, and 20 [%] SiH ₄ / H ₂ : 200 [sccm] pressure: 0.5 [Torr] substrate temperature: 250 [° C.] high frequency power: 50 [W] Under these conditions, the operating semiconductor layer 4 made of a-Si: H was grown to a thickness of, for example, 500 [Å].

At the growth stage of the a-Si: H, P deposited on the source electrode 2S and the drain electrode 2D made of the ITO film is taken into the a-Si: H, and the source electrode 2S and the drain electrode are formed. N ^{+ on the} interface in contact with 2D
Since the ohmic contact layer 3 made of a-Si is generated, and there is almost no deposition of P on the transparent insulating substrate 1 between the source electrode 2S and the drain electrode 2D, there is a conductive portion there. It is never generated.

Next, the same P-CVD method is applied, and 20 [%] SiH ₄ / H ₂ : 200 [sccm] NH ₃ : 450 [sccm] Pressure: 1.0 [Torr] Substrate temperature: 250 [° C.] The gate insulating film 5 made of SiN _x was continuously grown to have a thickness of, for example, 3000 [Å] under the condition of high frequency power: 50 [W].

After that, the value of the off current in the staggered TFT completed by applying the usual technique is a value which is considered to have no practical problem, that is, 1 × 10 ⁻¹³ [A]. I was able to lower it.

As described above, if it is found that P is deposited on the transparent insulating substrate in the presence of oxygen (O), a sufficient countermeasure is to purge oxygen (O). Therefore, the object of the present invention can be achieved, and it can be realized by applying the conventional technique described in the above.

However, if such means is adopted, it takes a lot of time to achieve the conditions, or a large-scale and expensive device is required. Therefore, it is desirable to prevent P from being deposited on the transparent insulating substrate by a simpler means, and when severe suppression of the off current is required, as described in the above ,. It is also necessary to take measures to reduce the presence of P.

A first embodiment of the present invention will be described. P is deposited using a parallel plate type P-CVD apparatus, and a
Simultaneously with the formation of the operating semiconductor layer 4 made of -Si, n ⁺ a-
When generating the ohmic contact layer 3 made of Si, first,

(1) Source electrode 2S made of ITO film
And the transparent insulating substrate 1 on which the drain electrode 2D is formed is set in a parallel plate type P-CVD apparatus, and 1 [%] PH ₃ / Ar: 200 [sccm] pressure: 0.2 [Torr] substrate temperature: The source electrode 2S and the drain electrode 2D are exposed to a plasma atmosphere of 250 [° C.] high-frequency power: 100 [W] to deposit P on the source electrode 2S and the drain electrode 2D. At this time, (P + O) is deposited on the surface of the transparent insulating substrate 1 unless the measures described in the above are taken for purging oxygen (O).

(2) Next, H ₂ : 200 [sccm] Pressure: 0.5 [Torr] Substrate temperature: 250 [° C.] High frequency power: 200 [W] Time: About 1 [minute] H ₂ plasma Exposed to.

In this way, the P deposited on the transparent insulating substrate 1 between the source electrode 2S and the drain electrode 2D.
It is possible to make the abundance ratio of 1% or less. Here, when exposed to H ₂ plasma, (P + O) is satisfactorily removed, but (P + In) is not removed. Therefore, the P deposited on the source electrode 2S and the drain electrode 2D is
Keeps the state as it is.

(3) Next, the P-CVD method is applied, and 20 [%] SiH ₄ / H ₂ : 200 [sccm] pressure: 0.5 [Torr] substrate temperature: 250 [° C.] high frequency power: 50 [ W], the operating semiconductor layer 4 made of a-Si: H having a thickness of, for example, 500 [Å] is grown.

At the growth stage of the a-Si: H, P deposited on the source electrode 2S and the drain electrode 2D made of the ITO film is taken into the a-Si: H, and the source electrode 2S and the drain electrode are formed. The interface in contact with 2D has n
^{Since the} ohmic contact layer 3 made of ⁺ -a-Si is generated, and in this case, there is almost no deposition of P on the transparent insulating substrate 1 between the source electrode 2S and the drain electrode 2D. , No conductive part is generated there.

(4) Then, the same P-CVD method is applied, and 20% SiH ₄ / H ₂ : 200 [sccm] NH ₃ : 450 [sccm] pressure: 1.0 [Torr] substrate temperature: 250 [° C.] High-frequency power: Under a condition of 50 [W], a gate insulating film 5 made of SiN _x having a thickness of 3000 [Å] is continuously grown.

(5) After that, a normal technique is applied to complete the process. The value of the off current in the staggered TFT thus obtained is a practical standard of 1 × 10 ^−13.
Needless to say, it becomes less than [A].

A second embodiment of the present invention will be described. P is deposited using a parallel plate type P-CVD apparatus, and a
Simultaneously with the formation of the operating semiconductor layer 4 made of -Si, n ⁺ a-
When generating the ohmic contact layer 3 made of Si, first,

(1) Source electrode 2S made of ITO film
And the transparent insulating substrate 1 on which the drain electrode 2D is formed is set in a parallel plate type P-CVD apparatus, and 1 [%] PH ₃ / Ar: 200 [sccm] pressure: 0.2 [Torr] substrate temperature: The source electrode 2S and the drain electrode 2D are exposed to a plasma atmosphere of 250 [° C.] high-frequency power: 100 [W] to deposit P on the source electrode 2S and the drain electrode 2D.

(2) Next, heat treatment is performed under the conditions of substrate temperature: 350 [° C.] time: approximately 30 [minutes].

In this way, since (P + O) deposited on the transparent insulating substrate 1 between the source electrode 2S and the drain electrode 2D is sublimated, its abundance ratio is 1% as in the first embodiment. ] It is possible to suppress below. When this heat treatment is performed, (P + In) does not sublimate, so P deposited on the source electrode 2S and the drain electrode 2D maintains the same state.

(3) Next, the P-CVD method is applied, and 20 [%] SiH ₄ / H ₂ : 200 [sccm] pressure: 0.5 [Torr] substrate temperature: 250 [° C.] high frequency power: 50 [ W], the operating semiconductor layer 4 made of a-Si: H having a thickness of, for example, 500 [Å] is grown.

At the growth stage of the a-Si: H, P deposited on the source electrode 2S and the drain electrode 2D made of the ITO film is taken into the a-Si: H, and the source electrode 2S and the drain electrode are formed. N ^{+ on the} interface in contact with 2D
An ohmic contact layer 3 made of a-Si is generated, and in this case, since there is almost no deposition of P on the transparent insulating substrate 1 between the source electrode 2S and the drain electrode 2D, there is no conduction there. No sex part is generated.

(4) Then, the same P-CVD method is applied, and 20 [%] SiH ₄ / H ₂ : 200 [sccm] NH ₃ : 450 [sccm] pressure: 1.0 [Torr] substrate temperature: 250 [° C.] High-frequency power: Under a condition of 50 [W], a gate insulating film 5 made of SiN _x having a thickness of 3000 [Å] is continuously grown.

(5) After that, a normal technique is applied to complete the process. The off-current value in the staggered TFT thus obtained is 1 × 10 ⁻¹³ [A] or less, which is a practical standard, as in the first embodiment.

By the way, in any of the above embodiments,
Although the transparent insulating substrate 1 is described as being made of SiO ₂ , in reality, there are problems due to the material, as described above. That is, SiO ₂
When the transparent insulating substrate 1 made of SiO ₂ is subjected to PH ₃ / Ar plasma treatment, ionic molecules collide with each other to form SiO ₂
In Si, the bond between Si and oxygen (O) is broken, and the released oxygen (O) bonds with P.

The third embodiment of the present invention can deal with the damage of SiO ₂ during such PH ₃ / Ar plasma treatment. That is, when the transparent insulating substrate 1 made of SiO ₂ is exposed to PH ₃ / Ar plasma, the μ-wave CVD device which is not directly exposed to an ionic element, or the plasma generation place and the substrate mounting place are isolated. Remote plasma CVD equipment or PH
By using a photo CVD apparatus for decomposing ₃ / Ar with a laser beam or the like, and processing using only radical species of PH ₃ ,
The SiO ₂ forming the transparent insulating substrate 1 between the source electrode 2S and the drain electrode 2D is prevented from being damaged.

In this way, oxygen (O) is not liberated from SiO ₂ , so that P does not adhere to the transparent insulating substrate 1. Therefore, after this, the staggered TFT may be completed in the same manner as the other embodiments. This third embodiment is effective when used in combination with the first and second embodiments, and is a parallel plate type plasma CVD.
When oxygen (O) is externally supplied to the device, it is impossible to achieve the intended purpose by itself.

Further, the stagger type T in which the off current is severely limited
When manufacturing FT, even if it takes time and labor, after performing the means described in the above ,,,
It is effective to take the measures found in the first to third embodiments.

[0059]

In the method of manufacturing a stagger type TFT according to the present invention, a source electrode and a drain electrode are formed on a transparent insulating substrate and exposed to plasma containing a Group 3 or Group 5 element, or the like. The element of Group 3 or Group 5 is deposited on the source electrode and the drain electrode by exposing to the radical species of the element and exposed to the plasma of reducing gas, or heated to heat the group 3 or group 5 on the transparent insulating substrate. After removing the group element, the operation semiconductor layer is formed, and at the same time, the group 3 or group 5 element is mixed into the operation semiconductor layer to form the ohmic contact layer, and the gate insulating film is formed on the operation semiconductor layer. After that, the gate electrode is formed and completed.

By adopting the above structure, the abundance ratio of P on the transparent insulating substrate exposed between the source electrode and the drain electrode can be made 1% or less,
Therefore, an off-current that causes a practical hindrance is passed through n-
Since a-Si: H is not generated and the on / off ratio is sufficiently high, the display characteristics become good when used in a liquid crystal display, and the manufacturing yield is improved.

[Brief description of drawings]

FIG. 1 is a diagram for explaining changes in TFT characteristics due to the presence or absence of P on a transparent insulating substrate between a source electrode and a drain electrode.

FIG. 2 is a photoelectron spectrum of P on a transparent insulating substrate made of SiO ₂ obtained by applying X-ray photoelectron spectroscopy (XPS) after being exposed to a 1% (PH) PH ₃ / Ar atmosphere. It is a diagram.

FIG. 3 is a cutaway side view of a main part of a staggered TFT at a process key point for explaining a conventional example.

FIG. 4 is a cutaway side view of an essential part of a staggered TFT at a process step for explaining a conventional example.

FIG. 5 is a cutaway side view of a main part of a staggered TFT at a process key point for explaining a conventional example.

FIG. 6 is a cutaway side view of a main part of a staggered TFT at a process key point for explaining a conventional example.

FIG. 7 is a side sectional view showing a staggered type TFT for explaining a problem in the conventional technique.

[Explanation of symbols]

 1 Transparent Insulating Substrate 2S Source Electrode 2D Drain Electrode 3 Ohmic Contact Layer 4 Operating Semiconductor Layer 5 Gate Insulating Film 6 Gate Electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Kakei 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (3)

[Claims] 1. A step of forming a source electrode and a drain electrode whose edges are opposed to each other while maintaining a gap in which a channel region is to be formed on a transparent insulating substrate, and then containing a Group 3 or Group 5 element. Exposing the source electrode and the drain electrode to an element of Group 3 or Group 5 on plasma, and then exposing the source electrode and the drain electrode to plasma of a reducing gas to form an element of Group 3 or Group 5 on the transparent insulating substrate. And then forming an operating semiconductor layer in a laminated manner and mixing an element of Group 3 or Group 5 deposited on the source electrode and the drain electrode into the operating semiconductor layer to form an ohmic contact layer. And a step of forming a gate insulating film on the operating semiconductor layer and then forming a gate electrode to complete the staggered thin film transistor. Method of manufacturing data. 2. A step of forming a source electrode and a drain electrode whose edges face each other while maintaining a gap in which a channel region is to be formed on a transparent insulating substrate, and then containing a Group 3 or Group 5 element. Exposing the source electrode and the drain electrode to an element of Group 3 or Group 5 by exposing to plasma, and then a temperature at which the element of Group 3 or Group 5 on the transparent insulating substrate can be removed. And a step of heating the semiconductor layer to form an ohmic contact layer by laminating an operating semiconductor layer and mixing an element of Group 3 or Group 5 deposited on the source electrode and the drain electrode into the operating semiconductor layer. And a step of forming a gate insulating film on the operating semiconductor layer and then forming a gate electrode to complete the staggered thin film. Manufacturing method of a transistor. 3. A step of forming a source electrode and a drain electrode whose edges are opposed to each other while maintaining a gap in which a channel region is to be formed on a transparent insulating substrate made of a material containing oxygen (O), Then, depositing an element of Group 3 or Group 5 on the source electrode and the drain electrode using only a radical species of Group 3 element or Group 5 element, and then forming an operating semiconductor layer in layers and Mixing a Group 3 or Group 5 element deposited on the source electrode and the drain electrode into the operating semiconductor layer to form an ohmic contact layer, and then stacking a gate insulating film on the operating semiconductor layer. A step of forming a gate electrode, and then completing the step of forming a gate electrode.