JPH05342885A - Logic circuit - Google Patents

Abstract

PURPOSE:To make high speed operation possible even when the driving force of a PMOSTR is reduced by constituting a sense amplifying circuit with NMOSTR, PMOSTR and first and second CMOS inverters. CONSTITUTION:When the potential of a bit line 14 is changed from a logical value '1' to a logical value '0', first the potential of the bit line 14 is increased by both NMOS transistor TR1 and the PMOS TR2 of a sense amplifier circuit 8. Then, when the potential exceeds the logical threshold value of a CMOS inverter 3 the potential is increased by the TR1. When the potential of the bit line 14 is transited from a logical value '0' to a logical value '1' conversely, first the potential of the bit line 14 is decreased by the electric discharge of the reading TR18 of a memory cell 15 and when the potential exceeds the logical threshold value of the inverter 3, the drop of the potential is restrained by the TR2. Thus, even when the driving force of the TR2 is reduced by the miniaturization of a semiconductor, the speed of the transition time is made very fast by the high speed TR1 and the high speed operation is available.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit such as a sense amplifier circuit, a read circuit and an address generation circuit.

[0002]

2. Description of the Related Art In recent high-speed, high-performance logic LSIs, it is possible to write new data to an address and simultaneously read previously written and stored data, which has a large storage capacity and is capable of high-speed operation. The required memory circuit is required. Such a memory circuit is called a register file.

In such a register file, memory cells are used as storage elements for the purpose of suppressing the circuit scale. Since the memory cell can be realized with a small number of Trs (transistors), the area efficiency of the memory circuit is high, and thus a large memory capacity can be realized with a relatively small area.

In recent register files, the number of data that can be read at one time, that is, the number of read ports of memory cells is increasing. As a result, the wiring area inside the memory cell, and consequently the area per memory cell, increases, and the area efficiency advantage of using the memory cell is diminished.

Therefore, a technique called a so-called single-end type bit line has been used in which the number of wirings for reading data from a memory cell is minimum for one port.

A circuit using memory cells has a problem that the operation speed is slow because a small memory cell drives a bit line having a large load capacitance. This is no exception even when the single-ended bit line is used.

In order to solve this problem, it has recently become common to use a sense amplifier. When the single end type bit line is used, a so-called single end type sense amplifier is used.

In the single end type sense amplifier, a circuit as shown in FIG. 5 (hereinafter referred to as a conventional sense amplifier circuit) is conventionally used.

In the conventional sense amplifier circuit 23, an inverter circuit 20 whose input and output terminals are short-circuited, a sense inverter 21 which is connected to the input and output terminals and whose logical threshold is adjusted, and an output signal of the sense inverter 21 are inverted. The drive inverter 22 drives an external output load.

The conventional sense amplifier circuit 23 is connected to a memory cell 15 via a bit line 14 as shown in the figure.

The operation of the conventional sense amplifier circuit 23 will be described with reference to the drawings. In the following description, the potential of the read word line 17 is "H". First, the storage node 16 inside the memory cell 15 is adjusted by adjusting the dimensions of the Tr forming the inverter Tr 20 in which the input / output terminals are short-circuited with the read Tr 18 inside the memory cell 15.
Is a logical value "0", the potential of the bit line is Vh, a logical value "
When it is 1 ″, the potential of the bit line is (Vh−ΔV), and the logic threshold value of the sense inverter 21 is almost (Vh−ΔV /
2), so that

Then, when the storage node 16 inside the memory cell 15 has the logical value "0", the potential of the bit line 14 is higher than the logical threshold value of the sense inverter 21,
The sense inverter 21 determines that the potential of the bit line 14 is "H", and its output is "L", and therefore the drive inverter 22 outputs "H", that is, the logical value "1".

On the contrary, the storage node 16 inside the memory cell 15
Is a logical value "1", the sense inverter 21 determines the potential of the bit line 14 to be "L", and its output is "H", so the drive inverter 22 outputs "L", that is, a logical value "0". To do. Here, the logical value output from the drive inverter 22 is inverted with respect to the logical value of the storage node 16 inside the memory cell 15, but this is not a problem in terms of function.

If the value of ΔV, the potential difference of 14 of the bit line 14 due to ON / OFF of the read Tr 18, is small,
Even if the small memory cell 15 drives the bit line 14 having a large load capacitance, its transition time is short. Furthermore, the potential change is due to the sense inverter
Since it occurs in the vicinity of the logic threshold value of 1 having the highest sensitivity (amplification factor), the sense inverter 21 also operates at high speed. Therefore, such a sense amplifier circuit 23 can read the data stored in the memory cell 15 at an extremely high speed.

As is clear from the above description, the smaller the value of ΔV, the faster the read operation. However, designing for that becomes difficult.

That is, if the value of ΔV is small, the process,
It becomes susceptible to slight changes in temperature or power supply voltage, and it becomes difficult to compensate for them in design.

Since the logic threshold value of the sense inverter 21 must be set to be approximately (Vh-ΔV / 2), the design of the sense inverter 21 becomes difficult for the same reason.

However, if the value of ΔV is increased in order to secure the above-mentioned design compensation, that is, the operation margin,
The transition time of the potential of the bit line 14 becomes long and the operation speed becomes slow.

As described above, in the sense amplifier circuit 23, there is generally a trade-off between the operating margin and the operating speed. Therefore, in the design, it is necessary to increase the speed while ensuring the operation margin. On the other hand, the conventional sense amplifier circuit 23 has the following problems.

First, regarding speeding up, recently, as semiconductors have been miniaturized, the driving force of the PMOS Tr has been particularly reduced. However, in the conventional sense amplifier circuit 23, the potential of the bit line 14 is (Vh
When making a transition from −ΔV) to Vh, only the PMOS Tr forming the inverter circuit 20 with the input / output terminals short-circuited prompts the transition.

Since the PMOS Tr having a weak driving force shifts the potential of the bit line 14 having a large load capacitance by ΔV which is a large value due to the operational margin, a considerable time is required. Therefore, in order to perform high speed operation, the load capacitance of the bit line 14 cannot be increased so much, and as a result it is difficult to increase the capacity of the memory circuit.

Regarding the operational margin, in the conventional sense amplifier circuit 23, the amplitude ΔV of the potential of the bit line 14 is the same as that of the Tr constituting the inverter 20 having the input and output short-circuited and the read Tr 18 of the memory cell 15. Although it depends on the dimension, it is difficult to increase the value of ΔV in this case.

This becomes more remarkable when the conventional sense amplifier circuit 23 is used as shown in FIG. Figure 6
Shows a circuit diagram when the conventional sense amplifier circuit 23 is applied to the read circuit 24 for a large capacity memory circuit.

That is, a plurality of NMOS Tr90,
.. 92 are connected to a plurality of control terminals 110, 111, ... 112 and a plurality of input terminals 100, 101 ,. Amplifier circuit 2
The read circuit 24 is commonly connected to the input terminals 3 and 3.

A plurality of input terminals 10 of the read circuit 24
0 to 102 are connected to a plurality of memory cells 15 via a plurality of bit lines 14, respectively. Further, the plurality of control terminals 110 to 112 are respectively connected to different control signals. As a result, the control signal causes the plurality of bit lines 14
Can select one bit line.

Here, the amplitude ΔV of the input potential of the conventional sense amplifier circuit 23 is determined by the Tr constituting the inverter 20 with the input and output short-circuited and the read Tr 18 of the memory cell 15,
Furthermore, the NMOS Tr90 selecting the bit line 14
~ V because it is determined by the dimension of ~ 92
It becomes increasingly difficult to increase the value of.

As described above, in view of the operational margin, the conventional sense amplifier circuit 23 makes it difficult to increase the capacity of the memory circuit.

On the other hand, in recent semiconductor logic LSIs, especially signal processing LSIs, a plurality of arithmetic circuits and memory circuits are integrated on one chip, so that the functions are advanced and the control is complicated. Therefore, the control side tends to shift from centralized control to distributed control, and the controlled circuit itself tends to be highly functional.

A memory circuit such as a register file is taken as an example of the circuit to be controlled. However, not only the data is temporarily stored and the data is taken out when necessary, but the circuit is closely related to the memory circuit. There is a tendency that the control circuits, such as those for generating high-frequency addresses, are integrated as an additional circuit of the memory circuit.

A selection signal for selecting an output in such an address generation circuit is determined as a specification at an initial stage of designing the entire chip, and usually, at that stage, a combination of logical values of the selection signal is not considered so much. Was not done.

As an example, with respect to the input address, the input address remains +1 (increment)
The specifications shown in FIG. 7 are given to the address generation circuit having a function of selecting one of the input address, the input address decremented by 1 and 0 (zero).

The specifications of this figure are based on two selection signals C0 and C.
Output value depends on combination of 1, input value, input value +
1, the input value is -1, or 0 (zero).

Based on this specification, an address generating circuit as shown in FIG. 8 can be obtained.

The address generation circuit of FIG. 8 has 3-bit inputs O0, I1, I2 and 3-bit outputs O0, O.
1 and O2 are output by a combination of two selection signals C0 and C1. This address generation circuit has a large number of gates, and the wiring is complicated accordingly.

Recent semiconductor logic LSI, especially signal processing L
With SI, the operating speed is increasing, and it has become important to increase the operating speed even in the address generating circuit as described above. As shown in FIG. 7, a logic circuit designed on the basis of specifications in which the combination of selection signals is not taken into consideration has a problem in operating speed, and the circuit scale becomes large depending on the design method.

[0036]

As described above, in the conventional single-end type sense amplifier circuit, it becomes difficult to operate at high speed as the driving force of the PMOS Tr decreases due to the recent miniaturization of semiconductors. Further, it is difficult to secure a sufficient operation margin, and it is difficult to increase the capacity of the memory circuit.

In addition, with respect to the input value, the output value has four types of <input value>, <input value +1>, <input value -1>, and <0 (zero)> depending on the combination of two selection signals. In the logic circuit such as the address generation circuit, which is one of the above, there is a problem in operating speed and circuit scale because the combination of the logical values of the selection signals is not sufficiently taken into consideration at the stage of determining the specifications.

The present invention has been made to solve the above problems, and the first invention is a PMOS Tr.
It is possible to provide a sense amplifier circuit that enables high-speed operation even when the driving force of the memory device is reduced and that can easily secure a sufficient operation margin, and that can increase the capacity of a memory circuit, and a read circuit using the same. To aim.

A second aspect of the present invention provides a high-speed and small-scale logic circuit in a logic circuit such as an address generation circuit by considering a combination of logic values of selection signals at the stage of determining specifications. With the goal.

[0040]

In order to achieve the above object, the first invention is one NMOS transistor and one NMOS transistor.
A sense amplifier circuit comprising two PMOS transistors and first and second COMS inverters,
The sense amplifier circuit has one input terminal and one output terminal, the input terminal is connected to one bit line drawn from one storage element, and the one NMO is connected.
The gate and source electrodes of the S transistor are connected to the input terminal and the drain electrode thereof is connected to the power supply, and the gate, drain and source electrodes of the one PMOS transistor are connected to the output terminal, the input terminal and the power supply, respectively. The input and output terminals of the first CMOS inverter are the input terminal and the second CMO, respectively.
The second CMO connected to the input terminal of the S inverter
The input and output terminals of the S inverter are respectively the first C
It is an output terminal of the MOS inverter and a logic circuit connected to the output terminal.

Further, the first aspect of the invention is to provide a plurality of NMOSs.
A read circuit including a transistor and the sense amplifier circuit, wherein the read circuit has a plurality of input terminals, a plurality of control terminals, and one output terminal, and the plurality of input terminals are The plurality of bit lines drawn from the plurality of storage elements are respectively connected, and the gate and source electrodes of the plurality of NMOS transistors are connected to the plurality of control terminals and the plurality of input terminals, respectively. The drain electrode is commonly connected to the input terminal of the sense amplifier circuit, and the output terminal of the sense amplifier circuit is a logic circuit connected to the output terminal.

According to the second aspect of the present invention, the output value with respect to the input value is one of the input value, the input value +1, the input value -1, and 0 (zero) depending on the combination of the two selection signals. In such a logic circuit, the two selection signals for the output value of the input value +1 are the same signal, and the two selection signals for the output value of the input value -1 are different combinations or The two selection signals corresponding to the output value of −1 are the same signal, and the two selection signals corresponding to the output value of the input value +1 are different combinations.

[0043]

With the above structure, in the sense amplifier circuit of the first invention, the potential of the bit line changes from (Vh'-ΔV ') to Vh'.
In the case of transition to, considering the transition time of the bit line potential, initially, both the NMOS Tr and the PMOS Tr raise the bit line potential.

Moreover, since one of them is a high speed NMOS Tr, the transition time is extremely fast. Further, when the bit line potential exceeds (Vh'-ΔV '/ 2), only the NMOS Tr can raise the bit line potential, but the time until the bit line potential exceeds (Vh'-ΔV' / 2) Need only be high speed, and then only NMOS Tr is not a problem for speeding up.

On the contrary, the potential of the bit line changes from Vh 'to (Vh'
In the case of transition to −ΔV ′), considering the transition time of the bit line potential, initially, the bit line potential drops due to the discharge of the read Tr of the memory cell.

Further, the bit line potential is (Vh'-ΔV '/
When it exceeds 2), the PMOS Tr suppresses the drop of the bit line potential, but the time until the bit line potential exceeds (Vh'-ΔV '/ 2) is a problem, and then the PMOS T
Suppressing the fall of the bit line potential by r does not pose a problem for speeding up.

Further, in the read circuit of the first invention, the high potential side of the amplitude ΔV ′ of the input potential of the sense amplifier circuit is determined by only one NMOS Tr, and a relatively high potential is obtained as described above. You can

On the other hand, one NMO is provided on the low and high potential side of ΔV '.
S Tr, one PMOS Tr, memory cell read Tr, and a plurality of NMs selecting bit lines
Although determined by the dimension of OSTr, the higher potential side becomes higher.

In the logic circuit of the second invention, for example, two selection signals for the output value of the input value +1 are (0,0).
And the two selection signals for the output value of the input value -1 are (0, 1). Alternatively, for example, the two selection signals for the output value of the input value +1 are (1, 0), and the input value −
The two selection signals for the output value of 1 are (1,1).

Thus, the input value +1 or the input value −
If one of the two selection signals different from each other is used to select 1, the logic design becomes easy.

[0051]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the first and second inventions will be described below with reference to the drawings.

First Invention FIG. 1 shows the configuration of an embodiment of the sense amplifier circuit of the first invention.
Shown in.

The gate and source electrodes of the NMOS Tr1 are connected to the input terminal 5 of the sense amplifier circuit 8, the drain electrode is connected to the power supply 7, and the input terminal 5 is connected to the bit line 14 drawn from the memory cell 15.

The gate, drain and source electrodes of the PMOS Tr2 are respectively the output terminal 6 of the sense amplifier circuit,
It is connected to the input terminal 5 of the sense amplifier circuit 8 and the power supply 7. The input and output terminals of the first CMOS inverter 3 are connected to the input terminal 5 of the sense amplifier circuit 8 and the input terminal of the second CMOS inverter 4, respectively, and CM
The input and output terminals of the OS inverter 4 are CM
It is connected to the output terminal of the OS inverter 3 and the external output terminal 6.

The operation of such a sense amplifier circuit 8 is
This will be described with reference to FIG.

The sense amplifier circuit 8 is connected to the memory cell 15 via the bit line 14. First, NMOS Tr
1, by adjusting the dimensions of the PMOS Tr2 and the read Tr18 of the memory cell 15, the storage node 16 inside the memory cell 15 has a logical value "
When it is "0", the potential of the bit line 14 is Vh ', and the logical value is "1".
, The transition of the bit line 14 is (Vh′−ΔV ′), and the logical threshold value of the first CMOS inverter 3 is almost (Vh′−ΔV ′).
h′−ΔV ′ / 2).

As a result, the sense amplifier circuit 8 operates similarly to the circuit 23 of FIG. That is, when the storage node 16 inside the memory cell 15 has the logical value "0", the first CMOS inverter 3 changes the potential of the bit line 14 to "".
H ”, the output is“ L ”, and therefore the second C
The MOS inverter 4 outputs "H", that is, a logical value "1".

On the contrary, the storage node 16 inside the memory cell 15
Is a logical value "1", the first CMOS inverter 3 determines the potential of the bit line 14 to be "L", and its output is "L".
H ", and therefore the second CMOS inverter 4 is
Outputs L ", that is, logical value" 0 ". Memory cell 1
The second CMO for the logical value of the storage node 16 inside
The fact that the logical value output from the S inverter 4 is inverted is exactly the same as in the circuit 23 of FIG.

Now, the potential of the bit line 14 is (Vh'-Δ
Consider the case of transition from V ′) to Vh ′. At this time,
What promotes the transition changes with the passage of time. That is, initially, both the NMOS Tr1 and the PMOS Tr2 raise the potential of the bit line 14.

After that, the potential of the bit line 14 becomes (Vh'-Δ
When V '/ 2) is exceeded, the CMOS inverter 3 determines that the potential of the bit line 14 is "H", the output is "L", and the CMOS inverter 4 outputs "H". Then, the PMOS Tr2 is cut off, and the bit line 14
Only the NMOS Tr1 can raise the potential of.

Here, considering the transition time of the potential of the bit line 14, first, the NMOS Tr1 and the PMOS T
Both r2 raise the potential of the bit line 14, and one of them is a fast NMOS Tr1, so the transition time is extremely fast.

The potential of the bit line 14 is (Vh'-Δ
When V '/ 2) is exceeded, only the NMOS Tr1 can raise the potential of the bit line 14, but if the time until the potential of the bit line 14 exceeds (Vh'-ΔV' / 2) is high, Well, after that, only the NMOS Tr1 is not a problem for speeding up.

On the contrary, the potential of the bit line 14 changes from Vh 'to (V
Consider the case of transition to h′−ΔV ′). Also at this time,
What promotes the transition changes with the passage of time. That is, initially, the potential of the bit line 14 is lowered by discharging the read Tr 18 of the memory cell 15.

After that, the potential of the bit line 14 becomes (Vh'-Δ
When V '/ 2) is exceeded, the CMOS inverter 3 determines that the potential of the bit line 14 is "L", the output is "H", and the CMOS inverter 4 outputs "L". Then, the PMOS Tr2 is turned on, and the fall of the potential of the bit line 14 is suppressed.

Here, considering the transition time of the potential of the bit line 14, first, the read Tr of the memory cell 15 is
The discharge of 18 lowers the potential of the bit line 14. This is similar to the conventional circuit 23.

The bit line voltage 14 is (Vh'-Δ
When V '/ 2) is exceeded, the PMOS Tr2 is connected to the bit line 14
The potential of the bit line 14 is suppressed to (V
The time until it exceeds h'-ΔV '/ 2) is a problem,
After that, it is not a problem for speeding up that the PMOS Tr2 suppresses the fall of the potential of the bit line 14.

Further, in the sense amplifier circuit 8 of the first aspect of the present invention, the design for ensuring the operational margin is easy.
That is, the high potential side of ΔV ′ is determined only by the NMOS Tr1 and the low potential side of ΔV ′ is the NMOS Tr1 and PMO.
S Tr2 and Tr18 for reading the memory cell 15
It is decided by the dimension of.

The high potential side is almost uniquely determined by the NMOS Tr1 and a relatively high potential can be obtained.
Therefore, the design is easy because the design can be performed mainly on the low potential side.

Further, the sense amplifier circuit 8 of the first invention
2 is applied to a large-capacity memory circuit as shown in FIG.

FIG. 2 shows the conventional sense amplifier circuit 23 shown in FIG. 6 replaced with the sense amplifier circuit 8 of the first invention.

In FIG. 2, a plurality of NMOS Tr9 are provided.
.. 92 are connected to the control terminals 110, 111 .. 112 and the input terminals 100, 101 .. 102, and their drain electrodes are connected to the sense amplifier circuit 8 shown in FIG. , And the output terminal of the sense amplifier circuit 8 is connected to the output terminal 12 of the read circuit 13.

A plurality of input terminals 100, 101 ...
2 are connected to a plurality of bit lines 14 drawn from a plurality of memory cells 15, respectively.

In this case, the high potential side of the amplitude ΔV 'of the input potential of the sense amplifier circuit 8 is the same as the NMOS Tr.
It is determined only by 1, and a relatively high potential can be obtained. On the other hand, the low and high potential side of ΔV 'is NMOS Tr1, PM
OS Tr2, Tr18 for reading the memory cell 15,
Further, the NMOS Tr9 selecting the bit line 14
Although it is determined by the dimensions of 0, 91, ... 92, the design is easy because the high potential side is high.

Second Invention FIG. 3 shows a specification for the logic circuit of the second invention, and FIG. 4 shows an address generation circuit designed based on this specification.
FIG. 4 is a circuit designed based on the specifications of FIG. 3 by using a method of simplifying a logical expression from a truth table.

As shown in FIG. 3, two selection signals C0,
The combination of C1 is (0,
0) and (1, 0) with respect to the output value of the input value −1, it is possible to realize speeding up and downsizing of the logic circuit.

It is well known that the circuits for realizing <input value +1> and <input value -1> are logically complementary to each other, but in the circuit of the second invention, <input value +1>> Or <input value −1> may be output, and the combination of the logical values of the two selection signals C0 and C1 for each is the same when the two selection signals for the output value of the input value + 1 The selection signals for the output value of -1 are different from each other. Therefore, in selecting <input value +1> and <input value -1>, if one of the two selection signals different from each other is used, the logic design becomes easy.

Further, in the logic circuit of the second aspect of the present invention, at the time of designing, a simplification method of a logical expression is used from a truth table showing a relationship between a signal representing an input value, a selection signal and a signal representing an output value. There is. By doing so, logic design becomes easier, and higher speed and smaller circuit can be realized.

Comparing the logic circuit of FIG. 4 with that of the conventional circuit of FIG. 8, the number of gates of the conventional logic circuit is 20 and that of the second invention is 17, which is small.

In FIG. 3, the output value of the input value +1 is (0, 0), and the output value of the input value -1 is (1,
0), but not limited to this, (1, 1) for the output value of the input value +1 and (0, 1) for the output value of the input value -1.
But of course it is possible.

Further, in this embodiment, the two selection signals for the output value of the input value +1 are the same signal, and the input value -1
Although the selection signals for the output values of 1 are different from each other, the reverse combination is also possible.

[0081]

As described above, according to the first logic circuit invention, even if the driving force of the PMOS Tr is lowered due to miniaturization or the like, high speed operation can be realized and the operation margin can be easily secured. Thus, the capacity of the memory circuit can be increased.

Further, according to the second aspect of the invention, the output value with respect to the input value is <input value>, <input value +1>, <input value -1>, <0 (zero) depending on the combination of the two selection signals.
Speeding up the logic circuit that is one of the four
The circuit can be downsized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a sense amplifier circuit of the first invention.

FIG. 2 is a circuit diagram showing a configuration of an embodiment of a read circuit of the first invention.

FIG. 3 is a specification for a circuit of an embodiment of the second invention.

FIG. 4 is a circuit diagram showing an embodiment of the second invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional sense amplifier circuit.

FIG. 6 is a circuit diagram showing a configuration of a conventional read circuit.

FIG. 7 is a specification for a conventional address generation circuit.

FIG. 8 is a circuit diagram showing a conventional address generation circuit.

[Explanation of symbols]

 1 NMOS Tr 2 PMOS Tr 3 First CMOS Inverter 4 Second CMOS Inverter 5 Input Terminal of Sense Amplifier Circuit 6 Output Terminal of Sense Amplifier Circuit 7 Power Supply 8 Sense Amplifier Circuit 90, 91, 92 NMOS Tr 100, 101, 102 Read circuit input terminal 110, 111, 112 Read circuit control terminal 12 Read circuit output terminal 13 Read circuit 14 bit line 15 Memory cell C0, C1 selection signal I0, I1, I2 input signal O0, O1, O2 output signal

Claims (3)

[Claims] 1. A sense amplifier circuit comprising one NMOS transistor, one PMOS transistor, and first and second COMS inverters, wherein the sense amplifier circuit has one input terminal and one An output terminal, the input terminal is connected to one bit line drawn from one storage element, the gate and source electrodes of the one NMOS transistor are connected to the input terminal, and the drain electrode thereof is connected to a power supply. The gate, drain and source electrodes of the one PMOS transistor are respectively connected to the output terminal, the input terminal and a power supply, and the input and output terminals of the first CMOS inverter are the input terminal and the second CMOS, respectively. The input of the second CMOS inverter, which is connected to the input terminal of the inverter Logic circuit, wherein the pre-output terminal is connected to the output terminal and the output terminal of the first CMOS inverter, respectively. 2. A read circuit comprising a plurality of NMOS transistors and the sense amplifier circuit according to claim 1, wherein the read circuit comprises a plurality of input terminals, a plurality of control terminals and one output. Terminals, the plurality of input terminals are respectively connected to a plurality of bit lines drawn from a plurality of storage elements, and the gate and source electrodes of the plurality of NMOS transistors are respectively the plurality of control terminals. And the plurality of input terminals, the drain electrodes of which are commonly connected to the input terminal of the sense amplifier circuit according to claim 1, and the output terminal of the sense amplifier circuit according to claim 1 is connected to the output terminal. A logic circuit characterized by that. 3. A logic circuit in which an output value with respect to an input value becomes one of an input value, an input value +1, an input value -1, or 0 (zero) depending on a combination of two selection signals. Then, the two selection signals for the output value of the input value +1 are the same signal, and the two selection signals for the output value of the input value -1 are different combinations, or the two selection signals for the output value of the input value -1 are A logic circuit, wherein the two selection signals are the same signal, and the two selection signals corresponding to an output value of an input value + 1 are different combinations.