JPH05342877A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a malfunction caused by a coupling capacitance between signal lines by controlling the write operations to storage elements by a single signal line connected through a driving transistor. CONSTITUTION:When a write signal line W-bl is made high and a writing is performed, the potential of the line W-bl located on the negative side of a coupling capacitance C1 between the signal line W-bl and a read signal line R-blt is risen and the potential of the plus side signal line R-blt rises higher. On the other hand, in a coupling capacitance C2 between the signal line W-bl and a read signal line R-blc, the minus side signal line W-bl potential rises and therefore, the plus side signal line R-blc is risen higher. This, when the capacitances C1 and C2 vary, the signal level between the two signal lines R-blc and R-blt rises as a whole. However, the relative signal level difference between the two signal levels does not change. Thus, a malfunction caused by coupling capacitances C1 and C2 is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit in which writing and reading operations for a memory element are independently performed.

[0002]

2. Description of the Related Art A conventional example of this type of semiconductor memory circuit is shown in FIG.
Will be described. A semiconductor memory circuit 50 shown in FIG.
Is a CMOS-type storage element 51 having a flip-flop circuit configuration, and a pair of write signal lines for sending write signals to symmetrical nodes a and b of the storage element 51 via drive transistors 53 and 54 for writing operation, respectively. W-bl
t, W-blc and symmetrical nodes a and b of the storage element 51
To the pair of read signal lines R-blt and R- connected to the read signal lines through drive transistors 55 and 56 for read operation, respectively.
blc, a write word line WWL connected to the gates of the drive transistors 53 and 54, a read word line RWL connected to the gates of the drive transistors 55 and 56, and a pair of read signal lines R-blt, R.
-Blc and a differential sense amplifier 57 for detecting and amplifying the stored content of the storage element to be read out.

In the memory element 51, the connection point between the P-type transistor 61 and the N-type transistor 62 is a node a, the connection point between the P-type transistor 63 and the N-type transistor 64 is a node b, and these are complementary. And a flip-flop circuit configuration.

[0004]

When the integrated circuit becomes finer and the pitch between lines becomes narrower, the line capacitance becomes non-negligible, and the fluctuation of the signal of one signal line causes the signal of another signal line to change. May have an adverse effect. In the case of the semiconductor memory circuit 50 shown in FIG. 3, the write signal has a large amplitude and fully oscillates between the power supply and the ground. Therefore, the potential difference between the complementary signals is several volts. On the other hand, since the read signal is a signal stored in the storage element 51, its amplitude is small, and is usually several tens of millivolts to several hundreds of millivolts. Therefore, as shown in FIG. 3, when the write signal line and the read signal line are adjacent to each other, when the signal of the write signal line changes from the power supply voltage to the ground voltage or from the ground voltage to the power supply voltage, capacitive coupling occurs. An unintended current flows through the read signal line, which takes time to read or causes a malfunction.

FIG. 4 is an explanatory diagram showing coupling capacitance between signal lines of a conventional semiconductor memory circuit. The effect of the coupling capacitance of the conventional semiconductor memory circuit shown in FIG. 3 will be described in detail below also with reference to FIG. Conventional semiconductor memory circuit 5 shown in FIG.
At 0, the write word line WWL is set high and the read word line R is set as an initial state during the write operation.
It is assumed that WL is high, the write signal line W-blt is high, the write signal line W-blc is low, the read signal line R-blt is high, and the read signal line R-blc is low.

In this state, the write signal line W-blt
And the coupling capacitance Ct between the read signal line R-blt and
Since the potential level of the write signal line W-blt is higher than that of the read signal line R-blt, the write signal line W-blt side is positive and the read signal line R-blt side is negative, as shown in FIG. On the other hand, although the write signal line W-blc and the read signal line R-blc are both in the low state, the write signal line W-blc
4 is lower than the potential level of the read signal line R-blc, and as a result, the coupling capacitance Cc between the write signal line W-blc and the read signal line R-blc is as shown in FIG.
As shown in, the write signal line W-blc side is negative,
The read signal line R-blc side becomes positive.

In this state, when the write signal line W-blt is set to low and the write signal line W-blc is set to high to perform the write operation, the potential on the plus side of the coupling capacitance Ct decreases and the potential on the minus side also decreases. turn into. On the other hand, in the coupling capacitance Cc, the potential on the minus side rises, so that the potential on the plus side rises further. Therefore, the high signal of the read signal line R-blt becomes low, the low signal of the read signal line R-blc becomes high, and the signal levels of both may be reversed.

As described above, in the conventional semiconductor memory circuit 50, an unnecessary signal is generated due to the potential fluctuation of the coupling capacitors Cc and Ct during the read operation, and the signal stored in the memory element 51 cannot be accurately read. There is.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory circuit capable of preventing malfunction due to the influence of coupling capacitance between signal lines.

[0010]

In order to achieve the above object, the invention according to claim 1 is a semiconductor memory circuit having a memory element having a pair of load elements in a flip-flop circuit configuration, and A pair of read signal lines respectively connected to a pair of nodes and one node of the storage element are connected via a drive transistor having a drive capability equal to or higher than that of a storage operation transistor which constitutes the storage element. It has one write signal line and a drive transistor for write operation, which is connected between the other node of the storage element and a power supply and has a smaller drive capacity than the transistor for storage operation.

[0011]

The operation of the invention having the above-mentioned structure will be described below.
In this semiconductor memory circuit, when a write operation is performed on a memory element, one write signal line at one node of the memory element has a driving capability equal to or higher than that of a memory operation transistor included in the memory element. The storage element is connected through a drive transistor, and a drive transistor for write operation, which has a smaller drive capacity than the transistor for storage operation, is connected between the other node of the storage element and the power supply. It is possible to surely perform the low-to-high transition of one node and the high-to-low transition of the other node, and the signal line is composed of one write signal line and a pair of read signal lines.
With this configuration, each coupling capacitance between the signal lines raises or lowers the signal level of the two read signal lines together, and even if the coupling capacitance changes, the relative capacitance between the two read signal lines is increased. The difference in signal level does not change.

[0012]

EXAMPLES Examples of the present invention will be described in detail below. A semiconductor memory circuit 1 shown in FIG. 1 is a memory element in which transistors T1 and T2 for MIS type memory operation are connected to a flip-flop circuit configuration, and a pair of load elements 3 and 4 are connected as loads of the transistors T1 and T2. 2, a pair of read signal lines R-blt and R-blc connected to the pair of nodes a and b of the memory element 2 via read driving transistors 8 and 9, respectively, and one node of the memory element 2. One write signal line W-bl connected to a through a driving transistor 6 having a driving capacity equal to or higher than that of the transistor T1, and a source connected to a node b and a drain connected to a power supply Vc for memory operation. Drive transistor 7 having a smaller drive capacity than the transistor T2 of FIG. Word line WWL and the read word line RWL which is respectively connected to the gate of the drive transistor 8 and 9, a pair of read signal line R-blt, R
The differential sense amplifier 57 detects and amplifies the stored content of the storage element 2 read by -blc.

In the storage element 2, the connection point between the transistor T1 and the load element 3 is a node a, the connection point between the transistor T2 and the load element 4 is a node b, and these are connected complementarily to each other to form a flip-flop. It has a circuit configuration. Impedance elements such as resistors and capacitors, transistors, and the like can be used as the pair of load elements 3 and 4.

In the conventional circuit, the write operation is controlled by using the two transistors as described above, but in the present embodiment, the write operation is controlled by one transistor 6. Therefore, the transistor 6 has a larger drive capacity than the transistor T1. This is because the node a cannot be changed from low to high if the drive capability of the transistor 6 is smaller than that of the transistor T1.

FIG. 2 shows coupling capacitors C1 and C2 between the write signal line W-bl and the pair of read signal lines R-blt and R-blc. Next, the operation of the semiconductor memory circuit 1 described above will be described with reference to FIG. As the initial state during the write operation, the write word line W
It is assumed that WL is high, the read word line RWL is high, the write signal line W-bl is low, the read signal line R-blt is high, and the read signal line R-blc is low.

In this state, the coupling capacitance C1 between the write signal line W-bl and the read signal line R-blt has a potential level of the write signal line W-bl that is the read signal line R.
Since it is lower than the potential level of −blt, the write signal line W-bl side becomes negative and the read signal line R-blt side becomes positive, as shown in FIG. On the other hand, both the write signal line W-bl and the read signal line R-blc are in a low state, but the potential level of the write signal line W-bl is lower than the potential level of the read signal line R-blc,
As a result, the write signal line W-bl and the read signal line R
As shown in FIG. 2, the coupling capacitance C2 with −blc is negative on the write signal line W-bl side and read signal line R.
The -blc side becomes positive.

In this state, when the write signal line W-bl is set high and the write operation is performed, the negative potential of the coupling capacitance C1 rises and the positive potential rises further. On the other hand, in the coupling capacitance C2, the potential on the minus side rises, so that the potential on the plus side rises further. As a result, even if the coupling capacitances C1 and C2 change, the signal level between the two read signal lines R-blc and R-blt rises as a whole, but the relative signal level difference between the two signal levels is does not change. Therefore, the occurrence of malfunction due to the coupling capacitors C1 and C2 can be eliminated. Also, the coupling capacitance C1,
It is possible to reduce the deterioration of the operating margin and speed due to C2. The same applies to the case where the write signal line W-bl is set high while the write signal line W-bl is set low.

The writing operation is surely performed even if the load element 3 has impedance. Now node a
Is held high and the node b holds low, in order to rewrite it so that the node a holds low and the node b holds high, first, the write word line WWL is set to high and the write signal line W−. Bring bl low. As a result, the transistor 6 is turned on and the node a becomes low. When node a goes low, transistor T2 is open
It becomes F. Then, since the transistor 7 is turned on, the node b immediately becomes high, and the high of the node b is held by the power supply Vc via the load element 4 even if the transistor 7 is turned off. When the node b goes high, the transistor T1 turns on and the node a holds low because the resistance of the load element 3 is large.

Next, in order to rewrite the node a to hold high and the node b to hold high while the node a holds low and the node b holds high, the write word line WWL is first set to high. Then, the write signal line W-bl is set to high. As a result, the transistor 6 is turned on. Here, since the driving capability of the transistor 6 is the same as or greater than that of the transistor T1 as described above, the node a becomes high even if the transistor T1 is ON. This turns on the transistor T2. Then, since the driving capability of the transistor T2 is larger than that of the transistor 7, the node b becomes low even when the transistor 7 is ON. The node b is connected to the power supply Vc via the load element 4, but holds low because the resistance of the load element 4 is large and the transistor T2 is ON. When node b holds low, transistor T1 turns off and node a holds high.
Since the reading operation is the same as the conventional one, detailed description thereof will be omitted.

As described above, according to this embodiment, the write operation to the storage element 2 can be appropriately performed with only one write signal line W-bl. Further, according to the present embodiment, it is possible to eliminate the influence of the coupling capacitances C1 and C2 between the signal lines and prevent the malfunction. Furthermore, according to the present embodiment, the number of write signal lines is smaller than that of the conventional one, so that the degree of integration can be improved. Further, by forming impedance elements such as resistors and capacitors as the pair of load elements 3 and 4, the degree of integration can be further improved as compared with the case where transistors are used as the load elements 3 and 4.

The present invention is not limited to the above-described embodiments, but various modifications can be made within the scope of the gist thereof. For example, in the above embodiment, the write signal line W-b
The case where l is arranged between the memory element 2 and the read signal line R-blt has been described, but the write signal line W-b is described.
l may be arranged between the memory element 2 and the read signal line R-blc.

[0022]

As described above in detail, according to the present invention, since it has the above-mentioned structure, a malfunction due to the coupling capacitance is caused by a total of three signal lines, one write signal line and two read signal lines. Thus, it is possible to provide a semiconductor memory circuit capable of exhibiting stable operation without any trouble.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory circuit of the present invention.

FIG. 2 is an explanatory diagram showing a coupling capacitance between signal lines in the first embodiment.

FIG. 3 is a circuit diagram showing a conventional semiconductor memory circuit.

FIG. 4 is an explanatory diagram showing a coupling capacitance between signal lines of a conventional semiconductor memory circuit.

[Explanation of symbols]

 1 semiconductor memory circuit 2 memory element 3 load element 4 load element 6 drive transistor 7 drive transistor W-bl write signal line R-blt read signal line R-blc read signal line

Claims (2)

[Claims] 1. A semiconductor memory circuit having a memory element having a pair of load elements in a flip-flop circuit configuration, and a pair of read signal lines respectively connected to a pair of nodes of the memory element, and one of the memory elements. Between a single write signal line connected to a node via a drive transistor having a drive capability equal to or higher than that of a transistor for memory operation constituting this memory element, and the other node of the memory element and a power supply. And a drive transistor for write operation having a smaller drive capacity than the transistor for storage operation connected to the semiconductor storage circuit. 2. The semiconductor memory circuit according to claim 1, wherein the read signal line is connected to the node via a switching element.