JPH05342854A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device in which a high integration can be attained, and a reading error can not be generated. CONSTITUTION:This device is equipped with a sense amplifier 20lB which amplifies a potential difference between a first node SN2 of a sense amplifier 201B with which a first bit line BL21 is connected through a first switch 16, and a second node #SN2 of the sense amplifier 201B with which a second bit line BL12 is connected through a second switch 11. At the time of activating the sense amplifier 201B, the first and second bit lines BL21 and BL12 are separated from the first and second nodes SN2 and #SN2. At the time of transferring the amplified result, the second node #SN2 of the sense amplifier 201B is turned to a floating state at first the first node SN2 is connected with the bit line BL21, and the amplified result is transferred to the bit line BL21. Then, the second node #SN2 is connected with the second bit line BL12, and the amplified result is transferred to the bit line BL12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 1 shows, for example, IEEE JOURNAL OF SOLID-ST.
ATE CIRCUITS, VOL SC-15, NO.5, OCTOBER 1980 P846 ~
It is a typical block diagram of the conventional semiconductor memory device described in P854. An n-type MOSFET is provided between the bit line BL ₁ (BL ₂ , BL _m ) and the inverted bit line # BL ₁ (# BL ₂ , # BL _m ).
(Hereafter nMOS) 65 (67,69) and 66 (68,70) series circuit and p-type MOSFET (hereafter pMOS) 71 (73,75) and 72 (74,7)
Series circuits with 6) are inserted respectively. nMOS65 (67,69)
And 66 (68, 70) are commonly connected to the n-type sense amplifier drive line SD _n . pMOS71 (73,75) and 72 (74,76)
The common connection part with is connected to the p-type sense amplifier drive line SD _p . The n-type sense amplifier drive line SD _n (p-type sense amplifier drive line SD _p ) is connected to the ground portion V through the nMOS89 (pMOS90).
_It is connected to _SS (power supply V _CC ).

The bit line BL ₁ (BL ₂ , BL _m ) is an nMOS 53 (55,
57) is connected to the memory cell capacitors 77 (79, 81), and the gates of the nMOSs 53, 55, 57 are connected to the word line W ₁₁ . In addition, bit line BL ₁ (BL ₂ , BL _m ) is nMOS54
The memory cell capacitors 78 (80, 82) are connected via (56, 58), and the gates of the nMOSs 54, 56, 58 are connected to the word line W _1n .

The inverted bit line #BL ₁ (#BL ₂ , #BL _m ) is
Memory cell capacitor 83 (85,8,8) via nMOS59 (61,63)
7), and the gates of the memory cell capacitors 59, 61, 63 are connected to the word line W ₂₁ . The inverted bit line _{#BL 1 (#BL 2, #BL m} ) is connected to the memory cell capacitor 84 (86, 88) via the NMOS 60 (62, 65), nMOS
The gates of 60, 62 and 64 are connected to the word line W _2n . nM
OS53 (55,57,54,56,58) and memory cell capacitor 77 (79,8
1,78,80,82) and memory cell MC ₁₁₁ (MC ₁₁₂ , M
C _11m , MC _1n1 , MC _1n2 , MC _1nm ). In addition, nMOS59 (61,63,60,62,64) and memory cell capacitor 83 (8
5,87,84,86,88) and memory cell MC ₂₁₁ (MC ₂₁₂ , MC
_21m , MC _2n1 , MC _2n2 , MC _2nm ). Parasitic capacitance C _s111 is in the vicinity of the intersection of the bit lines _{BL 1, BL 2, BL m} , the word line W ₁₁ and _{(W 1n), C s112,} C s11m (C s1n1,
C _s1n2 , C _s1nm ) exist. Inverted bit line #B
_{L 1, # BL 2, #} BL m is near the intersection between the word line W ₂₁ (W _2n) parasitic capacitance _{C s211, C s212, C s21m} (C s2n1,
C _s2n2 , C _s2nm ) exist. In this manner, n × m memory cells are arranged in rows and columns in the memory cell arrays 89 and 90, respectively.

Next, the memory cell MC of this semiconductor memory device
_When the word line W ₁₁ is selected when ₁₁₁ stores “H” and the memory cells MC ₁₁₂ and MC _11m store “L”, the read operation of the memory cells MC ₁₁₁ , MC ₁₁₂ and MC _11m is performed. Figure 2
It will be described together with the timing chart.

The bit lines BL ₁ , BL ₂ , BL _m and the inverted bit lines #BL ₁ , #BL ₂ , #BL _m are 1/2 of the voltage of the power supply V _CC.
When the word line W ₁₁ rises as shown in FIG. 2 (a) at the time t ₁ while precharged to 1/2 V _CC , the bit line
BL ₁ respectively to, BL _2, BL _m "H" and "L", data of "L" is read. Next, at time t ₂ , the activation signal φ _{n is set} to “H” and the activation signal φ _{p is set} to “L” as shown in FIGS.
When set to, the sense amplifier is activated and bit lines BL ₂ and BL
_m to "L", the inverted bit line #BL _2, #BL _m becomes "H".

This potential change is caused by the bit lines BL ₁ , BL ₂ , BL _m
Parasitic capacitance C _s111 , C _s112 , C between the word line and the word line W _11
By capacitive coupling by _s2nm , word lines W ₁₁ , W ₁₂ , W
_As shown in Fig. 2 (e), _1n has negative noise LN and word line W
Positive noise PN is induced in ₂₁ , W ₂₂ , and W _2n as shown in FIG. 2 (f). These word lines W ₁₁ , W ₁₂ , W _1n and W
The potential changes of ₂₁ , W ₂₂ , W _{2n depend on} the bit lines BL ₁ , BL ₂ , BL _m
And the inverted bit lines #BL ₁ and #BL ₂ #BL _m are capacitively coupled to the bit line BL ₁ and negative noise is applied to the inverted bit line #BL ₁ as shown in FIG. 2B. Induces positive noise.
Since this noise is the opposite of the original read data,
As shown in (b), the amplification of the bit line BL ₁ and the inverted bit line #BL ₁ fails, the bit line BL ₁ is “L”, and the inverted bit line #BL 1
₁ becomes "H".

[0008]

As described above, in the conventional semiconductor memory device, the capacitive coupling by the parasitic capacitance between the bit line BL and the inversion bit line and the word line causes the coupling between the bit lines with the word line interposed. Since ring noise is induced, if the capacity of the memory cell capacitor becomes small due to high integration, malfunction will occur more easily. Therefore, in order to solve such a problem, conventionally, for example, IEEE JOU
RNAL OF SOLID-STATE CIRCUITS VOL. SC-15, NO.5, OCT
A folded bit line configuration is proposed in OBER 1980 P846 to P854, but it is necessary to arrange two word lines in a 1-bit memory cell area and one word line in a 1-bit memory cell area. The area of the memory cell becomes larger than that of the open bit configuration of FIG.

In view of the above problems, it is an object of the present invention to provide a semiconductor memory device which can be highly integrated and in which a read error due to coupling noise does not occur.

[0010]

A semiconductor memory device according to a first aspect of the present invention includes a first node connected to a first data line via a first switch, a second data line and a second node. First, second, third, and fourth one-conductivity-type transistor groups connected in series and first, second, and third connected in series with a second node connected via a switch. , A fourth group of other conductivity type transistors are respectively interposed, and the gates of the first one conductivity type transistor and the first other conductivity type transistor are connected to the second node, and the fourth one conductivity type transistor and the fourth one conductivity type transistor.
The gate of the other conductivity type transistor is connected to the first node, and the sense amplifier is activated in the common connection part of the second and third one conductivity type transistors and the common connection part of the second and third other conductivity type transistors. A signal is provided with a sense amplifier configured to give a complementary signal to the gates of the second and third one conductivity type transistors and the gates of the second and third other conductivity type transistors.

A semiconductor memory device according to a second invention is connected to a first node connected to a first data line via a first switch, and to a second data line connected to a second switch. The first, second, third and fourth one conductivity type transistor groups connected in series and the first, second, third and fourth other conductivity connected in series with the second node. Type transistor groups are respectively interposed, the gates of the second one conductivity type transistor and the second other conductivity type transistor are connected to the second node, and the third one conductivity type transistor and the third other conductivity type transistor are connected. The gate of the type transistor is connected to the first node, and the sense amplifier activation signal is supplied to the common connection portion of the second and third one conductivity type transistors and the common connection portion of the second and third other conductivity type transistors, Gates of first and fourth one conductivity type transistors and first To configure comprising a sense amplifier that is to give a signal complementary to the gate of the fourth opposite conductivity type transistor.

[0012]

The data read out to the first and second data lines is transferred to the first and second sense amplifiers via the first and second switches.
To the node. First and second nodes and first and second nodes
The data line is separated from the data line to activate the sense amplifier to amplify the potential difference between the first node and the second node.
The potentials of the first and second nodes are fixed by the one conductivity type transistor group and the other conductivity type transistor group. The amplified data of the sense amplifier is supplied to the first data line by connecting the first node to the first data line by first floating the second node and charging the first data line.
Then, connect the second node to the second data line to
To charge the second data line. As a result, the data line is not affected by the coupling noise when the sense amplifier is activated and when the amplified data is transferred.

[0013]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. 3 and 4 show the configuration of a semiconductor memory device according to the present invention, and are schematic configuration diagrams in the case where a shared sense amplifier is applied.

The node SN ₁ (SN of the sense amplifier 201A (201B)
₂ ) is bit line BL ₁₁ (BL ₂₁ ) via nMOS6 (nMOS16)
Connected with. The node SN ₃ of the sense amplifier 201C is nM
It is connected to OS302. The inversion node #SN ₁ of the sense amplifier 201A is connected to the nMOS 301. Bit line BL ₁₂
(BL ₂₂ ) is the sense amplifier 201B (201C) via nMOS11 (21)
Connected to the reverse node # SN ₂ (# SN ₃ ). nMOS
The gate of 301 (6) is connected to the block selection signal line φ _1R (φ _1R ). A series circuit of nMOSs ₁ , 2, 3, 4 and pMOSs 28, 29, 30, 3 are provided between the node SN ₁ and the inversion node #SN _1.
The serial circuits of 1 are provided respectively, and the read / write / equalize circuit 202A is also provided. The gate of nMOS1 (4) is connected to the inverting node #SN ₁ (node SN ₁ ). The common connection between the nMOSs 2 and 3 is connected to the n-type sense amplifier drive line SD _nA , and the n-type sense amplifier drive line SD _nA
Is connected to the ground portion V _SS via the nMOS 5. nMOS2
The gate is connected to the power supply line SL _A, the power supply line SL _A power supply V
_It is connected to _CC and the gate of the nMOS 3 is connected to the clock signal line φ ₁₂ . The gate of pMOS28 (31) is the inverting node #SN.
_It is connected to ₁ (node SN ₁ ). The common connection between the pMOSs 29 and 30 is connected to the p-type sense amplifier drive line SD _pA , and the p-type sense amplifier drive line SD _pA is connected to the power supply V _CC via the pMOS 27. The gate of pMOS 30 is connected to the clock signal line φ _13, and the gate of pMOS 29 is the ground line V _EA.
Is connected to the ground portion V _SS . And nMOS
A sense amplifier 201A is configured by 1, 2, 3, 4 and pMOSs 28, 29, 30, 31.

The bit line BL ₁₁ is connected to the memory cell capacitor 44 (45) through the nMOS 7 (8),
BL ₁₂ is a memory cell capacitor 46 (47) via nMOS 9 (10)
Connected with. The gates of nMOS 7 and 9 are word lines W ₁₁
The gates of the pMOSs ₈ and ₁₀ are connected to the dummy word line DW ₁ . The nMOS 7 (9) and the memory cell capacitor 44 (46) form a memory cell MC ₁₁₁ (MC ₁₁₂ ), and the nMOS 8 (10) and the memory cell capacitor 45.
The dummy cell DMC ₁₁ (DMC ₁₂ ) is constituted by (47). These memory cells MC ₁₁₁ , MC ₁₁₂ and dummy cell D
A memory cell array 42 is constituted by the MC ₁₁ and the DMC ₁₂ . The block selection signal line φ _2L is connected to the gate of the nMOS 11.

Between the node SN ₂ of the sense amplifier 201B and the inverting node #SN ₂ , a series circuit of nMOSs 12, 13, 14, 15 and
A series circuit of pMOSs 33, 34, 35, 36 is provided respectively, and a read / write / equalize circuit 202B is provided. nM
The gate of OS12 (15) is connected to the inverting node #SN ₂ (node SN ₂ ). the common connection portion of nMOS13 and 14 are connected to the sense amplifier drive line SD _nB, sense amplifier drive line SD _nB is
It is connected to the ground portion V _SS via the nMOS 52. nMOS13 (1
The gate of 4) is connected to the clock signal line φ ₂₁ (φ ₂₂ ). The gate of pMOS33 (36) is the inverting node #SN ₂ (node
SN ₂ ). The common connection between the pMOSs 34 and 35 is connected to the p-type sense amplifier drive line SD _pB, and the p-type sense amplifier drive line SD _pB is connected to the power supply V _CC via the pMOS 32.

The gate of the pMOS 34 (35) is a clock signal line φ _24.
(Φ ₂₃ ). The gate of the nMOS 11 (16) is connected to the block selection signal line φ _2L (φ _2R ). And
The nMOS 12, 13, 14, 15 and the pMOS 33, 34, 35, 36 form a sense amplifier 201B. Bit line BL ₂₁ is nMOS 17 (19)
The bit line BL ₂₂ is connected to the memory cell capacitor 50 (51) through the nMOS 18 (20). The gates of the nMOSs ₁₇ and ₁₈ are connected to the word line W _21, and the gates of the nMOSs ₁₉ and ₂₀ are connected to the dummy word line DW ₂ . With the nMOS 17 (18) and the memory cell capacitor 48 (50), the memory cell MC ₂₁₁ (M
C ₂₁₂₎ is, NMOS 19 (20) and the memory cell capacitor 49 (51)
And form a dummy cell DMC ₂₁ (DMC ₂₂ ).
A memory cell array 43 is configured by the memory cells MC ₂₁₁ and MC ₂₁₂ and the dummy cells DMC ₂₁ and DMC ₂₂ .

A read / write / equalize circuit is provided between the node SN ₃ of the sense amplifier 201C and the inversion node #SN _3.
202C is inserted, nMOS22,23,24,25 series circuit and pMOS
37,38,39,40 series circuits are inserted respectively. nMOS22
The gate of (25) is connected to the inverting node #SN ₃ (node SN ₃ ). The common connection between the nMOSs 23 and 24 is connected to the n-type sense amplifier drive line SD _nC, and the n-type sense amplifier drive line SD
_nC is connected to the ground portion V _SS via the nMOS 26. nMOS
The gate of 23 (24) is connected to the clock signal line φ ₃₁ (power supply line SL _C ). The power supply line SL _C is connected to the power supply V _CC . The common connection between pMOS 38 and 39 is connected to the p-type sense amplifier drive line SD _pC , and the p-type sense amplifier drive line SD _pC
Is connected to the power supply V _CC through pMOS41. The gate of the pMOS 38 (39) is connected to the clock signal line φ ₃₄ (ground line V _EC ). The ground line V _EC is connected to the ground portion V _SS . The nMOSs 22,23,24,25 and the pMOSs 37,38,39,40 constitute a sense amplifier 201C. In the memory cell arrays 42 and 43, n × m memory cells and m dummy cells are arranged in a matrix, but in FIG. 3 and FIG.
The memory cells in the rows and the dummy cells are shown in only two columns.

Next, the memory cell MC of this semiconductor memory device
_{When 111} stores "H" and MC ₁₁₂ stores "L",
The operation when the word line W ₁₁ is selected will be described with reference to the timing charts of the signals of the respective parts shown in FIG. 5 (solid line side) and FIG.

Bit lines BL ₁₁ , BL ₁₂ , BL ₂₁ , BL ₂₂ and node SN ₁ of sense amplifier 201A, inverted node #SN ₁ , node SN ₂ of sense amplifier 201B, inverted node #SN ₂ , node of sense amplifier 201C The SN ₃ and the inversion node #SN ₃ are precharged in advance to 1 / 2V _CC which is 1/2 of the voltage of the power supply V _CC .

Now, at time t ₁ , the word line W ₁₁ is changed to the one shown in FIG. 5 (D).
As shown in, the memory cells MC ₁₁₁ and MC ₁₁₂ rise to “H”.
There is selected, the data of "H" to the bit line BL ₁₁ can be data read "L" to the bit line BL ₁₂ increases the potential of the bit line BL _11, the potential of the bit line BL ₁₂ is lowered But,
Since the clock signals φ _1R and φ _2L are “H” as shown in FIGS. 5E and 5F, the nMOSs 6 and 11 are both turned on, the potential of the node SN ₁ rises, and the inversion node #SN ₂ The potential drops. Dummy word line at the same time as the potential of word line W ₁₁ rises
The potential of DW ₁ drops as shown in FIG. 5 (B), which has the effect of canceling the coupling noise between the word line W ₁₁ and the bit lines BL ₁₁ and BL ₁₂ .

Next, at time t ₂ , the clock signals φ _1R , φ _2L ,
φ _2R and φ _3L are set to “L” as shown in FIGS. 5E, 5F, 5Q and 5R to disconnect the bit line BL ₁₁ from the sense amplifier 201A. The nMOS 302 provided on the sense amplifier 201C side at the right end is a dummy transistor for balancing the parasitic capacitance existing between the word line and the bit line.

At the time point t ₃ , the clock signals φ _1p and φ _2p are _output as shown in FIG.
Clock signals φ _1n and φ _2n are set to “L” as shown in (G) and (I).
Is set to “H” as shown in FIGS. 5 (H) and (J) to turn on the nMOSs 5 and 52 to activate the sense amplifiers 201A and 201B, and
The potential difference between SN ₁ and the inversion node #SN ₁ and the potential difference between the node SN ₂ and the inversion node #SN ₂ are amplified.

At this time, the node SN ₁ and the inverted node #SN ₁
Since the node SN ₂ and the inversion node #SN ₂ are separated from the bit line BL ₁₁ and the bit line BL ₁₂ , the coupling noise between the bit lines via the word line, such as in the case of the open bit line, is eliminated. Sense amplifiers 201A and 201B without being affected
Is stably amplified, and the potential differences between the node SN ₁ and the inverting node #SN ₁ and between the node SN ₂ and the inverting node #SN ₂ become large as shown in FIGS. 6 (A) and 6 (B).

Next, the amplified data is transferred to the bit lines BL ₁₁ and BL ₁₂
When the data is transferred to the memory cell and rewritten to the memory cell, first, at time t ₄ , the clock signal φ _{13 is changed} to “H” and the clock signal φ _{12 is changed} to “L” as shown in FIGS. 5 (L) and 5 (K). , Fig.5 (M), (P)
Clock signal φ _{21 is set} to “L” as shown in
_{24 is set} to “H” to hold the potentials of the inversion node #SN ₁ and the node SN ₁ .

Next, at time t ₅ , both the clock signals φ _1R and φ _2L are set to “H” as shown in FIGS.
₁ is connected to the bit line BL ₁₁ , and the inversion node #SN ₂ is connected to the bit line BL ₁₂ . Bit line BL ₁₁ has inverted node #SN
_{Since 1} is "L", it is charged to "H" through the path of pMOS29,28. Further, since the node SN ₂ is “H”, the bit line BL ₁₂ is discharged to “L” in the path of the nMOSs 15 and 14. At this time, as in the open bit line configuration, noise LN, PN due to capacitive coupling between the bit lines with the word lines interposed is shown in FIG.
It occurs as shown in (B), but the reverse node #SN ₁ and the node
The potential of SN ₂ is nMOS3, pMOS30 and nMOS13, pMOS34, nMOS
Since 16 is off, the inversion node #
The potential of SN ₁ and node SN ₂ does not change, and bit lines BL ₁₁ and BL
Data is rewritten to ₁₂ in a stable manner, as shown in FIG.
As shown in (D), the bit line BL ₁₁ becomes “H”, and the bit line BL ₁₂
There becomes "L", the memory cell MC ₁₁₁ is "H", the memory cell MC ₁₁₂ is data in the "L" is rewritten.

At time t _6, after the clock signal φ ₁₂ becomes “H” and the clock signal φ ₁₃ becomes “L” as shown in FIGS. 5 (K) and 5 (L), the clock signal φ _{2R is changed} to FIG. 5 (Q). as shown in) becomes the "H" bit line BL ₂₁ is charged to "H". Bit line BL
When charging ₂₁ , the coupling noise between the bit lines via the word line is generated as in the case of the open bit line configuration, but the potential of the inversion node #SN ₂ is completely “L”, Further, since the capacitance of the bit line BL ₁₂ connected to it is large, there is no erroneous operation in which the potentials of the bit lines BL ₁₂ and BL ₂₁ are inverted due to the generated noise.

At time t ₈ , the word line W as shown in FIG.
₁₁ fall point, at time t ₉ the clock signal phi _1p, figure phi _2p 5
Set both to "H" as shown in (G) and (I), and clock signal φ
_1n and φ _2n are both set to “L” as shown in FIGS. 5 (H) and 5 (J) to deactivate the sense amplifiers 201A and 201B. And time t
Bit lines _{10 BL 11, BL 12, BL} 21, BL 22 and node SN _1, S
N ₂ and inverted nodes #SN ₁ and #SN ₂ are shown in FIG. 6 (C), (D), (E), (F).
And as shown in (A) and (B), it is 1/2 of the voltage of the power source V _CC.
Set to / 2 V _CC .

When the memory cell MC ₂₁₁ stores "H" and the memory cell MC ₂₁₂ stores "L", the word line W
_{When 21} is selected, the operation is as shown in the timing chart of the signals on the broken line side in FIG. 5 and each part shown in FIG. 7, and the operation in this case is the same as when the word line W ₁₁ is selected.

FIG. 8 is a schematic diagram showing an example of the read / write / equalize circuit 202A (202B, 202C) shown in FIGS. 3 and 4. Node _{SN 1 (SN 2, SN 3} ) and inverting node _{#SN 1 (#SN 2, #SN 3} ) between the, NMOS 101 and
A series circuit of nMOS99 and 100 is provided respectively. nMOS
Each gate of 99, 100, 101 is connected to the equalize signal line BLEQ. The common connection between nMOS99 and 100 is connected to the precharge potential line PCV. The read signal line O is nMOS91
When through the series circuit is connected to the ground portion V _SS and 93, the gate of nMOS93 is connected to the node _{SN 1 (SN 2, SN 3} ).

The inverted read signal line #O is connected to the ground portion V _SS via a series circuit of nMOS 92 and 94, and the gate of the nMOS 94 is connected to the inverted node #SN ₁ (#SN ₂ , #SN ₃ ). Has been done. The write signal line I is connected to the node SN ₁ (SN ₂ , SN ₃ ) via a series circuit of nMOS 95 and 97. The inverted write signal #I is connected to the inverted node #SN ₁ (#SN ₂ , #SN ₃ ) via the series circuit of the nMOSs 96 and 98.
The gates of the nMOSs 97 and 98 are connected to the word line W.
The gates of the nMOSs 91, 92, 95, 96 are connected to the column selection signal line Y.

This read / write / equalize circuit 202A
The equalizing operation of (202B, 202C) is performed at time t ₁₀ shown in FIG.
In when the equalize signal BLEQ to "H", reading, programming, if the equalizing circuit 202B, the bit line BL _12, which is charged to the bit line is charged to the "H" BL ₂₁ and "L" nM
Shorted by OS101, bit lines BL ₂₁ and BL ₁₂ are about 1 / 2V
_Charged to _CC . The deviation of 1/2 of the voltage of the power supply V _CC of the bit lines BL ₂₁ and BL ₁₂ from 1/2 V _CC causes the voltage of the bit lines BL ₂₁ and BL ₁₂ to pass through the nMOS 99, 100 and the precharge potential line PCV. It is corrected by connecting to a precharge power source (not shown) of 1/2 V _CC .

In the case of the read / write / equalize circuit 202A, the bit line BL ₁₁ , the node SN ₁ of the sense amplifier 201A, and the inversion node #SN ₁ are charged by the precharge power source of voltage 1/2 V _CC through the nMOS 99,100. To be done. Since the nMOS 101 is turned on, the node SN ₁ and the inversion node #SN ₁ have the same potential. Read / write / equalize circuit 202B is a bit line
About 1/2 V _CC could be generated by short-circuiting BL ₂₁ and BL ₁₂ , but read, write and equalize circuits
202A will be charged to a voltage of 1/2 V _CC by the nMOS 99,100. Therefore, read, write, equalize circuit
If the channel width of nMOS99,100 of 202A is larger than the channel width of read / write / equalize circuit 202B,
Equalize operation becomes faster. Note that reading, writing,
The operation of the equalize circuit 202C is similar to that of the read, write, and equalize circuit 202A.

[0034] Then the data read operation is performed by once in the time t ₁ shown in FIG. 5 the word line W is selected a column selection signal line Y to "H". When the node SN ₁ of the sense amplifier 201A is higher (lower) than the inversion node #SN ₁ , a larger (smaller) current than the inverted read signal line #O flows through the read signal line O, so this current difference is detected. To read.

The write operation is performed, for example, at time t ₇ shown in FIG.
By setting the word line W to "H" and the column selection signal line Y to "H", the write signal line I and the inverted write signal line #
I data is transferred to the node SN ₁ (SN ₂ , S of the sense amplifier).
N ₃ ), the inversion node #SN ₁ (#SN ₂ , #SN ₃ ) and the bit line.

The semiconductor memory device shown in FIGS. 3 and 4 can be controlled by the timing chart of the signals of the respective parts shown in FIG. The timing chart shown in FIG. 9 will be described. When the memory cell array 42 is selected, it changes as shown by a solid line, and when the memory cell array 43 is selected, it changes as shown by a broken line.

At time t ₁ , as shown in FIG. 9D, the word line W
When ₂₁ becomes "H", the dummy word line DW _1, as shown in FIG. 9 (B) is "L", to cancel the coupling noise of the word lines and bit lines.

Next, at time t ₂ , the clock signals φ _1R , φ _2L , φ _2R and φ _3L become “L” as shown in FIGS. 9 (E), (F), (Q), and (R), and the bits are changed. Separate the line from the sense amplifier. Figure 9 (H) at time t _3, the clock signal as shown in (J) φ _1n, φ the _2n to "H", Fig. 9 (G), the clock signal phi _1p as shown in (I)
, φ _{2p is set} to “L” to activate the sense amplifiers 201A and 201B to amplify the potential difference between the node SN ₁ and the inversion node #SN ₁ and the potential difference between the node SN ₂ and the inversion node #SN ₂ . At time t ₄ , the clock signal φ _{12 is set} to “L” as shown in FIG. 9 (K).
Then, as shown in FIG. 9 (L), set the clock signal φ ₁₃ to “H”,
Set the clock signal φ ₂₁ to “L” as shown in FIG.
As shown in (P), the clock signal φ _{24 is set} to “H” and the nMOS
3, pMOS 30 and NMOS 13, PMOS 34 turns off the by fixing the potential of the inverting node #SN ₁ and node SN _2.

At the time point t ₅ , the clock signals φ _1R and φ _2L are shown in FIG.
As shown in (E) and (F), the nMOSs 6 and ₁₁ are both turned to "H" to turn on the bit lines BL ₁₁ and BL ₁₂ , and the inversion nodes #SN ₁ and
Charges and discharges according to the potential of node SN ₂ . As a result, the initially stored data is rewritten in the memorial cell. At time t ₆ , the clock signal φ _{12 is changed} to “H” as shown in FIG. 9 (K), the clock signal φ _{13 is changed} to “L” as shown in FIG. 9 (L), and the clock signal φ _{21 is changed} to FIG. 9 (M). By setting the clock signal φ ₂₄ to “H” and the clock signal φ ₂₄ to “L” as shown in FIG. 9 (P), the sense amplifiers 201A and 201B are returned to the ON state.

At time t ₁₁ , the clock signal φ _1p is “H” as shown in FIG. 9 (G), and φ _1n is “L” as shown in FIG. 9 (H), φ
_{2p is set} to “H” as shown in FIG. 9 (I) and φ _{2n is set} to “L” as shown in FIG. 9 (J) to deactivate the sense amplifiers 201A and 201B. At time t ₁₂ , the clock signals φ _2R and φ _3L are _supplied to FIGS. 9 (Q) and (R).
The bit line is set to "H" as shown in, and the read / write / equalize circuit 202B is activated.
The potentials of BL ₂₁ , BL ₂₂ and the node SN ₂ of the sense amplifier 201B and the inversion node #SN ₂ are equalized to 1/2 V _CC .

The operation when the word line W ₂₁ becomes "H" at time t ₁ is as shown by the broken line in FIG. 9, and the operation is the same as that described above. Figure 10 shows a sense amplifier
It is a block diagram which shows the other Example of 201A (201B, 201C). Node SN ₁ (SN ₂ , SN ₃ ) and inverted node #SN ₁ (# SN ₂ ,
#SN ₃ ), a series circuit of nMOS 191, 192, 193, 194 and a series circuit of pMOS 197, 198, 199, 200 are respectively interposed. The gate of nMOS192 is the inverting node # SN ₁ (# SN ₂ , #
SN ₃ ) and the gate of nMOS193 is connected to node SN ₁ (SN
₂ , SN ₃ ). the common connection portion between the nMOS192 and 193 is connected to the n-type sense amplifier drive line SD _n, it is connected to a ground portion V _SS via the n-type sense amplifier drive line SD _n nMOS195. The gate of the nMOS 191 is connected to the clock signal line φ _i1 and the gate of the nMOS 194 is connected to the clock signal line φ _i2 .

The gate of pMOS198 is the inverting node #SN ₁ (#
SN ₂ , # SN ₃ ) and the gate of pMOS199 is a node
It is connected to SN ₁ (SN ₂ , SN ₃ ). pMOS198 and 199
The common connection portion with and is connected to the p-type sense amplifier drive line SD _p, and the p-type sense amplifier drive line SD _p is connected to the power supply V _CC via the pMOS 196. pMOS197 is clock signal line φ
_i4 and pMOS200 are connected to the clock signal line φ _i3 . The clock signal line φ _in is connected to the pMOS
The clock signal line φ _ip is connected to the gate of 196.

Instead of the clock signal lines φ _in , φ _ip , φ _i1 , φ _i2 , φ _i3 , and φ _i4 connected to this sense amplifier, the clock signal lines φ connected to the sense amplifier shown in FIGS. _1n , φ _1p , power supply line V _CC , clock signal line φ ₁₂ ,
φ ₁₃ , ground line V _EA or clock signal line φ _2n , φ _2p ,
φ ₂₁ , φ ₂₂ , φ ₂₃ , φ ₂₄ or clock signal line φ _3n ,
Even if φ _3p , the power supply line V _CC , the ground line V _EC , and the clock signal line φ ₃₄ are connected, the same operation as that of the sense amplifier shown in FIGS. 3 and 4 is obtained, and the same effect is obtained.

[0044]

As described above in detail, according to the present invention, since the bit line is not affected by the coupling noise due to the parasitic capacitance existing between the word line and the bit line, the memory is not affected. Even if the capacity of the memory cell is reduced by arranging only one word line in the cell area to increase the degree of integration, the data read / write operation is stable and no read / write error occurs. .. As a result, the present invention has an excellent effect that a read / write error does not occur and a semiconductor memory device that can be highly integrated can be provided.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a conventional semiconductor memory device.

FIG. 2 is a timing chart of signals of respective parts of the conventional semiconductor memory device.

FIG. 3 is a half of a schematic configuration diagram of a semiconductor memory device according to the present invention.

FIG. 4 is a half part of a schematic configuration diagram of a semiconductor memory device according to the present invention.

FIG. 5 is a timing chart of signals of respective parts of the semiconductor memory device according to the present invention.

FIG. 6 is a timing chart showing potential changes of bit lines and nodes when a word line W ₁₁ is selected.

FIG. 7 is a timing chart showing potential changes of bit lines and nodes when the word line W ₂₁ is selected.

FIG. 8 is a schematic configuration diagram of a read / write / equalize circuit.

FIG. 9 is another timing chart of signals of respective parts of the semiconductor memory device according to the present invention.

FIG. 10 is a schematic configuration diagram showing another embodiment of the sense amplifier.

[Explanation of symbols]

1,2,3 to 26,301,302 nMOSFET 27,28,29 to 41 pMOSFET 44,45 to 51 Memory cell capacitor 201A, 201B, 201C Sense amplifier 202A, 202B, 202C Read, write, equalize circuit BL ₁₁ , BL ₁₂ , BL ₂₁ , BL ₂₂ bit line W _11, W ₂₁ word lines DW _1, DW ₂ dummy word line SN _1, SN _2, SN ₃ node #SN _1, #SN _2, #SN ₃ inverting node MC _111, MC _112, MC ₂₁₁ , MC ₂₁₂ Memory cell DMC ₁₁ , DMC ₁₂ , DMC ₂₁ , DMC ₂₂ Dummy cell SD _nA , SD _nB , SD _nC n type sense amplifier drive line SD _pA , SD _pB , SD _pC p type sense amplifier drive line SL _A , SL _C power line _{φ 12, φ 13, φ 21} , φ 22, φ 23, φ 24, φ 31 clock signal line _{φ 1R, φ 2L, φ 2R} , φ 3L, φ 3R clock signal line

Claims (2)

[Claims] 1. A semiconductor memory device comprising a sense amplifier for amplifying a potential difference between a first data line and a second data line, wherein the sense amplifier includes the first switch via the first switch. Connected in series between the first node connected to the second data line and the second node connected to the second data line via the second switch. The third and fourth one conductivity type transistor groups and the first, second, third and fourth other conductivity type transistor groups connected in series are respectively interposed, and the first one conductivity type transistor and the first one conductivity type transistor group are provided. The gate of the other conductivity type transistor is connected to the second node, the gates of the fourth one conductivity type transistor and the fourth other conductivity type transistor are connected to the first node, and the second and third one conductivity type transistors are connected. Type transistor common connection and second and third other conductivity type transistors The sense amplifier activation signal is supplied to the common connection portion of the transistors, and the complementary signals are supplied to the gates of the second and third one conductivity type transistors and the gates of the second and third other conductivity type transistors. A characteristic semiconductor memory device. 2. A semiconductor memory device comprising a sense amplifier for amplifying a potential difference between a first data line and a second data line, wherein the sense amplifier is the first switch via a first switch. Connected in series between the first node connected to the second data line and the second node connected to the second data line via the second switch. The third and fourth one conductivity type transistor groups and the first, second, third and fourth other conductivity type transistor groups connected in series are respectively interposed, and the second one conductivity type transistor and the second one conductivity type transistor group are provided. The gate of the other conductivity type transistor is connected to the second node, the gates of the third one conductivity type transistor and the third other conductivity type transistor are connected to the first node, and the second and third one conductivity type transistors are connected. Type transistor common connection and second and third other conductivity type transistors The configuration is such that a sense amplifier activation signal is applied to the common connection part of the transistors and a complementary signal is applied to the gates of the first and fourth one conductivity type transistors and the gates of the first and fourth other conductivity type transistors. A characteristic semiconductor memory device.