JPH0534236Y2 - - Google Patents

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Publication number
JPH0534236Y2
JPH0534236Y2 JP1982006988U JP698882U JPH0534236Y2 JP H0534236 Y2 JPH0534236 Y2 JP H0534236Y2 JP 1982006988 U JP1982006988 U JP 1982006988U JP 698882 U JP698882 U JP 698882U JP H0534236 Y2 JPH0534236 Y2 JP H0534236Y2
Authority
JP
Japan
Prior art keywords
capacitor
circuit
semiconductor element
resistor
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1982006988U
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Japanese (ja)
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JPS58112087U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP698882U priority Critical patent/JPS58112087U/en
Publication of JPS58112087U publication Critical patent/JPS58112087U/en
Application granted granted Critical
Publication of JPH0534236Y2 publication Critical patent/JPH0534236Y2/ja
Granted legal-status Critical Current

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  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)
  • Power Conversion In General (AREA)

Description

【考案の詳細な説明】 本考案は主にスイツチングレギユレータに用い
られるダイオードやトランジスタのサージ電流吸
収回路に関する。
[Detailed Description of the Invention] The present invention relates to a surge current absorption circuit for diodes and transistors mainly used in switching regulators.

一般にダイオードに順方向電流を流している場
合にはPN接合面にキヤリアが蓄積されており、
逆方向電圧が加わるとこの蓄積効果により逆方向
電流が過渡的に流れる。この大きな逆方向電流、
すなわちサージ電流は例えばダイオードがスイツ
チングレギユレータの整流用ダイオードとして用
いてある場合にはノイズの発生の原因となる。
Generally, when forward current is flowing through a diode, carriers are accumulated on the PN junction surface.
When a reverse voltage is applied, a reverse current flows transiently due to this accumulation effect. This large reverse current,
That is, the surge current causes noise when the diode is used as a rectifying diode in a switching regulator, for example.

第1図はインバータ式のスイツチングレギユレ
ータのコンバータトランスを挟んで2次側の回路
図が示してあるが、従来は整流用グイオードD
1,D2と並列に抵抗の両端にコンデンサを接続
した直列回路を接続し、この直列回路でサージ電
流を吸収することによりノイズの発生を少くして
いた。なお抵抗の両端に接続してあるコンデンサ
は抵抗の一端が信頼性試験や使用時に接地された
場合に焼損することを防止する。しかしながらサ
ージ電流はこのような電圧源となる2次巻線に接
続する整流ダイオードだけでなく、トランジスタ
においても発生しスイツチングレギユレータの設
計仕様によつては必要に応じて整流ダイオード以
外の他の半導体素子にもサージ電流吸収回路を接
続せねばならない。従つて夫々のダイオードやト
ランジスタごとに同じ直列回路を接続することは
回路素子の節減という見地からは無駄である。本
考案は、電圧源の出力端に入力端を接続した第1
の半導体素子と、同じ電圧源の他の出力端に入力
端を接続した第2の半導体素子を有し、夫々の半
導体素子の電流出力端を共通接続した半導体回路
に設けられるサージ電流吸収回路である。このサ
ージ電流吸収回路は、第1の半導体素子の電流入
力端に第1のコンデンサと第1の抵抗からなる第
1直列回路のコンデンサ側の端を、また、第2の
半導体素子の電流入力端に第2のコンデンサと第
2の抵抗からなる第2直列回路のコンデンサ側の
端を接続し、夫々の直列回路の抵抗側の端を共通
接続し、この直列回路の共通接続端と前記半導体
素子の共通接続点間に第3のコンデンサを接続す
ることにより構成される。
Figure 1 shows a circuit diagram of the secondary side of an inverter-type switching regulator with a converter transformer in between.
A series circuit in which a capacitor is connected to both ends of a resistor is connected in parallel with 1 and D2, and this series circuit absorbs surge current to reduce noise generation. The capacitor connected to both ends of the resistor prevents it from burning out if one end of the resistor is grounded during reliability testing or use. However, surge currents occur not only in the rectifier diodes connected to the secondary windings that serve as voltage sources, but also in transistors, and depending on the design specifications of the switching regulator, it may be necessary to A surge current absorption circuit must also be connected to the semiconductor device. Therefore, connecting the same series circuit to each diode or transistor is wasteful from the standpoint of saving circuit elements. The present invention provides a first voltage source whose input end is connected to the output end of the voltage source.
A surge current absorption circuit provided in a semiconductor circuit having a second semiconductor element whose input terminal is connected to the other output terminal of the same voltage source, and whose current output terminals of the respective semiconductor elements are commonly connected. be. This surge current absorption circuit connects the capacitor side end of a first series circuit consisting of a first capacitor and a first resistor to the current input terminal of the first semiconductor element, and connects the capacitor side end to the current input terminal of the second semiconductor element. The capacitor side end of a second series circuit consisting of a second capacitor and a second resistor is connected to the capacitor side, and the resistor side ends of each series circuit are connected in common, and the common connection end of this series circuit and the semiconductor element are connected to each other. A third capacitor is connected between the common connection points of the two.

以下本考案の実施例を示す第2図を参照しなが
ら説明する。第2図はインバータ式のスイツチン
グレギユレータのコンバータトランスを挟んで2
次側の回路図だけが示してあり、L1は電圧源と
なるコンバータトランスの2次巻線、L2はチヨ
ークコイル、D3,D4は整流ダイオード、C1
……C4はコンデンサ、R1,R2は抵抗であ
る。2次巻線L1の両端にカソードの共通接続さ
れた整流ダイオードD3,D4のアノードが接続
され、共通接続されたカソードはチヨークコイル
L2の一端に接続される。チヨークコイルL2の
他端と2次巻線L1の中間タツプ間にはコンデン
サC4が接続されており、これらの回路がスイツ
チングレギユレータの整流平滑回路を構成するこ
とは説明を要しないであろう。
An embodiment of the present invention will be described below with reference to FIG. 2. Figure 2 shows the converter transformer of an inverter-type switching regulator.
Only the circuit diagram on the next side is shown, where L1 is the secondary winding of the converter transformer that serves as the voltage source, L2 is the chiyoke coil, D3 and D4 are the rectifier diodes, and C1
...C4 is a capacitor, and R1 and R2 are resistors. The anodes of rectifier diodes D3 and D4 whose cathodes are commonly connected are connected to both ends of the secondary winding L1, and the commonly connected cathodes are connected to one end of a chiyoke coil L2. A capacitor C4 is connected between the other end of the choke coil L2 and the intermediate tap of the secondary winding L1, and it is unnecessary to explain that these circuits constitute a rectifying and smoothing circuit of the switching regulator. .

そして抵抗R1と抵抗R2の接続点を中心にし
て、コンデンサC1と抵抗R1の直列回路、コン
デンサC3と抵抗R2の直列回路、コンデンサC
2とが夫々Y型に接続された回路の一面を形成す
る。コンデンサC1、コンデンサC3は夫々整流
ダイオードD3,D4のアノードに接続され、コ
ンデンサC2は共通接続された整流ダイオードD
3,D4のカソードに接続されている。そして整
流ダイオードD3の電流の入力端であるアノード
と出力端であるカソード間には抵抗R1の両端に
夫々コンデンサC1,C2を接続した直列回路に
よる第1の閉回路が形成され、又整流ダイオード
D4のアノードとカソード間には抵抗R2の両端
に夫々コンデンサC3,C2を接続した直列回路
による第2の閉回路が形成される。さらに又2次
巻線L1の両端にもコンデンサC1,抵抗R1、
R2、コンデンサC3の直列回路による第3の閉
回路が形成される。
Then, centering on the connection point between resistor R1 and resistor R2, a series circuit of capacitor C1 and resistor R1, a series circuit of capacitor C3 and resistor R2, and a series circuit of capacitor C
2 form one side of a circuit connected in a Y-shape. Capacitor C1 and capacitor C3 are connected to the anodes of rectifier diodes D3 and D4, respectively, and capacitor C2 is connected to rectifier diode D which is commonly connected.
3, connected to the cathode of D4. A first closed circuit is formed between the anode, which is the current input end, and the cathode, which is the output end, of the rectifier diode D3, which is a series circuit in which capacitors C1 and C2 are respectively connected to both ends of the resistor R1. A second closed circuit is formed between the anode and cathode of the resistor R2 by a series circuit having capacitors C3 and C2 connected to both ends of the resistor R2. Furthermore, a capacitor C1, a resistor R1,
A third closed circuit is formed by a series circuit of R2 and capacitor C3.

このようにY型に接続された回路は、第1の閉
回路と第2の閉回路が夫々整流ダイオードD3、
整流ダイオードD4のサージ電流を吸収し両方の
整流ダイオードのサージ電流吸収回路を構成す
る。このサージ電流吸収回路は第1図に比較して
コンデンサを1個節減できるが、さらに第3の閉
回路が形成されているので2次巻線L1に生ずる
スパイク電流を吸収することもできこのための特
別な回路を必要とする場合でも第3の閉回路で兼
用させ得る利点がある。
In the circuit connected in a Y-shape in this way, the first closed circuit and the second closed circuit are each connected to a rectifier diode D3,
It absorbs the surge current of the rectifier diode D4 and forms a surge current absorption circuit for both rectifier diodes. This surge current absorption circuit can save one capacitor compared to the one in Figure 1, but since a third closed circuit is formed, it can also absorb the spike current that occurs in the secondary winding L1. Even when a special circuit is required, there is an advantage that the third closed circuit can be used for the same purpose.

第3図は1石式のスイツチングレギユレータの
コンバータトランスを挟んだ2次側だけの回路図
であり、本考案の他の実施例が示されている。第
2図と同一部分は同じ付号を付与してある。整流
ダイオードD5とフライホイールダイオードD6
のカソードが共通接続され、夫々のアノードが2
次巻線L1の両端に接続されている。Y型に接続
されたサージ電流吸収回路の回路構成は第2図と
同じであるが、コンデンサC1、コンデンサC3
が夫々整流ダイオードD5、フライホイールダイ
オードD6のアノードに接続され、コンデンサC
2は共通接続されたカソードに接続される。そし
て整流ダイオードD5のアノードとカソード間に
は抵抗R1の両端に夫々コンデンサC1、コンデ
ンサC2を接続した直列回路による第1の閉回路
が形成され、フライホイールダイオードD6のア
ノードとカソード間には抵抗R2の両端に夫々コ
ンデンサC2,C3を接続した直列回路による第
2の閉回路が形成され、電圧源となる2次巻線L
1の両端には第3の閉回路が第2図と同様に形成
される。Y型に接続されたこのようなサージ電流
吸収回路により、整流ダイオードD5、フライホ
イールダイオードD6のサージ電流を吸収するこ
とができる。第4図はチヨツパ式のスイツチング
レギユレータの回路図であり、本考案のさらに別
の実施例が第2図、第3図と同一部分に同じ符号
を付与して示してある。電圧源となる直流源Sに
制御トランジスタTのコレクタが接続され、その
エミツタはフライホイールダイオードD6のカソ
ードと共通接続されている。Y型に接続されたサ
ージ電流吸収回路のコンデンサ1C1が制御トラ
ンジスタTのコレクタ、コンデンサC3がフライ
ホイールダイオードD6のアノード、コンデンサ
C2が共通接続された部分に夫々接続されてい
る。制御トランジスタTはベースに加わる信号に
よりチヨツパされ、この時コレクタとエミツタ間
にはサージ電流が流れようとするがコンデンサC
1、抵抗R1、コンデンサC2の直列回路による
第1の閉回路によりサージ電流は吸収される。フ
ライホイールダイオードD6のサージ電流はすで
に述べたように第2の閉回路により吸収される。
FIG. 3 is a circuit diagram of only the secondary side of a single-stone switching regulator sandwiching a converter transformer, and shows another embodiment of the present invention. The same parts as in FIG. 2 are given the same numbers. Rectifier diode D5 and flywheel diode D6
The cathodes of the two are connected in common, and the anodes of each
It is connected to both ends of the next winding L1. The circuit configuration of the surge current absorption circuit connected in a Y-shape is the same as shown in Figure 2, except that capacitor C1 and capacitor C3 are
are connected to the anodes of rectifier diode D5 and flywheel diode D6, respectively, and capacitor C
2 are connected to a commonly connected cathode. A first closed circuit is formed between the anode and cathode of the rectifier diode D5 by a series circuit in which a capacitor C1 and a capacitor C2 are respectively connected to both ends of a resistor R1, and a resistor R2 is connected between the anode and cathode of the flywheel diode D6. A second closed circuit is formed by a series circuit in which capacitors C2 and C3 are connected to both ends of the secondary winding L, which serves as a voltage source.
A third closed circuit is formed at both ends of 1 in the same manner as in FIG. Such a surge current absorption circuit connected in a Y-shape can absorb the surge current of the rectifier diode D5 and the flywheel diode D6. FIG. 4 is a circuit diagram of a chopper-type switching regulator, and shows yet another embodiment of the present invention, in which the same parts as in FIGS. 2 and 3 are given the same reference numerals. The collector of the control transistor T is connected to a DC source S serving as a voltage source, and its emitter is commonly connected to the cathode of a flywheel diode D6. A capacitor 1C1 of the surge current absorbing circuit connected in a Y-shape is connected to the collector of the control transistor T, a capacitor C3 to the anode of the flywheel diode D6, and a common connection to the capacitor C2. The control transistor T is chopped by the signal applied to the base, and at this time a surge current tries to flow between the collector and emitter, but the capacitor C
1, the surge current is absorbed by the first closed circuit formed by the series circuit of resistor R1 and capacitor C2. The surge current of the flywheel diode D6 is absorbed by the second closed circuit as described above.

かくして本考案のサージ電流吸収回路は、Y型
の回路接続により2個の半導体素子の入力端と出
力端間に抵抗の両端にコンデンサを接続した直列
回路の閉回路を形成したものであるから、従来に
比較してコンデンサを節減したにもかかわらず該
半導体素子のサージ電流を吸収できる。
Thus, the surge current absorbing circuit of the present invention forms a closed series circuit in which a capacitor is connected to both ends of a resistor between the input terminal and output terminal of two semiconductor elements by Y-shaped circuit connection. Even though the number of capacitors is reduced compared to the conventional method, the surge current of the semiconductor element can be absorbed.

さらに別の閉回路が形成されるので、例えば半
導体素子がスイツチングレギユレータの2個の整
流ダイオードであればその整流ダイオードのサー
ジ電流は無論のこと、コンバータトランスの2次
巻線のスパイク電流を吸収できる。
Furthermore, another closed circuit is formed, so for example, if the semiconductor elements are two rectifier diodes of a switching regulator, not only the surge current of the rectifier diodes but also the spike current of the secondary winding of the converter transformer will be generated. can be absorbed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のサージ電流吸収回路を示すスイ
ツチングレギユレータの回路図であり、第2図、
第3図、第4図は本考案のサージ電流吸収回路の
実施例を示すスイツチングレギユレータの回路図
である。 L1……2次巻線、D1……D5……整流ダイ
オード、D6……フライホイールダイオード、C
1……C4……コンデンサ、R1,R2……抵
抗、L2……チヨークコイル、T……制御トラン
ジスタ。
FIG. 1 is a circuit diagram of a switching regulator showing a conventional surge current absorption circuit, and FIG.
3 and 4 are circuit diagrams of a switching regulator showing an embodiment of the surge current absorbing circuit of the present invention. L1... Secondary winding, D1... D5... Rectifier diode, D6... Flywheel diode, C
1...C4...Capacitor, R1, R2...Resistor, L2...Chiyoke coil, T...Control transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧源の出力端に電流入力端を接続した第1の
半導体素子と、該電圧源の他の出力端に電流入力
端を接続した第2の半導体素子を有し、夫々の半
導体素子の電流出力端を共通接続した半導体回路
に設けられるサージ電流吸収回路において、第1
のコンデンサと第1の抵抗からなる第1直列回路
のコンデンサ側の端を第1の半導体素子の電流入
力端と接続し、第2のコンデンサと第2の抵抗か
らなる第2直列回路のコンデンサ側の端を第2の
半導体素子の電流入力端と接続し、該夫々の直列
回路の抵抗側の端を共通接続し、該直列回路の共
通接続点と前記半導体素子の共通接続点の間に第
3のコンデンサを接続したことを特徴とするサー
ジ電流吸収回路。
A first semiconductor element having a current input terminal connected to the output terminal of the voltage source, and a second semiconductor element having a current input terminal connected to the other output terminal of the voltage source, and the current output of each semiconductor element In a surge current absorption circuit provided in a semiconductor circuit whose ends are commonly connected, the first
The capacitor side end of a first series circuit consisting of a capacitor and a first resistor is connected to the current input terminal of the first semiconductor element, and the capacitor side of a second series circuit consisting of a second capacitor and a second resistor is connected to the current input terminal of the first semiconductor element. is connected to the current input terminal of the second semiconductor element, the resistor side ends of the respective series circuits are commonly connected, and a second semiconductor element is connected between the common connection point of the series circuit and the common connection point of the semiconductor element. A surge current absorption circuit characterized by connecting a capacitor No. 3.
JP698882U 1982-01-21 1982-01-21 Surge current absorption circuit Granted JPS58112087U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP698882U JPS58112087U (en) 1982-01-21 1982-01-21 Surge current absorption circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP698882U JPS58112087U (en) 1982-01-21 1982-01-21 Surge current absorption circuit

Publications (2)

Publication Number Publication Date
JPS58112087U JPS58112087U (en) 1983-07-30
JPH0534236Y2 true JPH0534236Y2 (en) 1993-08-30

Family

ID=30019764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP698882U Granted JPS58112087U (en) 1982-01-21 1982-01-21 Surge current absorption circuit

Country Status (1)

Country Link
JP (1) JPS58112087U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5709664B2 (en) * 2011-06-20 2015-04-30 新電元工業株式会社 Isolated switching power supply

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225221A (en) * 1975-08-21 1977-02-25 Meidensha Electric Mfg Co Ltd Detecting system of surge absorption ground fault for stationary high frequency inverter device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55147760U (en) * 1979-04-11 1980-10-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225221A (en) * 1975-08-21 1977-02-25 Meidensha Electric Mfg Co Ltd Detecting system of surge absorption ground fault for stationary high frequency inverter device

Also Published As

Publication number Publication date
JPS58112087U (en) 1983-07-30

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