JPH05342182A - Distributed processing system - Google Patents

Abstract

PURPOSE:To provide the distributed processing system which prevents the output of the own system from being affected by the other system. CONSTITUTION:This system is equipped with plural computers 11-1N, buffer memories BUF 41-4N provided between the computers 11-1N and a bus 2, and transmission source managing table provided at a bus controller 5. The BUF 41-4N separate the data areas of the own systems and the data areas of the respective other systems corresponding to an address common for the respective systems. The computers 11-1N just write output data in the data areas of the own systems, and the BUF 41-4N periodically output the data of the own systems according to the transmission source managing table under the control of the bus controller 5. For example, the transmission source of data areas (e) in the respective BUF 41-4N is allocated to a CPU 11 in advance. Even when a CPU 2 erroneously writes data in the data area (e) of the BUF 42, those data are not outputted to the bus but correctly rewritten at the time of outputting from the BUF 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed processing system for transmitting data between a plurality of computers via a transmission line,
The present invention relates to a data transmission system that prevents an influence on other systems due to a malfunction of a computer.

[0002]

2. Description of the Related Art In a data processing system of this type, a plurality of computers often share one input / output device. Further, such a system is often used to control a plant by outputting a control signal calculated by a computer to the plant via an input / output device.

However, it is easily conceivable to output data to an address other than an address to be accessed by a plurality of computers with respect to the input / output device. Such a situation must be absolutely avoided in order to safely control the plant.

A typical data processing system is shown in FIG. In this figure, N computers 11 to 1N exchange data with the input / output device 3 (31 to 3N) via the bus 2. For example, the output data of the computer 11 is output to the output device at the address designated by its own program. At this time, the output data is broadcast to other computers.

Data is exchanged between the computers via the bus 2. The source computer broadcasts the data to other computers, and at that time, the address common to each computer is designated and written in the memory area of each computer.

[0006]

In the example of FIG. 1, when data is transmitted from a computer of its own system to a computer of another system, if the computer 12 erroneously writes in an area written by the computer 11, the computer 11 Correct data will be lost, and the malfunction will spread to the data system and output device handled by each computer. This often happens when a program is mistaken or when the system is modified.

An object of the present invention is to provide a distributed processing system in which the output of its own system is not affected by other systems.

[0008]

According to the present invention, instead of directly transmitting data between computers, a buffer device is provided on each computer side, and this buffer device transmits data under the control of a bus controller. That is, the feature is that the data transmission system is independent of the computer, and is configured as follows.

According to the configuration of the present invention, in a distributed processing system in which a plurality of computers that autonomously process data and an output of a computer of its own system are data-transmitted to a computer of another system via a transmission path, each of the plurality of computers is Between the transmission line and the transmission line, there is a data area of its own computer (hereinafter, own system data area) divided by a common address, and a data area of each of the other computers (hereinafter, other system data area) A distributed shared memory (hereinafter referred to as a buffer memory) for storing, an input / output gate for controlling data transfer between the buffer memory and the bus in response to a data transmission command, and opening / closing of the input / output gate, etc. For one of the other system data areas of the buffer memory, the only buffer memory having the own system data area of the same address as the one area is assigned to the source, and Data in the data area is provided a channel controller that outputs the transmission command for controlling so sent.

[0010]

Since the present invention is constructed as described above, the output processing of the computer is limited to each buffer memory. Data transmission from the buffer memory to the buffer memory of the computer of another system is managed by the transmission path controller.
The transmission path controller uses one address for each area and source that is common to each buffer memory and unique to each computer.
Since the data is managed on a one-to-one basis, this data will not be output to the outside even if the computer mistakenly writes it to the area of the other system of its own buffer memory.

According to the present invention, it is possible to prevent the spread of malfunction of the computer. In addition, there is no need to be aware of other system troubles when designing the system.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the present invention. Each computer 11-1
Buffer devices 41, 42, ... 4 provided between N and the bus
N is connected to the input / output device group 3 and the bus controller 5 via the bus 2. Each of the buffer devices 41 to 4N has a built-in memory having a storage device sufficient to store the data amount required by the input / output device group 3 and the data amount required for data transmission between the computers. The sender of these data is registered in the sender management table 6 in the bus controller 5. An example of the structure of the sender management table 6 is shown in FIGS. 3 and 4.
The input device 310 is shared by each computer, but the output device 311
.About.31N are assigned so as to correspond to each computer. In addition, a computer that outputs data that is exchanged between computers is registered as a sender. The source management table 6 is provided with addresses a, b, to g corresponding to the addresses when the data is periodically transferred between the input / output device group 3 and the buffer devices 41 to 4N via the bus 2. When the transfer address is a, the data is transferred from the input device 310 to the buffer devices 41 to 4N. Buffer device 4 when the transfer address is b
1 to the output device 311. At this time, it is simultaneously broadcast to the buffer devices 42 to 4N. When the transfer address is e, it is transferred from the buffer device 41 to the buffer devices 42 to 4N. Thus, data transmission is performed between the input / output device and the buffer device and between the buffer devices.

FIG. 5 shows a concrete example of the bus controller and the input / output gate. The bus controller 5 comprises an address counter 51 for generating the transfer address signal 7, a memory 52 for accommodating a transmission source management table, and a decoder 53 for decoding the transmission source information 10 output from the memory 52. The decoder 11 is a gate (3100, 431-43) for putting the data of the input device 310 and the buffer devices 411-41N, which may be sources, on the data bus 12.
N) and the data on the data bus 12 to the output device 31
1 to 31N, and gates (3110 to 31N) taken into the buffer memories 411 to 41N in the buffer devices 41 to 4N.
N, 421 to 42N) is output.

In this embodiment, it operates as follows.

(1) When data is transmitted from the input device 310 to each computer side, the value of the address counter 51 is a
Next, the memory 52 outputs data indicating that the transmission source is the input device 310. This data is decoded by the decoder 53 and a signal 130 is issued which opens the gate 3100. The signals 131 to 13N for opening the output gates 431 to 43N in the buffer devices 41 to 4N are not output. Therefore, 13
Input gates 421 to 413 that perform the reverse operation of signals 1 to 13N
42N is opened and the data is written to the pre-specified address of the buffer memories 411 to 41N.

(2) In the case of data transmission from the computer side to the output device, for example, when outputting data from 41 to the output device 311, the address counter 51 becomes b, and the memory 52 is the computer 11 as the source. Data indicating that there is is output. This data is decoded by the decoder 53, and a signal for opening the gates 431 and 3110 is issued. Since other gate control signals are not output, the gates in the input / output device 3 other than 3110 and the gates 432 to 43N other than the buffer device 41 are closed. At this time, the input gate of the buffer device 41 is closed and the input gates 422 to 42N of the other buffer devices are opened. Therefore, the data in the buffer device 41 is transferred to the output device 311 and the buffer device 4.
2 to 4N.

FIG. 6 is a diagram for explaining that in the system according to the present invention, erroneous data does not spread to a data system handled by another computer due to an abnormality (hardware malfunction or program mistake) of an arbitrary computer. is there. Now, assume that the computer 12 malfunctions and tries to write data to the area (address b) to be output by the computer 11. At this time, the target to be written by the computer 12 is to designate the area b of the memory in the buffer device 42. However, since the bus controller 5 manages the data transmission source in the area of b as the computer 11, when transferring to the output device 3110, the buffer device 4 connected to the computer 11 is used.
The data in the area b of the memory in 1 is transferred to the output device 311. Then, the area b of the memory in the buffer device 42 connected to the computer 12 is also rewritten with the data of the computer 11. Therefore, the malfunction of the computer 12 does not affect the output device 311 and the malfunction does not spread to the data system handled by another computer. Utilizing this advantage, debugging in each processor unit and division adjustment for each subsystem are possible.

In the above example, data is transmitted from the computer 11 to the output device 311 via the area b of the buffer device 41, but the same applies to transmission between computers. Figure 3
As shown in FIG. 4 or the sender management table 6 in FIG. 4, the area e of each buffer memory is the buffer memory 4 of the computer 11.
1 is assigned to the sender. That is, the data written from the computer 11 to the area e of the buffer 41 is transmitted to the buffer memories 42 to 4N of the other system according to the transmission command of the bus controller 5 and written to the area e.
In this area e, the buffer memory 41 is managed by only one source, so that even if the computers 12 to 1N mistakenly write miss data in the area e of its own system, it is not output. Then, at the timing when the buffer 41 becomes the source of the area e again, the miss data is rewritten correctly.

As described above, the present invention does not directly transmit data between computers, but provides a buffer device on each computer side, and this buffer device transmits data under the control of the bus controller. Therefore, according to the present invention, it is possible to prevent a plurality of computers from accessing the same output device. It is also possible to prevent the malfunction of any processor from adversely affecting the output devices of other processors. By utilizing this, it is possible to make division adjustments in a distributed system, shorten the on-site adjustment period of the system, and adjust subsystems under the main system online. Further, since the input / output device is connected to the bus, it is possible to deal with the addition by adding the system function only by adding the computer and the buffer device and changing the source management table.

[0020]

According to the present invention, since the data transmission system can be independent of the computer, it is possible to prevent the malfunction of the computer which is performing distributed processing from spreading to other systems, and to provide a highly reliable distributed processing system. Can be provided. Further, even if the design or test is performed for each computer, it is not necessary to be aware of the influence on other systems, so that it is possible to design and test the distributed processing unit, and it becomes easy to construct or modify the system.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional system configuration.

FIG. 2 is a configuration diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of allocation of a transmission source management table.

FIG. 4 is an explanatory diagram showing an example of detailed allocation of a transmission source management table.

5 is a configuration diagram showing a more detailed example of FIG.

FIG. 6 is an explanatory diagram for explaining the operation of the present invention.

[Explanation of symbols]

11-1N ... Computer, 2 ... Bus, 3 ... Input / output device, 31
0 ... Input device, 311 to 31N ... Output device, 5 ... Bus controller, 51 ... Address counter, 52 ... Memory,
53 ... Decoder, 6 ... Source management table, 41-4N
... buffer device, 411 to 41N ... buffer memory, 4
31-43N, 3100 ... Output gates, 421-42
N, 3110 to 31NN ... Input gate.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Azusa 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Omika factory (72) Inventor Nagao Yoshida 5-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1 Incorporated company Hitachi Ltd. Omika factory (72) Inventor Hiroshi Saito 52-1 Omika-cho, Hitachi City, Ibaraki prefecture Incorporated company Hitachi Ltd. Omika factory (72) Inventor Takashi Sakurai Hitachi city, Ibaraki prefecture 5-2-1, Omika-cho, Hitachi Ltd. Omika Factory (72) Inventor Susumu Kitani 5-2-1, Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Omika Factory (72) Inventor Yuji Kikuchi 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Co., Ltd. Hitachi Ltd. Omika factory (72) Inventor Yoshihiro Kamegane Omika-shi, Hitachi-shi, Ibaraki 5-2-1, Machi Incorporated company Hitachi, Ltd. Omika factory

Claims (5)

[Claims] 1. A distributed processing system in which a plurality of computers that autonomously process data and an output of the computer are transmitted to another computer via a transmission path, and between the plurality of computers and the transmission path. , The data area of its own computer divided by a common address (hereinafter referred to as its own data area)
And a distributed shared memory (hereinafter, referred to as "other system data area") that stores data
Buffer memory), an input / output gate for controlling data transfer between the buffer memory and the bus in response to a data transmission command, and opening / closing of the input / output gate for the other system data area of another buffer memory. For one, the only buffer memory having the own data area of the same address as the one area is assigned to the sender, and the data in the own data area of the sender is controlled to be transmitted. A distributed processing system comprising a transmission path controller that outputs a transmission command, and performing data transmission between computers according to the transmission command of the transmission path controller. 2. The transmission path controller, when controlling one of the input / output gates to output data,
2. The distributed processing system according to claim 1, wherein the other input / output gates are controlled so that all data is input. 3. The distributed processing system according to claim 1, wherein the allocation of the transmission source is registered in advance in the transmission source management means of the transmission path controller from the computer. 4. The distributed processing system according to claim 1, wherein the transmission path controller periodically outputs the transmission command. 5. The distributed processing system according to claim 1, wherein the transmission line is composed of a bus.