JPH05342148A - Bus arbitration system - Google Patents

Abstract

PURPOSE:To provide the bus arbitration system in which the access right corresponding to priority can be allocated without being influenced by attachment and detachment of a slave device, and also, the signal lines are constituted of only two pieces of signal lines of a transmitting bus and a receiving bus, and a special bus arbitration control signal line is not required, with regard to the bus arbitration system in a device for executing a communication in the inside through the bus. CONSTITUTION:The system is provided with a transmitting bus B1 for transmitting a transmitting frame to a master device M from each slave device S0-Sn, and receiving buses B2, B3 for receiving a receiving frame from the master device M by each slave device S0-Sn. The slave device having a transmitting request detects a priority bit of the transmitting frame on the transmitting bus B1, and rewrites the priority bit and a discrimination bit of the transmitting frame by the own priority and discriminating information, when the priority of the own request is higher than its priority. The master device M gives a transmitting permission by a designated bit to the slave device corresponding to the discrimination bit contained in the received transmitting frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration system in a device adapted for internal communication via a bus.

[0002]

2. Description of the Related Art Conventionally, in a device having a master device and a slave device therein and communicating with each other via a bus,
A data bus, an address bus, and a bus arbitration control signal line are respectively connected from the master device to the slave device.

[0003]

However, in such a conventional device, when the parallel type bus arbitration as shown in FIG. 6 is adopted, the bus arbitration control signal line of the bus arbiter (arbitration device). Is required for the number of slave devices, and when serial bus arbitration is adopted,
There is a problem that the entire device does not function when the relay slave device is separated.

The present invention has been made in consideration of such circumstances, and by passively branching / inserting information on the transmission / reception bus, it is not affected by the attachment / detachment of the slave device and the priority is changed according to the priority. Further, the present invention provides a bus arbitration system in which the access right can be assigned, and the signal line is composed of only two signal lines, that is, the transmission bus and the reception bus, and no special bus arbitration control signal line is required.

[0005]

According to the present invention, in a bus arbitration system for a device including a master device M and a plurality of slave devices S0 to Sn, a transmission frame is transmitted from each slave device S0 to Sn to the master device M. Transmission bus B1
And each of the slave devices S0 to Sn includes receive buses B2 and B3 for receiving the received frames from the master device M in the order described above. , The received frame has a nominating bit for nominating a specific slave device, and the slave device requesting transmission has the priority bit of the transmission frame on the transmission bus B1. When the detected priority level is higher than the priority level requested by itself, the priority bit and the identification bit of the transmission frame are rewritten with the priority level and the identification information, and the master device M is included in the received transmission frame. The present invention provides a bus arbitration system characterized in that a slave device corresponding to an identification bit is given a transmission permission by a designated bit.

Further, the reception buses B2 and B3 are connected to each slave device S0 to Sn starting from the master device M, connected to the final slave device Sn, and then looped back to end the master device M. , Transmission bus B1
Are connected in parallel to the reception buses B2 and B3 and are connected to the slave devices S0 to Sn, and the reception buses B2 and B3
It is preferable that the signal transmission delay time between each slave device and the master device is set to be equal to the signal transmission delay time between each slave device and the master device on the transmission bus B1.

[0007]

The slave device having the transmission request is the transmission bus B1.
The priority bit of the upper transmission frame is detected, and when the priority requested by itself is higher than the priority, the priority bit and the identification bit of the transmission frame are rewritten with the own priority and the identification information.

The master device determines the slave device having the highest priority from the identification bits included in the received transmission frame, and designates the determined slave device by the nomination bit included in the reception frame to give transmission permission. Then, the slave device that has received the transmission permission transmits to the master device.

By thus inserting the bus arbitration signal into the transmission frame and the reception frame transmitted by the bus, a bus system capable of bus arbitration is provided without providing a bus arbitration control signal line. ..

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. This does not limit the invention.

FIG. 1 is a system configuration diagram of an embodiment, M
Is a master device, and S0 to Sn are slave devices.

The master device M and the slave devices S0 to Sn are passively connected by a transmission bus B1 and reception buses B2 and B3, and the master device M and each slave device perform 1: N communication. Further, the signal flow of the transmission bus B1 and the signal flow of the reception buses B2 and B3 are in the same direction, and the signal propagation delay amount is the same in each of the slave devices S0 to Sn.

The transmission bus B1 is the reception buses B2 and B3.
Similarly, after the final slave device Sn is connected, the master device M receives the reception timing from the reception bus B3 by returning to the master device M, and each of the slave devices S0 to Sn is transmitted to the transmission bus B1. The inserted transmission data is returned to the master device M in a constant phase regardless of the bus length.

FIG. 4 shows the received frame of this embodiment as shown in FIG.
Indicates the respective transmission frames. The received frame has a designated bit (VALID PHYSICAL ADDRESS) X for designating a slave device that is permitted to transmit, and the transmitted frame has a priority bit (PRIORITY MARK BIT) Y and an identification bit (PHYSICAL ADDRESS MARK BIT) Z for identifying the slave device. Prepare The transmission frame is provided with a guard time T in order to protect the propagation time of the priority bit Y and the identification bit Z in the opposite direction.

All other frames are the same as a normal packet frame except for the destination address DA, source address SA, transmission data INFO, and cyclic redundancy check bit C.
The RC and the frame synchronization bit F are provided.

FIG. 2 is a block diagram showing a master device M of the embodiment, 11 is an MPU and 12 is a slave device S0 to S0.
Dual port RA for storing data received from Sn
M and 13 are dual port RAMs for storing data to be transmitted to the slave devices S0 to Sn, 14 is a frame assembling unit for assembling frames of data to be transmitted to the slave devices S0 to Sn, and 16 is a slave via the transmission bus B1. A frame analysis unit for analyzing a frame of data received from the devices S0 to Sn, 15 a timing signal generation unit for generating timing signals to be output to the frame assembly unit 14 and the frame analysis unit 16, and 17 a slave device S0.
Is a generation unit that generates a transmission permission address (VALID PHYSICAL ADDRESS), that is, a designated bit X, based on transmission data from Sn.

FIG. 3 is a block diagram showing any one of the slave devices S0 to Sn of the embodiment, 31 is an MPU,
32 is a dual port RAM for storing the data received from the master device M, 33 is a dual port RAM for storing the data to be transmitted to the master device M, and 34 is a frame received from the master device M via the reception bus B3. A frame analysis unit for analyzing, a destination address determination unit for determining a destination address DA included in the received frame,
36 is a transmission permission address (VALI) included in the received frame.
D PHYSICAL ADDRESS) That is, the detection unit detects the designated bit X.

Reference numeral 38 is a timing signal generation unit for generating a timing signal, 43 is an arbitration unit, 40 is a priority determination unit for determining priority, and 41 is its own address (PHYSICAL ADDRE).
Address setting section for setting SS), 39 is a priority determination section 4
0 and the mark sending unit that receives the output of the address setting unit 41 and sends the mark that specifies the priority bit Y and the identification bit Z, 42 is the mark detecting unit that detects the mark included in the nomination bit X of the received frame, 37 Is a selector for selecting and inserting the data of the dual port RAM 33 or the output of the mark sending unit 39 into the transmission frame.

In FIG. 2, in the master device M, the MPU
When there is a transmission request from 11, the transmission packet is sent to the dual port RAM 13, and then the frame assembly unit 14 generates a frame pattern based on the timing signal from the timing signal generation unit 15 into a designated bit ( The transmission permission address) X is added and the data is transmitted to the reception bus B3.

When there is a received packet from the transmission bus B1, the timing signal generation unit 15 generates the timing signal of the transmission bus B1 based on the reception bus B2, and the frame analysis unit 16 detects the identification bit Z. To do. The transmission frame from the slave devices S0 to Sn is a dual port R
It is sent to the AM 12 and then received by the MPU 11.

Further, in FIG. 3, the received frame from the master device M is transmitted from the receiving bus B3 to the frame analysis unit 34.
Then, it is sent to the destination address determination unit 35, and if it matches with its own address, it is taken into the dual port RAM 32 and then received by the MPU 31.

When there is a transmission request from the MPU 31, it is sent to the dual port RAM 33 as packet data and notified to the arbitration unit 43. The arbitration unit 43 sends the priority to the priority determination unit 40. Based on the timing from the timing signal generator 38, the mark transmitter 39 generates a mark that specifies the priority bit Y and the identification bit Z.
When the mark detection unit 42 detects a priority higher than the self priority, the transmission of the identification bit Z specifying mark is stopped.

After that, the transmission permission from the master device M, that is, the designated bit X is detected by the detection unit 36. When the transmission permission is received, the selector 37 is switched to transfer the transmission packet information of the dual port RAM 33 to the transmission bus B1. To send to. Therefore, the system shown in FIG. 1 operates as follows as a whole.

First, from the master device M to the slave device S0
~ Sn is transmitted as a packet frame via the reception bus B3. In the slave devices S0 to Sn, if the own address and the destination address (DESTINATION ADDRESS) DA of the packet data are the same, the packet is transmitted. Capture the frame and ignore it if different.

From slave devices S0 to Sn to master device M
When the slave devices S0 to Sn have a transmission request, the priority bit (PRIO) of the frame on the transmission bus B1 is transmitted to the slave device S0 to Sn.
RITYMARK BIT) Mark the priority level on Y, and if there is no higher priority than yourself, then the identification bit (PHYSIC
AL ADDRESS MARK BIT) Mark your position on Z.

Then, the master device M takes in the data on the transmission bus B1 and analyzes the identification bit Z to identify the identification bit Z.
Permit the transmission request of the slave device having the largest value of. The designated bit X is for notifying transmission permission to a specific slave device, and only the slave device that matches the designated bit can transmit to the master transmission M.

When the transmission requests of the slave devices S0 to Sn compete with each other, the device having the higher priority is permitted to transmit. In the same case, the slave device having the larger identification bit Z is permitted to transmit. Further, the slave device, which has a low priority and cannot obtain the transmission permission, is given a priority of +1 when the next request is made, so that the transmission permission can be easily obtained.

FIG. 8 is an explanatory view for explaining the arbitration principle of the transmission right in more detail. The slave devices S0 to Sn are assigned physical addresses (PHYSICAL ADD) in the order closer to the master device M.
RESS) are set to 0, 1, 2, ... N respectively.

First, when the slave S0 issues a transmission request of priority 2, as shown in FIG. 8A, the priority bit Y
No. 2, and then the identification bit Z is marked with its own address 0.

Next, as shown in FIG. 8B, when there is no transmission request of the slave devices S1 and S2 and the slave device S3 issues a transmission request of priority 3, the priority bits already marked. The slave device 3 marks the priority 3 because it is higher than the priority 2 of Y, and subsequently marks the identification bit Z with 3 of its own address.

After that, when there is no transmission request up to the slave device n, the master device M accepts the transmission request of the slave 3 having the largest identification bit Z, and as shown in FIG. Mark 3 and give permission to send.

FIG. 7 is an explanatory diagram showing the phase relationship between the reception frame and the transmission frame. As shown in FIG. 1, the transmission bus B1 is used.
By laying in parallel with the receiving buses B2 and B3,
The master device M facilitates generation of reception timing. That is, θ in (a) of FIG. 7 is the phase difference between the reception frame and the transmission frame when passing through the slave device 1, and as shown in (b) of FIG. 7, even when passing through the slave device n. , The phase difference θ does not change. The same applies to the master device M. Note that FIG.
Represents the transmission line delay time between the slave devices S0 to Sn.

[0033]

According to the present invention, the master device and the plurality of slave devices can communicate with each other only by the transmission bus and the reception bus, which is effective in reducing wiring. Further, since the slave device and the transmission / reception bus are passively connected, the slave device is not affected by the disconnection of the slave device or the power-off, and is excellent in expandability.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an embodiment.

FIG. 2 is a block diagram illustrating a master device according to an embodiment.

FIG. 3 is a block diagram showing a slave device according to an embodiment.

FIG. 4 is an explanatory diagram showing a reception frame according to the embodiment.

FIG. 5 is an explanatory diagram showing a transmission frame according to the embodiment.

FIG. 6 is a connection explanatory view of a conventional example.

FIG. 7 is an explanatory diagram showing a phase relationship between a reception frame and a transmission frame according to the embodiment.

FIG. 8 is an explanatory diagram showing a transmission right arbitration principle of the embodiment.

[Explanation of symbols]

 M master device B1 transmission bus B2 reception bus B3 reception bus S0-Sn slave device 11 MPU 12 dual port RAM 13 dual port RAM 14 frame assembly part 15 timing signal generation part 16 frame analysis part 17 designated bit generation part 31 MPU 32 dual port RAM 33 Dual port RAM 34 Frame analysis unit 35 Destination address determination unit 36 Designation bit detection unit 37 Selector 38 Timing signal generation unit 39 Mark transmission unit 40 Priority determination unit 41 Address setting unit 42 Mark detection unit 43 Arbitration unit

Claims (2)

[Claims] 1. In a bus arbitration system of a device including a master device (M) and a plurality of slave devices (S0 to Sn), a transmission frame is transmitted from each slave device (S0 to Sn) to the master device (M). A transmission bus (B1) for
Receiving buses (B2, B) in which the slave devices (S0 to Sn) receive the received frames from the master device (M) in the above order.
3), the transmission frame has a priority bit (Y) indicating the priority and an identification bit (Z) indicating the identification information of the slave devices (S0 to Sn), and the reception frame indicates a specific slave device. A slave device that has a nomination bit for nomination and has a transmission request detects the priority bit of the transmission frame on the transmission bus (B1) and has a higher priority than the priority requested by itself. Sometimes, the priority bit and the identification bit of the transmission frame are rewritten with the priority and identification information of itself, and the master device (M) permits the slave device corresponding to the identification bit included in the received transmission frame to transmit by the nomination bit. A bus arbitration system characterized by giving. 2. The reception bus (B2, B3) is connected to each slave device (S0 to Sn) starting from the master device (M) and connected to the final slave device (Sn), and then loops back to the master device (Sn). M) is connected as an end point,
The transmission bus (B1) is wired in parallel with the reception bus (B2, B3) and connected to each slave device (S0 to Sn), and between the slave device and the master device on the reception bus (B2, B3). 2. The bus arbitration system according to claim 1, wherein the signal transmission delay time is equal to the signal transmission delay time between each slave device and the master device on the transmission bus (B1).