JPH05341745A - Display controller - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a display control circuit by limiting the number of gradation or the number of color of a display while executing the application software sufficient with a two-gradation display of a word processor, etc. CONSTITUTION:This controller is provided with plural displaying VRAM planes 10-13, and the display of plural gradations or plural colors is executed based on output signals from respective planes. The controller is provided with a display read inhibition means 9 inhibiting selectively the display read of respective planes, a first route having a means generating display data executing the display of plural gradations or plural colors based on the output signals from all planes, a second route having a means selecting the output of the plane where the display read is not prohibited according to the output of the display read prohibition means 9 and outputting it as the display data and a data nonpassing part stoping means stopping the operation of the first route when a route except the first route is selected by a data route selection means selecting the route where the display read data passes according to the output of the display read inhibition means 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for a display device capable of displaying a plurality of gradations and / or a plurality of colors, and more particularly to a display control device capable of reducing power consumption. ..

[0002]

2. Description of the Related Art In an information processing device such as a personal computer or a word processor, a VRAM (Vi
Deo Random Access Memory) has a plurality of planes, and some display a plurality of gradations or a plurality of colors on a display device. Display devices used in such information processing devices include flat panel display devices such as liquid crystal panels in addition to CRT displays. Portable computers such as laptop computers, laptop computers, and notebook word processors that have flat panel display devices as display devices are small, so they do not take up space, are easy to carry, and can be battery-powered. It surpasses the personal computer.

As a means for controlling the display operation of this type of display device, there is a conventional one as shown in FIG. 3, for example.

The display control device shown in FIG. 3 is a display control device for controlling the display of the liquid crystal panel 1 capable of displaying a plurality of gradations or a plurality of colors. This display control device stores (n + 1) from 0 to n for storing display data.
V with a number of VRAM planes 10, 11, 12, 13
RAM group 10a, VRAM control circuit 2 for controlling VRAMs 10, 11, 12, 13; parallel-serial conversion circuits 14, 15, 16, 17 for converting parallel display read data to serial data; and number of planes A palette 3 provided to display more colors than the number of display colors to be displayed, and a color conversion circuit 4 for converting the number of colors determined by the palette 3 into a limited number of gradations or colors of the liquid crystal panel 1. With.

Here, 30, 31, 32, and 33 are display read data lines from the VRAMs 10, 11, 12, and 13, and 34, 35, 36, and 37 are parallel-serial conversion circuits 14, 15, 16, and 17. Serial data line from
Reference numeral 18 is a display data line output from the color conversion circuit 4. Reference numeral 5 is a liquid crystal i / F circuit for matching the display data line 18 output from the color conversion circuit 4 and the i / F of the liquid crystal panel 1.

[0006]

In the above conventional display control device, the palette 3 and the color conversion circuit 4 give various degrees of freedom to the display on the liquid crystal panel 1. However, even when the application software that is sufficient for 2-gradation display, such as when editing a document, is being executed or the application software that requires multi-gradation display is being executed, all circuits are It is configured to work. Therefore, in the 2-gradation display, the number of circuits required for operation is smaller than that in the multi-gradation display, so that power is supplied to unnecessary circuits, and accordingly, unnecessary power is consumed. become.

[0007] By the way, in portable computers such as notebook type personal computers, the demand for longer battery life is increasing year by year in addition to miniaturization and weight reduction. For this reason, in this type of computer, it is possible to reduce the size and weight of the battery by reducing the size of the battery and to extend the life of the battery. Therefore, low power consumption is an important issue.

As a technique related to such low power consumption, there is, for example, a technique disclosed in Japanese Patent Laid-Open No. 56992/1993. However, in this liquid crystal drive circuit, the power consumption of the liquid crystal drive circuit itself is reduced, and as for the power saving in the case of displaying with a small display gradation and a small display color as described above, Not considered.

An object of the present invention is to provide a display control device capable of reducing the power consumption by stopping the operation of the unused part depending on the display mode.

[0010]

In order to achieve the above object, according to the present invention, a plurality of display VRAM (video random access memory) planes are provided, and a plurality of floors are output based on output signals from the respective planes. A device for performing display control of a display device that performs gray scale or multi-color display, and a display read prohibition unit that selectively prohibits display read of each plane, and a plurality of gray scales based on output signals from all planes or According to the first path having a means for generating display data for multi-color display and the output of the display read prohibiting means, the output of the plane in which the display reading is not prohibited is selected and outputted as the display data. Means for selecting at least one second path having the means and a path through which the display read data passes according to the output of the display read prohibiting means. And a data non-passage section stopping means for stopping the operation of the portion of the first path when the data path selecting means selects a path other than the first path. Provided.

The display read prohibiting means has a register, and the register has VRA for each plane of VRAM.
It is possible to set a value indicating that display reading of M is prohibited.

The data path selecting means detects a display read prohibition detecting circuit for detecting whether or not display read is prohibited for any of the planes, and based on an output of the display read prohibition detecting circuit, Switch for selecting the first path if display reading is not prohibited for any of the planes, and selecting the second path if display reading is prohibited for any of the planes. It can be configured by including a circuit.

The data non-passage section stopping means detects a display read prohibition for any of the planes, and a display read prohibition detection circuit based on the output of the display read prohibition detection circuit. , And a gate circuit for interrupting the supply of the clock to the means for generating display data for displaying a plurality of gradations or a plurality of colors included in the first path.

When the output of the display read prohibition detection circuit does not prohibit display read for any plane, the gate circuit supplies a clock to prohibit display read for any plane. If so, one that shuts off the clock supply can be used.

The means included in the first path for generating display data for displaying a plurality of gradations or a plurality of colors can have a palette and a color conversion circuit.

Further, according to the present invention, a plurality of display VRs are provided.
Provided is a display control device including an AM plane, a unit for displaying a plurality of gradations or a plurality of colors based on an output signal from each plane, and a display read-out prohibiting unit for selectively prohibiting display read-out of each plane. It

[0017]

The display control device of the present invention is
A plurality of gradations or a plurality of colors are displayed based on the output signals from the plurality of display VRAM planes. According to the present invention, the display read-out prohibiting means can selectively prohibit the display read-out of each plane. For example, it is possible to prohibit reading of three of the four planes. As a result, VRAM that consumes a large amount of power
The power consumption can be reduced by suppressing the operation of part of the plane.

Further, according to the present invention, the output signal from the VRAM plane is sent to the display device via one of the paths selected from the plurality of paths. The first path, which is one of the paths, generates the display data based on the output signals from all the planes by the means for generating the display data for displaying a plurality of gradations or a plurality of colors. Also, the second
For the path of, the output of the plane in which the display reading is not prohibited is selected, and the output of the plane in which the display reading is not prohibited is selected according to the output of the display reading prohibiting means by the means for outputting as the display data. Output as display data.

The data path selecting means selects a path through which the display read data passes according to the output of the display read prohibiting means. That is, the data path selection means detects whether or not the display reading is prohibited for any of the planes by the display reading prohibition detecting circuit, and outputs the output of the display reading prohibition detecting circuit by the switch circuit. On the basis of this, if the display readout is not prohibited for any of the planes, the first path is selected, and if the display readout is prohibited for any of the planes, the second path is selected. Select.

The data non-passage section stopping means stops the operation of the portion of the first path when the data path selecting means selects a path other than the first path. That is, the data non-passage section stopping means detects whether or not the display reading is prohibited for any of the planes by the display reading prohibition detecting circuit, and based on the output of the display reading prohibition detecting circuit. The gate circuit cuts off the supply of the clock to the means for generating display data for displaying a plurality of gradations or a plurality of colors included in the first path, and stops the operation of the means. Here, when the output of the display read prohibition detection circuit does not prohibit display read on any of the planes, the gate circuit supplies a clock to prohibit the display read on any of the planes. If yes, shut off clock supply.

As a result, it is possible to stop the operation of the means for generating display data for displaying a plurality of gradations or a plurality of colors, which consumes a large amount of power.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. In addition, components with the same numbers as other drawings,
The signals are the same.

FIG. 1 is a schematic block diagram showing the configuration of an embodiment of the display control device. In FIG. 1, the display control device of the present embodiment is similar to that shown in FIG.
VRAM group 10a having VRAMs 10, 11, 12, and 13 that constitute .about.n, a VRAM control circuit 2, parallel-serial conversion circuits 14, 15, 16, and 17, and a palette 3.
And a color conversion circuit 4, and controls the display of the liquid crystal panel 1 capable of displaying a plurality of gradations or a plurality of colors via the liquid crystal i / F circuit 5. Although (n + 1) planes are used, it is assumed here that n = 3.

Further, the display control apparatus of the present embodiment further includes a register 6 for setting display read prohibition for each of the planes 0 to n, a binary data generating circuit 7 for forming a second path described later, and a second data generating circuit 7. A switch circuit 8 for selecting the 1st path and the 2nd path, a display read prohibition detection circuit 9 for detecting whether or not the display read is prohibited for any plane, and the display read prohibition. Based on the output of the detection circuit 9, the gate circuit 4 that shuts off the clock supply to the palette 3 and the color conversion circuit 4.
1, 42 and.

Here, 30, 31, 32, and 33 are display read data lines from the VRAMs 10, 11, 12, and 13, and 34, 35, 36, and 37 are parallel-serial conversion circuits 14, 15, 16, and 17. Serial data line from
Reference numeral 18 is a display data line output from the color conversion circuit 4, and 19 is a data non-passing portion stop line from the display read prohibition detection circuit 9.

This embodiment has a first path having a palette 3 and a color conversion circuit 4 and a second path having a binary data generating circuit 7. The palette 3 and the color conversion circuit 4 constitute means for generating display data for displaying a plurality of gradations or a plurality of colors based on output signals from all the planes 0 to n.

In this embodiment, the register 6 is a parallel-out register having bits b0 to bn corresponding to the number of planes (n + 1) of the VRAM plane group 10a. This register 6 is set with a value indicating that the display reading of the VRAM is prohibited for each plane of the VRAM. The set values b0, b1, b2, bn are output via the register output lines 20, 21, 22, 23. The register 6, together with the VRAM control circuit 2, constitutes a display read prohibiting means.

The VRAM control circuit 2 has a register output line 2
Register values on 0, 21, 22, 23 b0, b1, b2, bn
Are respectively associated with planes 0, 1, 2, and n, and when the respective set values are “0”, display readout of the corresponding plane is prohibited. On the other hand, if the set value is “1”, display reading is permitted. Therefore, when the set values of the register 6 are all "1", the display reading is not prohibited. An external switch may be used instead of the register 6.

The binary data generating circuit 7 registers each of the serial data lines 34, 35, 36, 37 for each plane 0 to n corresponding to each of the register output lines 20, 2.
AND gates 71 and 7 that take the logical product with 1, 22 and 23
2, 73, and 74, and an OR gate 75 that takes the logical sum of these outputs. This binary data generation circuit 7
According to the set value of the register 6, selects the output of the plane in which display reading is not prohibited and outputs it to the switch circuit 8 as display data.

The display read prohibition detection circuit 9 is, for example,
The register output lines 20, 21, 22, and 23 are configured by NAND gates (NAND circuits) that perform a logical product negation.
It outputs "0" or "1" according to the logical value of the register output lines 20, 21, 22, 23. That is, when the logical values of the register output lines 20, 21, 22, 23 are all "1", "0" is output.

The switch circuit 8 connects the output of the OR gate 75 and the output of the color conversion circuit 4 to the data non-passage section stop line 19.
Signal is used to selectively output one of them. The switch circuit 8 is combined with the display read prohibition detection circuit 9 to form a data path selecting means for selecting either the first path or the second path. That is, the switch circuit 8 selects the output of the color conversion circuit 4 when the signal of the data non-passing portion stop line 19 is "0" and is "1".
At the time of, the outputs of the binary data generation circuit 7 are selected and those outputs are output to the display data line 18.

Each of the gate circuits 41 and 42 is formed of a 2-input AND gate. The signal of the data non-passage stop line 19 is inverted and input to one of the two inputs, and the clock CLK is input to the other. Is entered. Therefore, in the gate circuits 41 and 42, the signal of the data non-passage stop line 19 is'
When it is 0 ', the clock CLK is input to the palette 3 and the color conversion circuit 4, and when the signal of the data non-passage stop line 19 is'1', the input of the clock CLK to the palette 3 and the color conversion circuit 4 is input. Cut off.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

In the register of the display read prohibiting means 6,
Normally, all bits are set to "1". First, this case will be described.

Since the register values b0 to bn are all "1", the VRAM control circuit 2 does not prohibit display reading.
Therefore, display reading is performed for all the planes 0 to n of the VRAM group 10a. Further, the display read prohibition detection circuit 9 outputs '0' to the data non-passage section stop output line 19 by the NAND gate. As a result, the clock CLK is supplied to the palette 3 and the color conversion circuit 4 via the gate circuits 41 and 42, and these are brought into an operating state. Further, the switch circuit 8 selects the first path and selects the output of the color conversion circuit 4 included therein.

As a result, the display read data of all planes are converted into parallel serial conversion circuits 14, 15, 16 and.
After being converted into serial data at 17, it is output to the display data line 18 as display data through the palette 3 and the color conversion circuit 4. The display data is sent to the liquid crystal panel 1 via the liquid crystal i / F circuit 5 and displayed.

This is the same operation as that of the conventional display control device shown in FIG.
The contents of n VRAMs are displayed in a plurality of gradations or a plurality of colors.

Next, the case where the register value b0 of the display read prohibiting means 6 is "1" and all other values are "0" will be described.

In the VRAM control circuit 2, the register b0
.About.bn are associated with planes 0 to n of VRAM, and when each bit is "0", display reading of the corresponding VRAM plane is prohibited. Therefore, under the above conditions, display readout is prohibited for all but plane 0. Also,
In the display read prohibition detection circuit 9, a NAND gate outputs "1" to the data non-passage section stop line 19. As a result, the gate circuits 41 and 42 shut off the clock CLK and stop the operations of the palette 3 and the color conversion circuit 4. On the other hand, the switch circuit 8 selects the binary data generation circuit 7 because the signal of the data non-passage stop line 19 is “1”. In the binary data generation circuit 7, only the AND gate 74 is in a state capable of outputting the output of the parallel-serial conversion circuit 14. That is, VRAM1 of plane 0
Only the data read from 0 is the binary data generation circuit 7
Is output from.

Therefore, in this case, V of plane 0 is
The data read from the RAM 10 passes through the binary data generation circuit 7 and the switch circuit 8 and the display data line 1
8 is output. As a result, the liquid crystal panel 1 performs the 2-gradation display obtained from the information of the VRAM 10 of the plane 0.

Now, consider the power consumption at this time. Unlike the CPU access, the VRAM display readout is continuously and seamlessly performed. Therefore, the memory used for VRAM is
A large amount of power is consumed. For these reasons, VRAM
By performing display readout only on the plane 0 and not performing display readout on the other planes among the planes 10 to 13, the power consumption of the planes 1 to n not performing display readout can be significantly reduced.

The operation of the pallet 3 and the color conversion circuit 4 is stopped by the data non-passing portion stopping means, and the power consumption of that portion can be reduced. Palette 3, Color conversion circuit 4
Is a high-speed operation part that operates at a speed of one dot of the display. Generally, in a digital circuit, the power consumption increases as the operating frequency increases, so the power consumption reduction by stopping this part is significant. It will be

As a result of the above, in the display control device of FIG.
The display by the output from the value data generation circuit 7 shows 2
Although the gradation display is performed, the display read prohibition means limits the plane of the VRAM for display readout, and the display read prohibition detection circuit 9 and the gate circuits 41 and 42 stop the operations of the palette 3 and the color conversion circuit 4. It is possible to significantly reduce power consumption.

Here, if it is desired to perform display from information other than the two-gradation information obtained from the VRAM 10 of the plane 0, for example, the register value of the display reading means 6 is set to b0 being "0",
By setting b1 to “1”, b2 to “0”, and bn to “0”, two-gradation display obtained from the VRAM 11 of the plane 1 is performed, and the register value of the display reading means 6 is changed. Can handle.

This register may be a register directly accessed by the CPU or may be directly changed by an external switch. Also, this register may be set by using a dedicated tool before executing the application software, or may be changed by detecting a specific key input during the execution of the application software by using interrupt processing. ..

In the above embodiment, the case where the two paths of the first and second paths are provided as the path has been shown, but the present invention is not limited to this. For example, the second path is
It also includes the case where two or more systems are provided.

In the above embodiment, one function is as follows.
Although described, it can be configured in combination with other functions. For example, it can be combined with a general reverse display in liquid crystal display or switching of gradation display. Also,
It can also be incorporated as part of the power management processing in the information processing apparatus.

In the above-mentioned embodiments, the display device of the liquid crystal panel has been described, but other plasma display, electroluminescent, CRT display and the like are also applicable. Further, the final display is not limited to the two-gradation display, and the number of gradations or the number of colors smaller than the initial number of display gradations or the number of colors can be applied. In this case, there is an effect of power saving for the VRAM.

[0049]

According to the present invention, depending on the display mode,
The power consumption can be reduced by stopping the operation of the unused part. As a result, for example, by limiting the number of display gradations or the number of colors during the execution of application software sufficient for two-gradation display such as a word processor,
Power consumption of the display control circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a display control device of the present invention.

FIG. 2 is a timing chart showing the operation of the display control device.

FIG. 3 is a block diagram of a conventional display control device.

[Explanation of symbols]

1 ... Liquid crystal panel, 2 ... VRAM control circuit, 3 ... Palette, 4 ... Color conversion circuit, 5 ... Liquid crystal i / F circuit, 6 ... Register, 7 ... Binary data generation circuit, 8 ... Switch circuit, 9 ...
Display read prohibition detection circuit 10, 11, 12, 13, ...
VRAM, 14, 15, 16, 17 ... Parallel-serial conversion circuit, 18 ... Display data line, 19 ... Data non-passing portion stop line, 20, 21, 22, 23 ... Register output line, 3
0, 31, 32, 33 ... Display read data line, 34,
35, 36, 37 ... Serial data lines, 41, 42 ... Gate circuits.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takashi Abe, Inventor Takashi Ara, Narashino, Chiba Prefecture, 7-1, 1-1 Higashi Narashino Office Systems Design and Development Center, Hitachi, Ltd. (72) Inventor Takeshi Shiobara Yoshida, Totsuka-ku, Yokohama, Kanagawa 292 In stock company Hitachi Imaging Information Systems (72) Inventor Susumu Onodera Yoshida-cho, Totsuka-ku Yokohama, Kanagawa Prefecture 292 House In Hitachi Imaging Information System (72) Incorporator Takeshi Maeda Yoshida-cho Totsuka-ku, Yokohama-shi Kanagawa 292 In stock company Hitachi Image Information System (72) Inventor Masahiko Otaki Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture 292 In stock company Hitachi Image Information System (72) Inventor Nobuyuki Kobayashi Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefecture No. 292 Incorporated company Hitachi Image Information Systems (72) Inventor Sakae Nemoto Kanagawa Hitachi Image Information System, Hitachi, Ltd. 292 Yoshida-cho, Totsuka-ku, Yokohama-shi

Claims (8)

[Claims] 1. A plurality of display VRAMs (video random numbers)
Access memory) is a device for controlling the display of a display device having a plane and displaying a plurality of gradations or a plurality of colors based on an output signal from each plane, and selectively prohibits the display reading of each plane. In accordance with the first path having a display read-out prohibiting means and a means for generating display data for displaying a plurality of gradations or a plurality of colors based on the output signals from all the planes, and the output of the display read-out prohibiting means The output of a plane whose reading is not prohibited is selected and at least one second path having a means for outputting it as display data and a path through which the display reading data passes are selected according to the output of the display reading prohibiting means. When the data path selecting means and the data path selecting means select a path other than the first path, the movement of the portion of the first path is performed. Display control device characterized by comprising a data non-transmission unit stopping means for stopping the. 2. The display control device according to claim 1, wherein the display read prohibition means has a register, and a value indicating the display read prohibition of the VRAM is set in the register for each plane of the VRAM. 3. A display read prohibition detection circuit for detecting whether or not display read is prohibited for any of the planes, and the display read prohibition detection circuit according to claim 1. If the display readout is not prohibited for any plane based on the output of, the first path is selected, and if the display readout is prohibited for any of the planes, the first path is selected. A display control device having a switch circuit for selecting two paths. 4. The display non-passage detecting circuit according to claim 1, wherein the data non-passing section stopping means detects a display read prohibition for detecting whether or not display read is prohibited for any plane. A display control device comprising: a gate circuit that cuts off the supply of a clock to a unit that generates display data for displaying a plurality of gradations or a plurality of colors included in the first path based on the output of the detection circuit. 5. The gate circuit according to claim 4, wherein when the output of the display read prohibition detection circuit does not prohibit display read for any of the planes, a clock is supplied to the gate circuit for any of the planes. A display control device that cuts off the supply of the clock when the display reading is prohibited. 6. The display control device according to claim 5, wherein the means for generating display data for displaying a plurality of gradations or a plurality of colors included in the first path has a palette and a color conversion circuit. 7. The display control device according to claim 6, wherein the gate circuit is provided for the palette and the color conversion circuit. 8. A plurality of display VRAMs (video random)
Access memory) plane, a unit for displaying a plurality of gradations or a plurality of colors based on an output signal from each plane, and a display read-out prohibiting unit for selectively prohibiting display read-out of each plane. Display controller.