JPH05341725A - Display control device - Google Patents

Abstract

PURPOSE:To enable display timing control adapted to various flat panel displays by permitting to arbitrarily set the timing of a horizontal synchronizing signal and a shift clock. CONSTITUTION:A generation position and stop position of a horizontal synchronizing signal LP for a flat panel display are controlled by timing information set in a horizontal synchronizing signal start position register 302 and a horizontal synchronizing signal finish position register 303, and a stop position of a shift clock signal SCK is controlled by timing information set in a shift clock stop position register 304 Therefore, timing of the horizontal synchronizing signal LP and the shift clock SCK can be arbitrarily set by changing a setting value of these register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
In particular, the present invention relates to a display control device that controls the display timing of various flat panel displays.

[0002]

2. Description of the Related Art Recently, various portable laptop or notebook type portable computers have been developed.

A typical portable computer of this kind is equipped with a flat panel display such as a plasma display or a liquid crystal display as a standard equipment. This flat panel display is rotatably provided in the range between the closed position and the open position with respect to the computer body. When the flat panel display is set to the closed position, the flat panel display is positioned to cover the keyboard integrated with the computer body, which makes the computer easy to carry. Therefore, the flat panel display is suitable for a portable computer in terms of improving its portability.

Further, recent portable computers are equipped with a video output terminal to a CRT display so that a CRT display can be connected if necessary. Since the CRT display has been widely used as a monitor of a desktop type personal computer, many application programs for the CRT display have been developed. Therefore, the portable computer that can use the CRT display can effectively use the existing software resources, and can perform the same operation as the desktop type personal computer. A conventional display control device for this type of portable computer includes a display timing control circuit as shown in FIG.

The display timing control circuit shown in FIG. 6 is a CRT.
Display, a flat panel display composed of one panel (hereinafter referred to as FLT1S), and a flat panel display composed of two panels respectively corresponding to an upper screen and a lower screen (hereinafter referred to as FLT1S).
2S) is a control target, and is provided with a circuit for generating three types of horizontal synchronizing signals suitable for each.

The horizontal sync signal for a CRT display is
Horizontal total register 111, CRT horizontal timing counter 112, CRT horizontal synchronization start position register 11
3, the CRT horizontal synchronization end position register 114, the comparators 115 to 117, and the horizontal synchronization signal generation flip-flop 118.

Data display is performed while scanning horizontally from left to right. In the case of a CRT display, the number of characters in the horizontal direction is counted by the CRT horizontal timing counter 112 and counted up by the character unit clock (CRCK). The value of the CRT horizontal timing counter 112 is the CRT horizontal synchronization start position register 11
3 becomes equal to the value set by the BIOS, the comparator outputs "1" to set the CRT horizontal synchronization signal generation flip-flop 118 at the next CRCK, and
Output to RT. Further, when the CRT horizontal timing counter 112 continues to count up and becomes equal to the value set by the BIOS in the CRT horizontal synchronization end position register 114, the comparator 117 outputs "1" to generate the CRT horizontal synchronization signal at the next CRCK. The flip-flop 118 is reset so that the horizontal sync signal is stopped. Further, the CRT horizontal timing counter 112 is
The counter value is stored in the horizontal total register 111 as BIO.
When the total number of horizontal characters set by S is matched, the initial value is reset by the "1" output of the comparator 115.

The horizontal synchronizing signal of FLT1S is FLT1S.
Horizontal sync start position register 211, FLT1S horizontal sync width register 212, display enable signal generation circuit 21
3. By the FLT1S synchronization signal generation counter 214,
It is generated as follows.

In the case of FLT1S, the count synchronized with CRCK is FLT1 with reference to the cutoff point of the display enable signal generated by the display enable signal generation circuit 3.
The FLT1S horizontal synchronization signal having a width from the value of the FLT1S horizontal synchronization signal start position register 211 set by the BIOS to the value of the FLT1S horizontal synchronization signal width register 212 is generated by the S synchronization signal generation counter 214, It is sent to the selector 216. When the flat panel display equipped in the portable computer is FLT1S, the horizontal sync signal for FLT1S is selected by the selector 216, and FL
Output to T1S flat panel display. F
The horizontal synchronizing signal of the LT2S is the display enable signal generating circuit 213 and the FLT2S synchronizing signal generating counter 21.
5 produces the following:

In the case of the FLT2S, the FLT2S synchronization signal generation counter 215 starts counting in synchronization with the basic clock with reference to the point where the display enable signal generated by the display enable signal generation circuit 213 is cut off. To the FLT2S synchronization signal generation counter 215, a horizontal synchronization signal for FLT2S having a width up to a value fixed by hardware is generated.
When the flat panel display equipped in the portable computer is FLT2S, the horizontal synchronizing signal for FLT2S is selected by the selector 216, and FLT2S is selected.
It is output to the S flat panel display.

The display timing control circuit also includes
In order to generate the shift clock SCK output to the flat panel display, the shift clock generation circuit 2
17 and a shift clock delay circuit 218 are provided. The shift clock SCK is used as a synchronizing signal for shifting and fetching display data into a shift register in the flat panel display.

During the period when the display enable signal is generated from the display enable signal generating circuit 213, the shift clock generating circuit 7 outputs the display data for one line corresponding to the next display line to the shift register in the flat panel display. In order to take in, the shift clock SCK is sequentially generated and output based on the basic clock.

The shift clock SCK for the flat panel display is output by the shift clock delay circuit 8 for several clocks even after the display enable signal is cut off and the non-display period is started. This is to match the delay of circuit operation in the flat panel display. This delay in circuit operation occurs in the following cases, for example.

That is, recent flat panel displays employ techniques such as frame thinning (sometimes referred to as frame rate control) in order to realize multi-gradation / multi-color display. In the frame thinning, one screen is divided into a plurality of frames, and display data between the frames is controlled to change the effective value of the driving voltage to realize multi-gradation / multi-color display. In the flat panel display having such a mechanism, the display data processed by the frame thinning circuit is incorporated in the shift register of the line buffer.

In this case, the frame thinning circuit first
For example, serial display data consisting of 4 bits per pixel is sequentially fetched in synchronization with the shift clock SCK. Then, when 4 bits are fetched, data corresponding to the 4-bit value is generated and transferred to the shift register of the line buffer. The operation timing of this frame thinning circuit is shown in FIG.

As shown in FIG. 7, the display control device has a 4-bit serial display data and a shift clock S.
Output CK synchronously. The frame thinning circuit sequentially fetches 4-bit serial display data in synchronization with the shift clock SCK. And the frame thinning circuit
At the time of fetching 4 bits, the thinned-out data output corresponding to the 4-bit value is generated and the internal shift clock SCK 'is generated. The thinned-out data output is taken into the shift register in synchronization with the internal shift clock SCK '.

As described above, in the frame thinning circuit, the internal shift clock SCK 'whose timing is delayed by the circuit delay is generated, and the internal shift clock SCK is generated.
The thinned-out data output is fetched in the shift register in synchronization with '.

Here, the internal shift clock SCK 'is
Usually, it is generated by using the shift clock from the display control device. Therefore, the display control device outputs the display data for one display line and then outputs the shift clock SCK.
Need to be output extra. In FIG. 7, the case where the display data of the fourth pixel is the final data and the shift clock SCK is output for three extra clocks after the display data is output is shown. The number of extra shift clocks SCK to be output differs depending on the type of panel and the type of frame thinning circuit.

As described above, in the conventional case,
There is a drawback in that a dual timing generation circuit for FLT1S and FLT2S is required in order to generate the horizontal synchronization signals having different timings for LT2S.

In the shift clock SCK, since the delay number by the delay circuit 8 is fixed in terms of hardware, the type of panel to be controlled changes, and the number of clocks required for processing such as frame thinning within the panel changes. Even if it did, it was not possible to set the number of delays accordingly.

[0021]

Conventionally, since a double timing generation circuit is required to generate horizontal synchronization signals with different timings for a flat panel display, the number of circuits is increased and the shift clock is Since the number of delays is fixed, there is a drawback in that the number of delays of the shift clock cannot be set depending on the type of flat panel display panel.

The present invention has been made in view of the above circumstances, and allows the timings of the horizontal synchronizing signal and the shift clock to be arbitrarily set, so that the display timing suitable for various flat panel displays can be obtained with a simple circuit configuration. An object of the present invention is to provide a display control device capable of performing control.

[0023]

Means and Actions for Solving the Problems
In a display control device provided in a portable computer having a flat panel display and controlling display timing of the flat panel display, a counter circuit for counting horizontal scanning timing of the flat panel display in dot units, and the flat panel display A first register in which timing information indicating the generation and stop position of the supplied horizontal synchronization signal is set by the CPU of the portable computer, the timing information set in the first register, and the count value counted by the counter circuit. According to the above, a horizontal sync signal generation circuit for controlling the generation and stop timing of the horizontal sync signal, and a timing indicating a stop position of a shift clock signal supplied to the flat panel display. Second register in which the CPU information of the portable computer is set by the CPU of the portable computer, the shift clock signal is sequentially generated in a predetermined cycle, and the timing information set in the second register and the count counted by the counter circuit And a shift clock generation circuit that controls the stop timing of the shift clock signal according to the value.

In this display control device, the generation position and the stop position of the horizontal synchronizing signal are controlled by the timing information set in the first register, and the shift clock signal is set in the second register. The stop position is controlled by. Therefore, the timings of the horizontal synchronizing signal and the shift clock signal can be arbitrarily set by changing the setting values of these registers. Therefore, display timing control suitable for various flat panel displays can be realized with a simple circuit configuration without providing a plurality of circuits having different timings. Further, the counting of the scanning timing in the horizontal direction is performed in dot units, not in character units, so that the timings of the horizontal synchronizing signal and the shift clock can be accurately controlled.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

First, with reference to FIG. 1, the configuration of the entire system of a display control device according to an embodiment of the present invention will be described. This display control system 4 is, for example, 640 × 48.
VGA (V with a display mode of simultaneous display of 0 dots and 16 colors)
This is a display control system of the ideo Graphics Array) specification, and is connected to the system bus 2 of the portable computer via the bus connector 3. The display control system 4 performs display control on both the flat panel display 40 that is standardly equipped in the main body of the portable computer and the color CRT display 50 that is optionally connected.

The display control system 4 is provided with a display controller (DISP-CONT) 10, an image memory (VRAM) 25, and a RAMDAC (D / A converter with color table) 30. These display controllers (DISP-CONT) 1
0, image memory (VRAM) 25, and RAMDAC
The (D / A converter with color table) 30 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array, and is a main part of the display control system 4. The display controller 10 serves as an interface between the CPU 1 of the portable computer and the display control system via the bus connector 3 and the system bus 2. Further, the display controller 10 is an image memory (VRAM).
25 and a RAMDAC (D / A converter with color table) 30 are used to execute display control for the flat panel display 40 and the color CRT display 50.

The image memory (VRAM) 25 stores display data for displaying on the flat panel display 40 or the color CRT display 50 in a memory plane system. This memory plane method divides the memory area into multiple planes specified by the same address,
This is a method of assigning color information of each pixel to these planes. In the VGA specification, since the image memory (VRAM) 25 is composed of 4 planes, the display data for one pixel is
It consists of 4-bit data, one bit for each plane. The data input / output port (MDATA) of the image memory (VRAM) 25 has a 32-bit width, and data is input / output in 8-bit units for each plane. Therefore, from the image memory (VRAM) 25,
Display data for 8 pixels is read by one read access.

The RAMDAC 30 is for generating R, G, B analog color video signals for the color CRT display 50, and has a color table which uses the data supplied to the address input (A) as an index. It is composed of a D / A converter for converting color data read from the color table into an analog signal. 2 x 320 x 200 dots for VGA specifications
Since there is a display mode of 56-color simultaneous display, the color table includes 256 color registers in order to support this display mode. Each color register stores a total of 18-bit color data consisting of 6 bits for each of R, G, and B. The color data stored in the selected color register is D
It is converted into analog R, G, B signals by the / A converter and supplied to the CRT display 50. The value of the color data set in the color table is RAMDAC
It is determined by the write data from the CPU 1 supplied to the data input (D) of 30.

The display controller 10 includes a clock control circuit 11, a display timing control circuit 12, a parallel register group 13, and an address control circuit 1 as shown in the figure.
4, display address control circuit 15, raster operation control circuit 16, parallel / serial conversion circuit (P / S)
17, memory control circuit 18, color palette table 1
9, a multiplexer 20, and a flat pallet control circuit 21. The function of each of these circuits is
It is as follows.

The clock control circuit 11 uses the system bus 2
Based on the clock OSC from the basic clock BCK,
Divided clock VD2LD and character unit clock C
Generate RCK. The basic clock BCK is a clock that serves as a reference for the circuit operation of the display controller 10. Divided clock VD2LD is a basic clock BCK
Is a clock (BCK / 2) obtained by dividing the frequency by two. The character unit clock CRCK is a clock indicating the horizontal size (8 dots) of one character (for example, 8 × 12 dots).

The display timing control circuit 12 is a feature of the present invention, and is a flat panel display 4
0 and the display timing of the CRT display 50 are controlled. That is, the display timing control circuit 12 uses the basic clock BCK from the clock control circuit 11, the divided clock VD2LD, and the character unit clock CRCK.
And various control signals (horizontal synchronization signal LP, vertical synchronization signal FP, and shift clock SC) for controlling the display timing of the flat panel display 40 based on the timing information set in the parallel register group 13.
K) and various control signals (horizontal synchronizing signal HSYN) for controlling the display timing of the CRT display 50.
C, vertical sync signal VSYNC). The shift clock SCK for the flat panel display 40 is
It is used as a data shift signal for shifting and fetching display data into the flat panel display 40. Further, the display timing control circuit 12
Issues an interrupt request signal (IRQ) to the CPU 1. Details of the circuit configuration of the display timing control circuit 12 will be described later with reference to FIGS.

The parameter register group 13 holds various display parameters such as the display mode of the flat panel display 40 and the CRT display 50 and the display timing. This parallelism is given from the CPU 1 via the data bus (D15-0). The reading / writing of the parameter to the parameter register group 13 is controlled by the I / O read signal (I / OR) and the I / O write signal (I / OW).

The address control circuit 14 includes an image memory (V
A memory address for read / write access to the RAM 25 is generated. When the display data is written in the image memory (VRAM) 25, the address (SA19-0) given from the CPU 1 is converted into a memory write address by the address control circuit 14, and the address port (MADDR) of the image memory (VRAM) 20 is converted. ) Is supplied to. On the other hand, when the display data is read from the image memory (VRAM) 25, the display address control circuit 1
Under the control of 5, the memory read address is sequentially supplied from the address control circuit 14 to the address port (MADDR) of the image memory (VRAM) 20. The address control circuit 14 also generates a write address W1 when writing color data to the RAMDAC 30.

The raster operation control circuit 16 has a function of writing the data supplied from the CPU 1 via the data bus (D15-0) to the image memory (VRAM) 25 as display data, and the function stored in the image memory (VRAM) 25. It has a drawing function for executing various calculations on the displayed data. At the time of drawing, the raster operation control circuit 16 executes a predetermined logical operation on the display data read from the image memory (VRAM) 25 to process the data, and the processed data is again processed in the image memory (VRAM). ) 25. The contents of the drawing operation are
It is controlled by the operation parameter set in the parameter register group 13.

Parallel / serial conversion circuit (P / S) 1
Reference numeral 7 denotes an image memory (VRA) in order to sequentially cut out 32 bits (8 pixels) of display data read from the image memory (VRAM) 25 at a time in units of 4 bits.
M) The 8-bit data read from each of the four planes 20 are parallel / serial converted into serial data.

The memory control circuit 18 uses an image memory (VRA
M) 20 for access control, and controls generation of various control signals CONT (write enable signal, output enable signal, row address strobe signal, column address strobe signal, etc.). The generation operation of the control signal CONT is performed by the memory read signal (MEMR) and the memory write signal (MEMW) from the CPU 1.
Controlled by. Further, the memory control circuit 18 is
An I / O channel ready signal (IOCHRDY) is generated in order to extend the bus cycle of PU1.

The color palette control circuit 19 is for determining the color attribute of the display data of 4 bits / pixel output from the parallel / serial conversion circuit (P / S) 17, and displays the 4 bits / pixel. It has a color palette table that inputs data as an index. This color palette table is provided with 16 color palette registers, and each color palette register contains 6 color palette registers for defining color attributes of display data.
Bit color palette data is stored. The color palette data is written by the CPU 1 via the data bus (D15-0). 6 stored in the color palette register selected by the display data
Two bits output from the color selection register built in the color palette control circuit 19 are added to the bit data, and a total of eight bits of data are output. The 8-bit data is supplied to the flat palette controller 21 and the address multiplexer 20 as CRT video data. The 8-bit CRT video data is used as the read address R1 of the RAMDAC 30.

The address multiplexer 20 selects one of the read address R1 and the write address W1 and RA
It is supplied to the address input (A) of the MDAC 30. The operation of selecting the read address R1 and the write address W1 is RA
Read signal (RD) output from the flat palette control circuit 21 for read / write control of the MDAC 30
And a write signal (WR).

The flat pallet control circuit 21 is a RAM
By emulating the color data of the DAC 30 for the flat panel display 40, color or monochrome gradation video data FVD for the flat panel display 40 is generated. Further, the flat pallet control circuit 21 controls the read / write operation of the RAMDAC 30. FIG. 2 shows the configuration of the horizontal synchronizing signal generating circuit provided in the display timing control circuit 12 which is a feature of the present invention.

This horizontal synchronizing signal generating circuit generates a horizontal synchronizing signal HSYNC for the CRT display 50, a horizontal synchronizing signal LP for the flat panel display 40 and a shift clock SCK. CRT display 5
The circuit for generating the horizontal synchronization signal HSYNC for 0 has a horizontal total register 111, a CRT horizontal timing counter 112, and a CRT horizontal timing counter 112, as in the conventional configuration shown in FIG.
CRT horizontal synchronization start position register 113, CRT horizontal synchronization end position register 114, comparators 115-11
7 and a horizontal synchronization signal generation flip-flop 118.

The circuit for generating the horizontal sync signal LP for the flat panel display 40 includes a flat horizontal timing counter 301, a flat horizontal sync signal start position register 302, a flat horizontal sync signal end position register 303, and a shift clock end position register. 304,
Display enable generation circuit 305, load signal generation circuit 3
06, comparators 307 and 308, and a flat horizontal synchronization signal generation flip-flop 310.

Flat horizontal timing counter 301
Counts the horizontal scanning timing of the flat panel display 40 in units of 2 dots per pixel in synchronization with the frequency-divided clock VD2LD. The flat panel display 40 normally counts in units of 2 dots per pixel as described above.
This is because, in both cases of LT2S, the data for two dots is simultaneously fetched. The initial count value "00" of the flat horizontal timing counter 301 is the basic clock BCK when the load signal generation circuit 306 outputs the load signal HLD.
And is loaded on the flat horizontal timing counter 301 in synchronization with.

Flat horizontal sync signal start position register 3
The timing information indicating the horizontal synchronization start position is stored in 02. This timing information is set by the CPU 1 by executing the BIOS program. The flat horizontal synchronization start position register 303 stores timing information indicating the horizontal synchronization end position. This timing information is also set by the CPU 1 by executing the BIOS program.

The display enable generation circuit 305 generates a display enable signal indicating a horizontal display period based on the display start signal SCKST output from the comparator 115. The load signal generation circuit 306 generates the load signal HLD with reference to the end of display when the display enable signal is cut off. The comparator 307 outputs a match signal when the count output HTMC of the flat horizontal timing counter 301 and the value of the flat horizontal sync signal start position register 302 match. The comparator 308 outputs the count output HT of the flat horizontal timing counter 301.
When the MC and the value of the flat horizontal sync signal end position register 303 match, a match signal is output.

The flat horizontal synchronization signal generation flip-flop 310 is for outputting the flat horizontal synchronization signal LP, and is set by the coincidence output of the comparator 307 and reset by the coincidence output of the comparator 308.

The horizontal synchronizing signal generating circuit constructed as described above operates as follows. Here, a display operation of the flat display 40 having a resolution of 640 × 480 dots corresponding to the VGA specification will be described as an example.

The display is performed while scanning one dot in the horizontal direction from left to right. The number of characters in the horizontal direction is counted by the CRT horizontal timing counter 112 and counted up by the character unit clock CRCK. CRT
When the counter value of the horizontal timing counter 112 reaches 80 characters, the display of the first line ends. At this time,
Load signal HLD created by load signal generation circuit 306
Thereby, the initial value "00h" is loaded and the operation of the flat horizontal timing counter 301 starts. The divide-by-2 clock VD2LD is an enable signal for the counter 301, and has a period of 2 dots per pixel as described above.

When the counter 301 counts up to 00, 01, ... And becomes equal to the value set in the flat horizontal synchronizing signal start position register 302, the comparator 307 outputs "1" and the next basic clock BCK. The flat horizontal sync signal generation flip-flop 310 is set at. This causes the horizontal synchronizing signal LP to rise. Further, the counter 301 continues to count up, and when it becomes equal to the value set in the horizontal sync signal end position register 303, the comparator 308 outputs “1” and the flat horizontal sync signal generation flip-flop 310 at the next basic clock BCK. Is reset. This causes the flat horizontal synchronizing signal LP to fall.

The shift clock generation circuit comprises a shift clock end position register 304, a comparator 309, a shift clock enable flip-flop 311 and a shift clock generation flip-flop 312.

The shift clock end position register 304 stores timing information indicating the end position of the shift clock SCK. This timing information is set by the CPU 1 by executing the BIOS program. The comparator 309 outputs a match signal when the count output HTMC of the flat horizontal timing counter 301 and the value of the shift clock end position register 304 match.

The shift clock enable flip-flop 311 has a shift clock enable signal SCKEN.
The display enable signal maintains the set state during the display period, and is reset by the coincidence output of the comparator 309 after the display period ends. The shift clock generation flip-flop 312 has a divide-by-2 clock VD2LD and a basic clock BCK while the shift clock enable signal SCKEN is enabled.
The shift clock SCK is generated based on The operation of generating the shift clock SCK is performed as follows.

When display is started, the display enable signal is enabled "1", whereby the shift clock enable flip-flop 311 is set and the shift clock enable signal SCKEN of "1" is generated. This "1" shift clock enable signal SCK
During the period when EN is generated, the divide-by-2 clock VD2LD is latched by the shift clock generation flip-flop 312 at the timing of the basic clock BCK,
As a result, the shift clock SCK having the same cycle as the frequency-divided clock VD2LD is output from the shift clock generation flip-flop 312. After the display is finished, the flat horizontal timing counter 301 starts the counting operation by the input of the load signal HLD, and when the counter value becomes equal to the value of the shift clock end position register 304, the comparator 309 outputs “1”. Output. Then, the shift clock enable signal SCKEN becomes "0" at the timing of the next basic clock BCK, the shift clock generation flip-flop 312 is reset at the timing of the next basic clock BCK, and the shift of the next line starts. Clock SC
The generation of K is stopped. FIG. 3 shows an example of a specific configuration of the horizontal synchronization signal generation flip-flop 310.

As shown, the horizontal sync signal generation flip-flop 310 includes AND gates 401, 402 and J-.
K flip-flop 403, OR gates 404 and 40
5, a NAND gate 406, and a D flip-flop 407. First of AND gate 401
The output of the comparator 307 is input to the input, and the divide-by-2 clock VD2LD is input to the second input. The output of the AND gate 401 is supplied to the J input of the JK flip-flop 403. The output of the comparator 308 is input to the second input of the AND gate 402, and the divide-by-2 clock VD2LD is input to the second input. The output of the AND gate 402 is supplied to the K input of the JK flip-flop 403.

The basic clock BCK is input to the clock input CK of the JK flip-flop 403, and its J-
The inverted Q output (QN) of the K flip-flop 403 is OR
It is supplied to the first input of the gate 404. The divide-by-2 clock VD2LD is input to the second input of the OR gate 404, and the output of the OR gate 404 is the NAND gate 406.
Is output to the first input of. The output of the OR gate 405 is input to the second input of the NAND gate 406.
The output of the NAND gate 406 is the D flip-flop 4
07 D input. This D flip-flop 4
The basic clock BCK is supplied to the clock input CK of 07. The Q output of the D flip-flop 407 is supplied to the flat panel display 40 as the horizontal synchronizing signal LP. The inverted Q output (QN) of the D flip-flop 407 is supplied to the second input of the OR gate 405 whose inverted signal of the divided-by-2 clock VD2LD is input to the first input. OR gates 404 and 405, and NAN
The D gate 406 constitutes a selector, and VD2LD
When = 1, the inverted Q output (QN) of the JK flip-flop 403 is selected, and when VD2LD = 0, the inverted Q output (QN) of the JK flip-flop 407 is selected.

FIG. 4 shows the display enable generation circuit 30.
5, shift clock enable flip-flop 31
1, and shift clock generation flip-flop 312
An example of a specific configuration of is shown.

The display enable generation circuit 305 uses the JK
It is composed of a flip-flop 501. The display start signal SCKST is input to the J input of the JK flip-flop 501.
Is input, and the load signal HLD is supplied to the K input,
The basic clock BCK is supplied to the clock CK input.

The shift clock enable flip-flop 311 is composed of an AND gate 601, a JK flip-flop 602, and an OR gate 603.
A comparator 309 is connected to the first input of the AND gate 601.
Of the divided clock V is input to the second input thereof.
D2LD is input. The output of the AND gate 601 is supplied to the K input of the JK flip-flop 602. The load signal HLD is supplied to the J input of the JK flip-flop 602, and the basic clock BCK is supplied to the clock CK input. The Q output of the JK flip-flop 602 is supplied to the first input of the OR gate 603. The second input of the OR gate 603 is J-
The display enable signal FVDTEN, which is the Q output of the K flip-flop 501, is input, and the OR gate 603 is also provided.
Is supplied to the shift clock generation flip-flop 312 as the shift clock enable signal SCKEN.

Shift clock generation flip-flop 31
2 is an AND gate 701 and a D flip-flop 7
It consists of 02. The shift clock enable signal SCKEN is input to the first input of the AND gate 701, and the divide-by-2 clock VD2LD is input to the second input thereof. The output of the AND gate 701 is supplied to the D input of the D flip-flop 702. The basic clock B is input to the clock CK of the D flip-flop 702.
CK is supplied, and the Q output of the D flip-flop 702 is output as the shift clock SCK. Next, the operation of generating the horizontal synchronizing signal LP and the shift clock SCK will be described with reference to the timing chart of FIG.

This timing chart shows the timing of the horizontal synchronizing signal LP and the shift clock SCK in the graphics mode of horizontal 640 dots.
In this timing chart, HCNT07-00
Signal indicates the count value of the CRT horizontal timing counter 112 that counts the horizontal direction in character units (here, 8 dots = 1 character), and counts from 0 to 87 characters. In the HDSP, only the display area of 0 to 87 characters is "1". Here, since there are 640 horizontal dots and 1 character of 8 dots, 0 to 79 characters are the display area. FVD is a flat panel display 4 output from the flat pallet control circuit 21 of FIG.
Display data for 0, which is output for two dots at the same time. These 2 dots are flat panel display 40
Corresponds to an odd dot and an even dot of the same scanning line, and when the flat panel display 40 is FLT2S, it corresponds to one dot on each of the upper screen and the lower screen. FVDTEN is a display enable signal, and here, 0 to 8 in consideration of the delay of the display data FVD.
It is set to enable during the period of up to 3 characters. The signal HTMC05-00 is the counter value of the flat horizontal timing counter 301 as described above, and the load signal HLD is flat at the timing of the second divide-by-2 clock VD2LD after HCNT07-00 indicates "83". It is input to the horizontal timing counter 301, and the initial value “00” is loaded into the horizontal timing counter 301 at the timing of the next basic clock BCK. After that, the horizontal timing counter 301 counts up in synchronization with the divided clock VD2LD.

Thereafter, the horizontal total register 111 has the value "53h" (53h = the total number of horizontal characters 88-5), and the flat horizontal sync signal start position register 302 has the value "06".
h ”, the value“ 0Eh ”in the flat horizontal sync signal end position register 303, and the shift clock end position register 304
The operation of generating the horizontal synchronizing signal LP and the operation of generating the shift clock SCK will be described by taking the case of setting the value "02h" as an example. First, the operation of generating the shift clock SCK by the circuit of FIG. 4 will be described.

When the display is started, the display start signal SC
KST = 1, so that the JK flip-flop 501 of the display enable generation circuit 305 is set,
The display enable signal FVDTEN = 1. The display enable signal FVDTEN is the JK flip-flop 5
It remains "1" until the reset condition of 01 (HLD = 1) is satisfied. Display enable signal FVDTEN
When = 1, the OR circuit 603 outputs the shift clock enable signal SCKEN of “1”. The shift clock enable signal SCKEN of "1" is logically ANDed with VD2LD by the AND gate 701. Then, the result of the logical product delayed by one basic clock BCK is output from the D flip-flop 702 as the shift clock SCK. That is, when the shift clock enable signal SCKEN = 1, VD2
The inversion signal of LD becomes the shift clock SCK. As described above, the shift clock SCK is continuously output during the display period. Next, the display area ends, and the shift clock SCK
The operation of stopping the operation will be described.

When the load signal HDL of "1" is input, the JK flip-flop 501 is reset and becomes the display enable signal EVDTEN "0". Also, J
-The K flip-flop 602 receives the load signal H of "1".
It is set when DL is input, and its Q output becomes "1". Therefore, the shift clock enable signal SCKEN output from the OR gate 603 remains "1".

On the other hand, when the load signal HLD = 1, the flat horizontal timing counter 301 is loaded with the initial value "00", and the counting operation of the flat horizontal timing counter 301 is started. When the count value HTMC of the flat horizontal timing counter 301 matches the value “02h” of the shift clock end position register 304, the comparator 309 outputs a match signal of “1”. This AND signal of "1" is ANDed with VD2LD by the AND gate 601 and the JK flip-flop 602 is reset by the ANDed output. As a result, the shift clock enable signal SCKEN output from the OR gate 603 becomes "0", and the shift clock SCK is stopped. in this way,
The stop position of SCK can be adjusted in units of VD2LD according to the setting value of the shift clock end position register 304. Next, the operation of generating the horizontal synchronizing signal LP by the circuit of FIG. 3 will be described.

As described above, the flat horizontal timing counter 301 starts counting when the load signal HLD of "1" is input. When the count value HTMC matches the value “06h” of the horizontal sync signal start position register 302, the comparator 307 outputs a match signal of “1”. The match signal of "1" is the AND gate 4
At 01, the logical product is obtained with VD2LD, and when the logical product is "1", the JK flip-flop 403 is set. As a result, the QN of the JK flip-flop 403 is
The output (FLTLP signal) becomes "0". OR gate 4
A selector composed of 04, 405 and NAND gate 406 selects the QN output of the JK flip-flop 403 when VD2LD = 0. Therefore, FLTLP
= 0, the output of the NAND gate 407 becomes “1” only when VD2LD = 0, and the horizontal synchronizing signal LP of “1” becomes D flip-flop 40 after one basic clock BCK.
It is output from the Q output of 7. When VD2LD = 1, D
Since the inverted Q output (QN) of the flip-flop 407 is selected, the output of the NAND gate 407 is maintained at "1".

Further, the flat horizontal timing counter 301 continues counting, and when the count value HTMC matches the value "0Eh" of the horizontal sync signal end position register 303, the comparator 308 outputs a match signal of "1". The match signal of "1" is the AND gate 4
At 02, the logical product is obtained with VD2LD, and when the logical product is "1", the JK flip-flop 403 is reset. As a result, the Q of the JK flip-flop 403 is
The N output (FLTLP signal) becomes "1". After that, FL
As in the case of TLP = 0, OR gates 404 and 40
5, the NAND gate 406 operates and the horizontal synchronizing signal L
P becomes "0".

As described above, in this embodiment, the horizontal sync signal LP for the flat panel display 40 is generated at the position where the horizontal sync signal LP is generated by the timing information set in the horizontal sync signal start position register 302 and the horizontal sync signal end position register 303. And the stop position is controlled, and the stop position of the shift clock signal SCK is controlled by the timing information set in the shift clock end position register 304.

Therefore, the timings of the horizontal synchronizing signal LP and the shift clock SCK can be arbitrarily set by changing the set values of these registers. Therefore,
Display timing control suitable for various flat panel displays can be performed without providing a plurality of circuits having different timings. Further, the horizontal scanning timing is counted by the flat horizontal timing counter 301 not by character, but by a clock indicating the horizontal scanning timing of the flat panel display 40 in dot units (here, 2 per pixel).
Since it is executed in synchronization with the dot cycle clock VD2LD), the horizontal synchronization signal LP and the shift clock SC
The timing of K can be controlled accurately.

For a flat panel display that does not need to output an extra shift clock SCK, the shift clock SC is set by setting the set value of the shift clock end position register 304 to "00h".
It is also possible to eliminate the extra output of K.

[0071]

As described in detail above, according to the present invention,
The timings of the horizontal synchronizing signal and the shift clock can be arbitrarily set, and display timing control suitable for various flat panel displays can be performed with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a display control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a display timing control circuit in the display control device in the embodiment.

3 is a circuit diagram showing a main part of a horizontal sync signal generation circuit for a flat panel display provided in the display timing control circuit of FIG.

4 is a circuit diagram showing a main part of a shift clock generation circuit for a flat panel display provided in the display timing control circuit of FIG.

5 is a timing chart illustrating the operation of the display timing control circuit of FIG.

FIG. 6 is a circuit diagram showing a configuration of a conventional display timing control circuit.

FIG. 7 is a timing chart for explaining how a delay shift clock generated from a conventional display timing control circuit is used in a flat panel display.

[Explanation of symbols]

12 ... Display timing control circuit, 301 ... Flat horizontal timing counter, 302 ... Horizontal sync signal start position register, 303 ... Horizontal sync signal end position register, 30
4 ... Shift clock end position register, 310 ... Flat horizontal synchronization signal generation flip-flop, 311 ... Shift clock enable flip-flop, 312 ... Shift clock generation flip-flop.

Claims (1)

[Claims] 1. A display control device, provided in a portable computer having a flat panel display, for controlling display timing of the flat panel display, comprising: a counter circuit for counting horizontal scanning timing of the flat panel display in dot units; A first register in which timing information indicating the generation and stop positions of the horizontal synchronizing signal supplied to the flat panel display is set by the CPU of the portable computer, and the timing information set in the first register and the counter circuit A horizontal synchronization signal generation circuit that controls the generation and stop timing of the horizontal synchronization signal according to the counted value, and stop of the shift clock signal supplied to the flat panel display A second register in which the timing information indicating the position is set by the CPU of the portable computer, the shift clock signal is sequentially generated in a predetermined cycle, and the timing information set in the second register and the counter circuit counts. And a shift clock generation circuit that controls the stop timing of the shift clock signal according to the counted value.