JPH05335914A - Power supply resetting circuit - Google Patents

Abstract

PURPOSE:To provide a power supply resetting circuit capable of obtaining the operating time of a desired time constant with the small capacitance of a capacitor. CONSTITUTION:A constant current source 11 charges up a capacitor C1 at the time of the application of power. When the terminal voltage of the capacitor C1 reaches a prescribed voltage, a comparator 16 is used to release the resetting. In order to reduce the charging current, the resetting circuit is provided with a shunt circuit composed of a transistor(TR) 12 and a current mirror circuit CM1. Thus, the charging time is prolonged even with the small capacitance of the capacitor C1 and a sufficient operating time is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply reset circuit which is used in a contactless switch such as a photoelectric switch or a proximity switch and which stops output for a predetermined time in order to prevent malfunction when power is turned on.

[0002]

2. Description of the Related Art In a contactless switch, the circuit voltage is not stable immediately after the power is turned on and the operation becomes unstable. Especially in a high-frequency oscillation type proximity switch, etc., the object can be detected only after the oscillation circuit normally starts oscillating.
It is necessary to stop the output operation for a predetermined time after the power is turned on. Therefore, the contactless switch is provided with a power supply reset circuit so that the contactless switch output is output to the outside only after a predetermined time elapses after the power is turned on and the voltage reaches a predetermined voltage. Known as such a power supply reset circuit is a reset circuit in which an integrating capacitor is charged with a minute current and the output is delayed depending on the time until the voltage reaches a predetermined voltage. According to such a conventional reset circuit, the delay time is determined by the capacitance of the integrating capacitor.

However, it is difficult to use a capacitor having a large shape in a contactless switch which is required to be downsized, and for example, only a capacitor having a capacitance of several tens pF or less can be used. Therefore, in order to lengthen the delay time, the capacitors are integrated by the Miller integrating circuit using Darlington connection. FIG. 4 and FIG. 5 are diagrams showing these conventional power supply reset circuits by Miller integration. For example, a constant current source 1 of about several μA is used,
It is assumed that the two NPN transistors 2 and 3 are Darlington connection, an integrating capacitor C is inserted between the collector and the base of the transistor 2, and the capacitance of the capacitor C is equivalently multiplied by the current amplification factor (hfe) of the two transistors. .. Then, the terminal voltage is detected by the comparator 4 to obtain the delay time. Similarly in FIG. 5, NP
The Miller integrating circuit is configured by Darlington connection using the N-type transistor 5 and the PNP-type transistor 6.

[0004]

In such a conventional circuit, the charging current of the capacitor is determined by the amplification factor of the transistor forming the Miller integrator circuit, but since the value greatly varies, the reset time also varies greatly. There was a problem.

The present invention has been made in view of the problems of the conventional power supply reset circuit, and provides a power supply reset circuit in which the capacitance of the capacitor is reduced and the operating time of a desired time constant is obtained. The purpose is to do.

[0006]

SUMMARY OF THE INVENTION The present invention is a power supply reset circuit for stopping output for a predetermined time after power is turned on, and it integrates capacitors for integration (C1, C3) and when the power supply voltage reaches a predetermined value. A current source for supplying a charging current to the capacitors for charging (C1, C3), a reset canceling means (16) for canceling a reset when the charging voltage of the integrating capacitor reaches a predetermined value, and a current mirror circuit. A shunt means (12, CM1, 23, CM2) for shunting the current of the power source and reducing the ratio of the charging current to the integrating capacitor by making a part of the current flowing out of the current source the charging current.
And are provided.

[0007]

In the present invention having such characteristics, the current from the current source is shunted by the shunting means when the power is turned on,
A part of it flows into the integrating capacitor as a charging current to charge the capacitor. By making this shunting device a part of the charging current, the capacitance of the capacitor can be reduced and a long time constant can be obtained. When the charging voltage of the capacitor reaches a predetermined value, the reset canceling means cancels the reset.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first power reset circuit according to the present invention.
It is a circuit diagram which shows an Example. In this figure, a voltage detection circuit 10 is provided between both ends of the power supply. Voltage detection circuit 1
Reference numeral 0 is a detection circuit for detecting whether or not the power supply voltage exceeds a predetermined operable value, and when the power supply voltage exceeds the predetermined value, an output is given to the constant current source 11. The constant current source 11 supplies a constant current of, for example, several μA to the emitter of the transistor 12 when an output is given from the voltage detection circuit 10. The collector of the transistor 12 is the transistor 13,
Is connected to a current mirror circuit CM1 composed of 14
Its base is grounded via an integrating capacitor C1. A discharging transistor 15 having an emitter and a collector connected to both ends of the integrating capacitor C1 is provided, and its base is connected to a power supply. Transistor 1
It is assumed that the emitter areas of 3 and 14 are formed on the IC chip so that the emitter area of 1S to nS, that is, the emitter of the transistor 14 is n times. The collector of the transistor 14 of the current mirror circuit CM1 is commonly connected to the constant current source 11 together with the emitter of the transistor 12, and is further supplied to the comparator 16. Here, the transistor 12 and the current mirror circuit CM1 configure a shunting unit that diverts the current of the constant current source 11 to reduce the ratio of the charging current flowing into the capacitor C1. Further, the comparator 16 is a reset releasing means for providing an output that enables the contactless switch when the voltage of the capacitor C1 reaches a predetermined value.

Next, the operation of the above-described first embodiment will be described. FIG. 2 is a waveform diagram showing the waveform of each part of this contactless switch. In this figure, if the power is turned on at time t ₀ as shown in FIG. 2A, then the power supply voltage rises. When the power supply voltage reaches a predetermined value, the voltage detection circuit 10 gives a voltage detection output to the constant current source 11. Then, a constant current flows out from the constant current source 11, and the transistor 12 and the transistor 14 of the current mirror circuit CM1.
And a current flows into the integrating capacitor C1. The collector current of the transistor 12 is hfe times the current flowing into the capacitor C1, and as described above, the transistors 13, 1
Since the emitter area of 4 is 1S to nS, the collector current is amplified by n times by the current mirror circuit CM1. Therefore, the current of the constant current source 11 is shunted, and 1+ (n + 1) × hfe times the charging current flowing into the capacitor C1 flows into the transistors 12 and 14, and most of the current flowing out from the constant current source 11 is transferred to the transistor 12. , 14 At this time, since the base of the transistor 15 is connected to the power supply, the transistor 15 is reverse-biased and is in the off state. Therefore, FIG. 2 (b)
As shown in, the terminal voltage of the capacitor C1 gradually rises, and the collector voltage of the transistor 14 also rises accordingly. Then, when the voltage reaches a predetermined level at time t ₁ , the comparator 16 outputs an output as shown in FIG. 2C, and thereafter the contactless switch can be operated.

When the power switch is turned off at time t ₂ , the power supply voltage drops and the base potential of the transistor 15 also drops. Then, the emitter of the transistor 15 becomes higher than the base potential due to the charge of the integrating capacitor C1, so that the transistor 15 becomes conductive, and the integrating capacitor C1 is rapidly discharged as shown in FIG. 2 (b).
Therefore, even if again the power switch at the time t ₃ is turned so that it is possible to operate reliably power reset circuit by the same operation.

FIG. 3 is a circuit diagram showing a second embodiment of the power supply reset circuit according to the present invention. In this embodiment, FIG.
The same parts as are indicated by the same reference numerals. In the present embodiment, the auxiliary capacitor C2 and the integrating capacitor C3 are connected to the constant current source 11, the emitter / collector of the discharging transistor 20 is connected to both ends of the integrating capacitor C3, and the base thereof is connected to the power source end. .. The other end of the integrating capacitor C3 is connected to a current mirror circuit CM2 composed of transistors 21 and 22, and the current mirror circuit CM2 performs current amplification by making the emitter areas different as in the first embodiment. The collector of the transistor 22 is connected to the base of the transistor 23 for current amplification. The emitter of the transistor 23 is commonly connected to the constant current source 11 together with the integrating capacitor C3, and is also connected to the comparator 16. Current mirror circuit CM
2 and the transistor 23 constitute a shunt means for shunting the current flowing out of the constant current source 11 and making a part of it a charging current of the capacitor C3 to reduce the ratio of the charging current to the capacitor.

Also in this embodiment, when the power is turned on and the detection output is given from the voltage detection circuit 10 to the constant current source 11, current is supplied from the constant current source 11 to the capacitors C2 and C3. Here, the charging current flowing through the capacitor C3 is amplified by the current mirror circuit CM2 and the transistor 23. Therefore, most of the current flowing out from the constant current source 11 is drawn into the transistor 23, and the ratio of the charging current to the capacitor C3 is significantly reduced. Therefore, it takes a long time to charge the capacitor C3. Here, the reset operation at power-on is stopped by the output of the comparator 16 until the terminal voltage of the capacitor C3 reaches a predetermined value. During this period, the transistor 20 is reverse-biased and thus is in the off state.

When the power is turned off, the electric charge of the auxiliary capacitor C2 is discharged through the emitter / base of the transistor 20, and the transistor 20 is turned on. Therefore, the integrating capacitor C3 is short-circuited and rapidly discharged. Therefore, even if the power is subsequently turned on, the power reset circuit can be operated again.

[0014]

As described above in detail, according to the present invention, the current from the current source is shunted to be the charging current for the capacitor, so that the operating time can be made sufficiently long even if the capacitance of the capacitor is small. You can Therefore, it can be integrated into an IC together with a small-capacity capacitor, and a power supply reset circuit can be configured without increasing the IC mounting area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a power supply reset circuit for a contactless switch according to the present invention.

FIG. 2 is a waveform diagram showing the operation of the power reset circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the power reset circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional power supply reset circuit.

FIG. 5 is a circuit diagram showing an example of a conventional power supply reset circuit.

[Explanation of symbols]

1, 11 Constant current source 2, 3, 5, 6, 12 to 15, 20 to 23 Transistor 10 Voltage detection circuit 4, 16 Comparator C1, C2, C3 Capacitor CM1, CM2 Current mirror circuit

Front page continuation (72) Inventor Keinosuke Imazu 10 Ouron Co., Ltd., Hanazono-cho, Ukyo-ku, Kyoto City, Kyoto Prefecture Omron Co., Ltd.

Claims (3)

[Claims] 1. A power supply reset circuit for stopping output for a predetermined time after power-on, wherein the integration capacitors (C1, C3) and the integration capacitors (C1, C3) are provided when the power supply voltage reaches a predetermined value. A current source for supplying a charging current; a reset releasing means (16) for releasing a reset when the charging voltage of the integrating capacitor reaches a predetermined value; and a current mirror circuit, which divides the current of the current source. A shunting means (12, CM1, 23, CM2) for reducing the ratio of the charging current to the integrating capacitor by making a part of the current flowing out of the current source the charging current. Power reset circuit. 2. The power supply reset circuit according to claim 1, wherein the shunting means is a current mirror circuit including a pair of transistors having different area ratios. 3. The current shunting means is configured by cascading a current mirror circuit composed of a pair of transistors having different emitter areas and a current amplification transistor for amplifying the shunt current. The power supply reset circuit according to claim 1.