JPH05335342A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide processe for selectively eliminating only a first insulation film leaving an insulation film of the side wall portion at the time of removing an insulation film under the gate electrode by the etching in the process to form the desired gate electrode on a side wall consisting of a first insulation film opened on a compound semiconductor substrate and a third insulation film formed at the side wall of the aperture. CONSTITUTION:An insulation film side wall is formed in a double-layer structure comprising a film 3 as a lower layer having selectivity at the time of removing a first insulation film 2 by the etching and a film 4 as an upper layer which is suitable for side wall processing, that is, anisotropic etching. Thereby, selectivity for removing the first insulation film by the etching process can be ensured by the lower film, while processing control for the side wall may be optimized independently by optimization of the upper layer film. Moreover, the process having a higher stability can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a fine metal electrode of a compound semiconductor device.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view showing a conventional method of forming a fine gate electrode according to a manufacturing flow thereof. First, a first insulating film, for example, a plasma SiO film 2 is deposited on a compound semiconductor substrate 1 made of GaAs, the insulating film 2 is etched and opened, and then the compound semiconductor substrate 1 is etched to a desired depth. (Fig. 2 (a)).

Next, a third insulating film, for example, a plasma SiO film 4 is deposited on the entire surface of the substrate (FIG. 2 (b)). The third insulating film 4 is etched by anisotropic etching such as reactive ion etching (hereinafter referred to as RIE) to form a sidewall 4a on the side wall of the substrate opening (FIG. 2).
(c)).

After depositing the gate electrode metal film 5, eg, Au / Ti, on the entire surface of the substrate by sputtering, the metal film 5 other than the portion covering the opening is removed by etching (FIG. 2 (d)).

The plasma SiO film which is the first insulating film 2 is removed by isotropic etching, for example, wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride (FIG. 2).
(e)). The reason why the first insulating film 2 needs to be removed in the last step (FIG. 2E) is as follows.

As an example, when considering the case where the gate electrode 5 formed in the above process is applied to a low noise transistor, the noise figure Fmin, which is one of the figures of merit, is calculated using the equivalent circuit parameter of the transistor as follows. Is represented as Fmin = 1 + 2πKf · fCgs√ ((Rg + Rs) / gm) (1) Kf: Fitting parameter Cgs: Gate
Source capacitance Rs: Source resistance f: Operating frequency Rg: Gate resistance gm: Transconductance Therefore, as the gate electrode, (a) short gate length (Lg in FIG. 3) (b) low gate resistance (in FIG. 3) (Inversely proportional to the cross-sectional area of the gate electrode) (C) It is necessary that a low parasitic capacitance (the one shown as C'gs in FIG. 3 is also one of the parasitic capacitances). In order to satisfy the condition of (a), it is necessary to increase the cross-sectional area of the gate electrode, and there is a considerable amount of overlap between the upper part of the gate electrode and the first insulating film.

In the above state, if the first insulating film 2 is left as it is, parasitic capacitance C'gs is generated as shown in FIG. Therefore, it is necessary to reduce the dielectric constant and the capacitance by removing the insulating film 2 in this portion.

[0008]

In the conventional process flow, it is difficult to control the step of removing the first insulating film 2 in the final step, and the insulating film is removed too much to etch the sidewall (see FIG. 4 (a)) and the removal is insufficient (Fig. 4 (b)).

When excessive etching is performed as shown in FIG. 4A, when a passivation film is formed on the semiconductor device in a later step, the etched portion of the compound semiconductor substrate immediately below the gate electrode, that is, the recessed portion. It is extremely difficult to deposit a film up to and including. Since this portion is close to the active portion where the transistor operates, such passivation failure has a problem in reliability. Further, when the etching becomes insufficient as shown in FIG. 4B, there is a problem that the reduction of the parasitic capacitance becomes insufficient.

On the other hand, for the film forming the sidewall portion 4a, it is necessary to use a film type such as a SiO film that is unlikely to be laterally etched during anisotropic etching. In addition, in the step of removing the first insulating film 2, there are restrictions on the etching method having a sufficient selection ratio with respect to the sidewall film 4a and the selection of the type of the first insulating film 2.

The present invention has been made in order to solve the above problems, and it is possible to stably remove only the first insulating film while leaving the insulating film sidewall of the recess portion completely. At the same time, it is an object to provide a method for manufacturing a semiconductor device in which the gate electrode can be formed with a great degree of freedom in selection of the first and third insulating film types.

[0012]

According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein an insulating film serving as a sidewall is formed into a second structure.
2 layer structure consisting of the insulating film and the third insulating film, a film suitable for forming a sidewall on the third insulating film is used, and the second insulating film is etched for removing the first insulating film. At this time, a film having a low etching rate and capable of selectively removing the first insulating film is used.

[0013]

In the present invention, when the first insulating film is removed, the selectivity is realized by the second insulating film, and the sidewall is formed by the third insulating film. It is possible to form the sidewall having a good shape while stably removing the insulating film.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing method according to an embodiment of the present invention will be described below with reference to a sectional view according to the manufacturing flow of FIG. First, the compound semiconductor substrate 1 made of GaAs
Of the insulating film 2, for example, a plasma SiO film is deposited, the insulating film 2 is etched to form an opening, and then the compound semiconductor substrate 1 is etched to a desired depth (FIG. 1).
(a)).

Next, second and third insulating films 3, 4 such as a plasma SiN film and a plasma SiO film are successively deposited on the entire surface of the substrate (FIG. 1 (b)). In this case, the SiN film deposition conditions are: SiH4 flow rate: 100 sccm NH3 flow rate: 1000 sccm pressure: 2 Torr RF power: 0.04 W / cm2 SiO film deposition conditions are SiH4 flow rate: 100 sccm N2 O flow rate: 500 sccm NH3 flow rate: 500 sccm pressure: 2 Torr RF power: 0.04 W / cm2.

Next, RIE is performed using a mixed gas of CHF3 gas and O2 gas to etch the plasma SiO film 4 and the plasma SiN film 3 to form sidewalls 6 (FIG. 2 (c)).

Next, a gate electrode metal 5, for example Au / Ti, is deposited on the entire surface of the substrate by sputtering. Further, a photoresist mask (not shown) is formed by photolithography, and the metal film 5 other than the portion covering the opening is etched and removed by ion milling using Ar gas (FIG. 1 (d)).

Next, the first insulating film 2, plasma SiO
The film is removed by wet etching with a mixed solution of hydrofluoric acid and ammonium fluoride. At this time, the selection ratio of the SiO film 4 to the SiN film 3 can be set to about 5 to 10 by selecting the film forming conditions as described above (FIG. 1).
(e)).

Therefore, when the SiO film which is the first insulating film 2 is removed by the above-mentioned wet etching, the sidewall 6 formed of the second and third insulating films 3a and 4a in the recessed portion.
It is possible to selectively leave only.

According to this embodiment, when the first insulating film under the gate electrode is removed in the formation of the gate electrode, a film having high selectivity is used as the second insulating film. The insulating film sidewall can be stably left in the recessed portion, and the sidewall formation is stable by selecting a film type suitable for processing the sidewall shape for the third insulating film. Can be done.

[0021]

As described above, according to the present invention, in the method of forming a gate electrode, when the first insulating film under the gate electrode is removed, a film type having high selectivity is used as the second insulating film. By using it, it is possible to stably leave the insulating film side wall in the recess portion,
By selecting a film type suitable for processing into the sidewall shape as the insulating film, there is an effect that the sidewall formation can be performed stably.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing formation of a gate electrode according to an embodiment of the present invention according to a manufacturing flow thereof.

FIG. 2 is a cross-sectional view showing a conventional manufacturing flow.

FIG. 3 is a diagram showing a problem when the first insulating film is left without being removed.

FIG. 4 is a diagram showing a problem when the first insulating film is removed by a conventional method.

[Explanation of symbols]

 1 Compound Semiconductor Substrate 2 First Insulating Film 3 Second Insulating Film 4 Third Insulating Film 5 Gate Electrode Metal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H01L 29/50 J 9055-4M

Claims (2)

[Claims] 1. A first step of depositing a first insulating film on a compound semiconductor substrate, etching the insulating film to form an opening, and exposing the compound semiconductor substrate to the opening to a desired depth. A second step of etching, a third step of depositing an insulating film having a two-layer structure composed of a second insulating film and a third insulating film on the substrate, and the entire surface of the two-layer insulating film being etched back Thus, a fourth step of forming a so-called sidewall in the opening, and a fifth step of forming an electrode metal film on the entire surface and then etching away the metal film other than the portion completely covering the opening And a step of forming a gate electrode by completely removing the first insulating film from the surface of the substrate by an isotropic etching method having a sufficient selection ratio with respect to the second insulating film. And a step of manufacturing the semiconductor device. 2. The first insulating film is a plasma SiO film, the second insulating film is a plasma SiN film, and the third insulating film is a plasma SiO film. 1. The method for manufacturing a semiconductor device according to 1.