JPH05334268A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To attain a data transfer between plural arithmetic processing units by independently providing a parallel processor and a successive processor, connecting them through a network enabling the data transfer, carrying out a parallel processing by the storage processor of area data and a firmware which arithmetically processes the data, data-transferring the result to the successive arithmetic processing unit, and independently operating the successive arithmetic operation. CONSTITUTION:A parallel arithmetic processor 31 is connected through the network enabling the data transfer with a successive arithmetic processing unit 33, and a distributed processing is carried out. A space is area-divided by a finite element method or the like, and the information of the related areas and entire node constituting the areas is stored in a storage part based on the nodes constituting the area. The plural arithmetic processing units simultaneously prepare more than one simultaneous equation which fulfill the entire nodes in parallel, and transmit the data to the parallel or successive arithmetic processing unit, and the equation is solved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In this description, a plurality of arithmetic processing units and a sequential processing unit are made independent, and they are connected by a network that enables data transfer, and parallel processing operations and sequential processing operations are performed independently. The present invention relates to an arithmetic processing device, a storage processing device for area data, and firmware for arithmetically processing the same.

[0002]

2. Description of the Related Art A conventional arithmetic unit utilizes a single or a plurality of arithmetic units and divides a partial region of an arithmetic process into tasks and distributes them to a single or plural arithmetic units or performs continuous processing. When using such an arithmetic processing unit to discretize regions such as the finite element method and assemble and solve simultaneous equations that satisfy the governing equations in each divided region, use a data structure that depends on the divided regions. , A coefficient matrix matrix of simultaneous equations satisfying the governing equation in the order of elements is obtained by an arithmetic processing unit of sequential processing or parallel processing. An overall coefficient matrix satisfying the variable vectors of nodes in all areas was created for the simultaneous equations for each element obtained for all elements, and this was solved using an arithmetic processing unit for sequential processing or parallel processing.
In this method, when the simultaneous equations satisfying each element are individually created, it is assumed that the phenomena governed by the elements are independent, and therefore it is possible to perform the operation for each element and It was possible to perform distributed processing on the device.

In this case, however, in both cases where a plurality of arithmetic processing units share or independently hold a data storage area, an independently created coefficient matrix is composed of all final variables. It is necessary to expand to simultaneous equations and store it. In this case, it can not be processed by multiple processing devices,
A single processor needs to do this, and parallel processing takes less time than sequential processing to create the equations for each element, but the whole equation creation process takes more time. There was such a problem. In addition, the solution of the simultaneous equations cannot be processed in parallel in many cases because the operation results between the matrix elements are related. Due to these causes, it takes a long time to synthesize the equations and calculate the solution by the parallel arithmetic processing device alone, and at this time, there is a problem that many arithmetic machines are stopped. Further, in the sequential arithmetic processing device, there is a problem that it takes time to create an equation for each element.

[0004]

SUMMARY OF THE INVENTION The present invention is a network for enabling data transfer between a plurality of arithmetic processing devices in a plurality of arithmetic processing devices by making a parallel processing device and a sequential processing device independent. It is possible to combine these, perform parallel processing by the area data storage processing device and firmware that performs arithmetic processing on it, and transfer the result to the sequential arithmetic processing device and perform sequential processing operation independently. is there.

[0005]

A parallel processing device and a sequential processing device are combined to perform distributed processing.

[0006]

With the above arrangement, the parallel arithmetic processing device and the sequential arithmetic processing device can operate independently. Furthermore, it is possible to eliminate the data transfer for synthesizing a group of simultaneous equations that governs the area created by conventional elements into an equation that satisfies all areas, shortening the processing time and improving the operating rate of the processing equipment. It can be realized.

[0007]

【Example】

(Embodiment of the First Invention) FIG. 1 shows an embodiment of the first invention. 11 is a parallel arithmetic processing device, 12 is a sequential arithmetic processing device, 13 is a parallel arithmetic processing device 11 and a sequential arithmetic processing device 1.
It is a network that connects two and transfers data. The parallel arithmetic processing unit 11 and the sequential arithmetic processing unit 12 are driven and controlled by independent firmware, and mutual arithmetic results are exchanged using the network 13. As a result, since each arithmetic processing unit can perform its own processing, there is no problem of suspending a plurality of arithmetic units during sequential processing, which is a problem with conventional parallel processing computers. Computer efficiency is improved.

(Embodiment of the Second Invention) FIG. 2 shows an embodiment of the second invention. Reference numeral 21 denotes a parallel arithmetic processing unit composed of N arithmetic units, 22 denotes N storage areas of the N arithmetic units, 23 denotes a sequential arithmetic processing unit, and 24 denotes a storage region of the sequential arithmetic processing unit. Show. The parallel arithmetic processing device 21 is composed of N arithmetic units, and one arithmetic unit has a dedicated or shared storage area 22 and is capable of parallel processing. The sequential processing device 23 has one or more storage areas 24, and the storage area 24 can be divided into one or more storage areas for use. 25 is the i-th arithmetic unit of the parallel arithmetic processing unit 21, 26 is the storage area used by the i-th arithmetic unit 25 of the storage area 22 of the parallel arithmetic processing unit 21, 27 is the sequential arithmetic processing unit 23 The storage area obtained by dividing the storage area 24 is a network for connecting the parallel arithmetic processing device 21 and the sequential arithmetic processing device 23 and transferring data. FIG. 3 shows the matrix elements of simultaneous equations and the parallel arithmetic processing unit 3.
The data flow in the process of processing with one storage area 32 is shown. The processing flow is shown in FIG. The i-th arithmetic unit 35 sequentially calculates the equations in the i-th row or the i-th column and stores them in the i-th storage area. i-th computer 25
After the calculation is completed, the contents of the storage area 36 are transferred to and stored in the i-th storage area 37 of the storage area 34 of the sequential processing operation device 33 via the network 38. Do this for all of the equations. As a result, the parallel arithmetic processing unit 31 does not need to transfer data between the arithmetic units 31. Further, by simply transferring the data in the storage area 32 of the parallel arithmetic processing device 31 to the storage area 34 of the arithmetic processing device 33,
The equations to be solved by the sequential arithmetic processing unit 33 can be synthesized on the storage area 34 of the sequential arithmetic processing unit 33.

(Embodiment of the third invention) FIG. 5 shows a data storage device for storing data of nodes and elements in which regions are discretized according to an embodiment of the third invention. Reference numeral 51 denotes a node number storage unit, 52 denotes a node coordinate data storage unit, 53 denotes a plurality of node number storage units different from the node 51 sharing the element,
Reference numeral 54 is a coordinate of the node 53, and 55 is a storage unit of various data such as material data necessary for creating an equation of the region formed by the node 51 and the node 53. FIG. 6 shows an example of dividing the area. Reference numeral 61 is a target area, 62 is an i-th node when the area 61 is divided into N areas, and 63 is an area related to the i-th node 52.

As shown in FIG. 6, the i-th node 61 is e
Surrounded by areas 1 to e4, the area e1 to e4 is composed of nodes i and jklm. When the governing equations are sequentially created for e1 to e4 in the region 63, if one node has one variable, it is necessary to create a 4 × 4 simultaneous equation, but only the i row or i column for the node i is obtained. Nodes of i and j and e1 on both sides
The values of ii, ij, and ji of the simultaneous equations can be calculated by creating equations for the areas e1 and e4 from the material data of and e4. i and k are areas e
If 1 and e2 are performed, the values of ii, ik, and ki can be calculated, and il, li, im, and mi can be calculated in the same manner.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of an arithmetic unit according to an embodiment of the first invention.

FIG. 2 is a diagram showing a structure of an arithmetic unit according to an embodiment of the second invention.

FIG. 3 is a diagram showing the matrix elements of the simultaneous equations of the second invention, the storage area of the parallel arithmetic processing device, and the data flow in the processing process of the sequential arithmetic processing device.

FIG. 4 is a processing flow chart in the second invention.

FIG. 5 is a diagram showing a data storage device for storing data of nodes and elements obtained by discretizing an area according to the third embodiment of the invention.

FIG. 6 is a diagram showing an example of dividing a region.

[Explanation of symbols]

 31 parallel arithmetic processor 32 storage area 33 sequential arithmetic processing device 34 storage area 35 arithmetic machine 36 storage area 37 storage area

Claims (3)

[Claims] 1. An arithmetic processing device, wherein a parallel processing device and a sequential processing device are combined to perform distributed processing. 2. An arithmetic processing unit capable of parallel processing in which a plurality of arithmetic processing units capable of causing one or more arithmetic processing units to create row elements of a coefficient matrix having one or more rows of equations and a solution of the equation are calculated. An arithmetic processing unit characterized by performing parallel processing and distributed processing of sequential processing by connecting a sequential processing apparatus capable of performing other sequential processing including a function to perform. 3. A coefficient matrix of one or more rows of equations satisfying the variables given to a plurality of arithmetic processing units at the same time by having element information related to an arbitrary point and point information included in the related element at the same time. An arithmetic processing unit characterized by being configured to.