JPH05328776A - Limiting method and limiter operator - Google Patents

Abstract

PURPOSE:To provide a limiting method and a limiter operator which can limit an amplitude and a phase of a vector represented, when d-axis and q-axis PI control arithmetic signals are limited, by the signals in forms as near as an ideal form. CONSTITUTION:First and second control-operated signals are respectively limited to regular octagonal shape on first and second coordinate axes by using a variable gain multiplier 20, a d-axis limiter 13d and a q-axis limiter 13q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a limiter method and a limiter computing device for limiting a signal having two components on two orthogonal coordinate axes to within a predetermined range on a coordinate plane defined by the two coordinate axes. Regarding

[0002]

2. Description of the Related Art As is well known, in vector control of an induction motor, three-phase signals consisting of U-phase, V-phase and W-phase are once converted into two-phase signals in mutually orthogonal coordinate systems for processing. Is generally done. The conversion of the rotating coordinate system to the orthogonal stationary coordinate system is called dq conversion in this technical field.

In the vector control of this induction motor,
When performing control calculation such as PI control, it is necessary to apply a limiter to the signal subjected to the control calculation. Conventionally, the following three methods have been adopted as this limiter method.

(1) Limiter method on three-phase coordinates (see FIGS. 7 and 8) In this method, as shown in FIG.
The limiter is performed using the signals of the two phases, without performing q conversion.

In the example of FIG. 7, of the U-phase current signal i _U representing the U-phase current, the V-phase current signal i _V representing the V-phase current, and the W-phase current signal i _W representing the W-phase current, the U-phase After the PI control calculation is performed using the current signal i _U and the W-phase current signal i _W , a limiter is applied to the U-phase voltage signal V _U representing the U-phase voltage and the V-phase voltage signal V representing the V-phase voltage. _V , and W representing the W-phase voltage
The phase voltage signal V _W is output.

Hereinafter, the limiter arithmetic unit for realizing the limiter method on the three-phase coordinates will be described in detail with reference to FIG. This limiter arithmetic unit includes a U-phase subtractor 11U,
W-phase subtractor 11W and U-phase PI control calculator 12U
It has a W-phase PI control calculator 12W, a U-phase limiter circuit 13U, a V-phase limiter circuit 13V, a W-phase limiter circuit 13W, and a V-phase sign inversion adder 14V.

A U-phase current signal i _{U is} supplied to the U-phase subtractor 11U.
And a U-phase current command signal i _U * is supplied from a three-phase current command generation circuit (not shown). The U-phase subtractor 11U converts the U-phase current command signal i _U * to the U-phase current signal i _U.
Is subtracted from the U-phase current deviation signal Δi
Output _U. This U-phase current deviation signal Δi _U is a PI for U-phase
It is supplied to the control calculator 12U. The U-phase PI control calculator 12U executes PI control calculation on the U-phase current deviation signal Δi _U and outputs a U-phase PI control calculation signal indicating the PI control calculation result. The U-phase PI control calculation signal is supplied to the U-phase limiter circuit 13U because it needs to be limited within a predetermined range. The U-phase limiter circuit 13U is
The U-phase PI control calculation signal is limited so that its absolute value is within a predetermined range, and this limited signal is limited to the U-phase voltage signal V _U.
Output as.

Similarly, the W-phase current signal i _W is supplied to the W-phase subtractor 11W, and the W-phase current command signal i _W * is supplied from the three-phase current command generation circuit. W-phase subtractor 1
1W subtracts the W-phase current signals i _W from W-phase current command signal i _W *, W phase current deviation signal .DELTA.i _W representing the subtraction result
Is output. This W-phase current deviation signal Δi _W is W-phase PI
It is supplied to the control calculator 12W. The W-phase PI control calculator 12W executes the PI control calculation on the W-phase current deviation signal Δi _W and outputs the W-phase PI control calculation signal indicating the PI control calculation result. The W-phase PI control calculation signal is supplied to the W-phase limiter circuit 13W because it needs to be limited within a predetermined range. The W-phase limiter circuit 13W is
The W-phase PI control calculation signal is limited so that its absolute value is within a predetermined range, and this limited signal is limited to the W-phase voltage signal V _W.
Output as.

The U-phase voltage signal V _U and the W-phase voltage signal V _W are V
It is supplied to the phase sign inversion adder 14V. The V-phase sign inversion adder 14V is a signal − which is the inversion of the U-phase voltage signal V _U.
V _U and the signal −V _W obtained by inverting the W-phase voltage signal V _W are added, and an inverted / added signal representing the result of this inversion / addition is output. Since this inverted / added signal also needs to be limited within a predetermined range, the V-phase limiter circuit 13V
Is supplied to. The V-phase limiter circuit 13V limits the inverted / added signal so that its absolute value falls within a predetermined range, and outputs this limited signal as a V-phase voltage signal V _V.

As described above, the U-phase voltage signal V _U and the V-phase voltage signal V _V obtained from the limiter arithmetic unit shown in FIG.
And the W-phase voltage signal V _W is limited to the range of a regular hexagon, as shown in FIG.

The above-mentioned conventional example is a limiter method on three-phase coordinates. Next, a conventional limiter method for applying a limiter to the control-calculated signal after 3-phase / 2-phase conversion will be described. As described in detail below, there are two conventional limiter methods: a method in which the coordinates are directly changed on the orthogonal biaxial coordinates and a method in which the coordinates are converted. First, the former method will be described, and the latter method will be described subsequently.

(2) Limiter method on orthogonal two-axis coordinates (see FIGS. 9 and 10) In this method, as shown in FIG.
After the q conversion, the limits are directly applied to the d axis component and the q axis component.

The limiter arithmetic unit for realizing the limiter method on the orthogonal biaxial coordinates will be described in detail below with reference to FIG. This limiter arithmetic unit includes a three-phase / 2-phase (rotational coordinate) converter 10, a d-axis subtractor 11d, a q-axis subtractor 11q, a d-axis PI control arithmetic unit 12d, and a q-axis P.
An I control calculator 12q, a d-axis limiter circuit 13d,
It has a q-axis limiter circuit 13q and a two-phase / 3-phase (reverse rotation coordinate) converter 15.

The U-phase current signal i _U , the V-phase current signal i _V , and the W-phase current signal i _W are supplied to the 3-phase / 2-phase converter 10. The three-phase / two-phase converter 10 uses the three-phase current signals i
_U , i _V , and i _W are two-phase current signals, that is, dq (orthogonal) defined by the d axis and the q axis which are orthogonal to each other.
It is converted into a primary d-axis current signal i _1d and a primary q-axis current signal i _1q in the coordinate system.

The primary d-axis current signal i _1d is the d-axis subtractor 11
supplied to d. This d-axis subtractor 11d has a primary d
The axis current command signal i _1d * is supplied. Subtractor 11 for d-axis
d subtracts the primary d-axis current signal i _1d from the primary d-axis current command signal i _1d * and outputs a d-axis current deviation signal Δi _1d representing the subtraction result. The d-axis current deviation signal Δi _1d is supplied to the d-axis PI control calculator 12d. The d-axis PI control calculator 12d executes PI control calculation on the d-axis current deviation signal Δi _1d , and the d-axis PI indicating the PI control calculation result.
Outputs a control calculation signal. The d-axis PI control calculation signal is supplied to the d-axis limiter circuit 13d because it needs to be limited within a predetermined range. Limiter circuit 1 for d-axis
3d limits the d-axis PI control calculation signal so that its absolute value is within a predetermined range, and outputs this limited signal as a primary d-axis voltage signal v _1d .

Similarly, the primary q-axis current signal i _1q is supplied to the q-axis subtractor 11q. The primary q-axis current command signal i _1q * is supplied to the q-axis subtractor 11q. The q-axis subtractor 11q converts the primary q-axis current command signal i _1q * into the primary q
The axis current signal i _1q is subtracted, and the q axis current deviation signal Δi _1q representing the result of the subtraction is output. This q-axis current deviation signal Δ
i _1q is supplied to the q-axis PI control calculator 12q. The q-axis PI control calculator 12q executes PI control calculation on the q-axis current deviation signal Δi _1q , and outputs a q-axis PI control calculation signal representing the PI control calculation result. Since this q-axis PI control calculation signal needs to be limited within a predetermined range,
It is supplied to the q-axis limiter circuit 13q. The q-axis limiter circuit 13q limits the q-axis PI control operation signal so that its absolute value falls within a predetermined range, and outputs this limited signal as a primary q-axis voltage signal _v1q .

The primary d-axis voltage signal v _1d and the primary q-axis voltage signal v _1q are supplied to the 2-phase / 3-phase converter 15. 2 phase / 3
The phase converter 15 receives these two-phase voltage signals v _1d and v _1q.
Is converted into a three-phase voltage signal, that is, a U-phase voltage signal V _U , a V-phase voltage signal V _V , and a W-phase voltage signal V _W.

Therefore, d-axis and q-axis limiter circuits 13d and 13q of the limiter arithmetic unit shown in FIG.
The primary d-axis voltage signal v _1d and the primary q-axis voltage signal v _1q obtained from the above are the range of a square perpendicular to each of the two coordinate axes, d-axis and q-axis, as shown by the dotted line in FIG. Limited to within.

For example, a PI control computing unit 1 for d-axis and q-axis
The d-axis and q-axis PI control operation signals obtained from 2d and 12q (hereinafter, sometimes collectively referred to as PI amplifiers) are 1 as shown by vector A in FIG.
It is assumed that the signal is smaller than the lower limit value of the next d-axis voltage signal v _1d and larger than the upper limit value of the primary q-axis voltage signal v _1q . In this case, the d-axis limiter circuit 13d is the d-axis PI.
The control calculation signal is limited to the lower limit value of the primary d-axis voltage signal v _1d , while the q-axis limiter circuit 13q limits the q-axis PI control calculation signal to the upper limit value of the primary q-axis voltage signal v _1q. become. That is, as shown in FIG. 10, the vector A is limited to the vector A ″.
Is in the direction of 45 ° with respect to the d-axis and the d-axis, and its amplitude has a value of √2 times the limit value of each voltage signal.

However, originally, it is desired to limit the radius within the circle having the limit value, which is shown by the solid line in FIG. That is, it is ideal that only the amplitude of the vector A is within the limit value without changing the phase of the vector A like the vector A ′. In order to achieve this, in the conventional limiter method described below, the orthogonal coordinate system is coordinate-transformed into a polar coordinate system, the limit is performed on this polar coordinate, and the coordinate transformation is performed again into the orthogonal coordinate system.

(3) Limiter Method on Polar Coordinates (Refer to FIGS. 11 and 10) With reference to FIG. 11, a limiter arithmetic unit for realizing the limiter method on polar coordinates will be described in detail. This limiter arithmetic unit has a quadrature / polar form conversion circuit 16, an amplitude limiter 17, and a pole / orthogonal form conversion circuit 18 in place of the d-axis limiter circuit 13d and the q-axis limiter circuit 13q. And has a configuration similar to that shown in FIG. Therefore, components having the same functions as those shown in FIG. 9 are designated by the same reference numerals, and their description will be omitted.

The orthogonal / polar form conversion circuit 16 includes d-axis and q-axis PI control arithmetic units 12d and 12q for d-axis and q-axis.
An axis PI control calculation signal is supplied. The orthogonal / polar format conversion circuit 16 converts the orthogonal d-axis and q-axis PI control calculation signals into a polar amplitude control calculation signal and an angle signal. The amplitude control calculation signal is supplied to the amplitude limiter 17, and the angle signal is supplied to the polar / orthogonal format conversion circuit 18. Amplitude limiter 1
Reference numeral 7 limits the amplitude value of the amplitude control calculation signal so that it falls within a predetermined range, and outputs the limited signal as an amplitude voltage signal. This amplitude voltage signal is converted into a polar / orthogonal format conversion circuit 18
Is supplied to. The polar / orthogonal form conversion circuit 18 converts the polar form of the amplitude voltage signal and the angle signal into the orthogonal form of the primary d-axis voltage signal v _1d and the primary q-axis voltage signal v _1q . The primary d-axis voltage signal v _1d and the primary q-axis voltage signal v _1q are supplied to the 2-phase / 3-phase converter 15.

With such a configuration, the radius can be limited within the circle having the limit value as shown by the solid line in FIG. Therefore, unlike the vector A ′, the vector A can be kept within the limit value without changing the phase of the vector A.

[0024]

The conventional limiter method for applying a limiter to a signal which has been control-calculated after the above three-phase / two-phase conversion, that is, the limiter methods (2) and (3) described above, There are drawbacks as described in.

As described above, in the limiter method (2), the primary d-axis voltage signal v _1d and the primary q-axis voltage signal v _1q are limited to the square range as shown by the dotted line in FIG. Therefore, depending on the phase of the vector represented by the d-axis and q-axis PI control calculation signals, the limit value is up to √2 times the desired limit value, and the phase is also the middle of the d-axis and the q-axis.
That is, there is a drawback in that it moves in any direction of 45 °, 135 °, 225 ° and 315 °.

On the other hand, in the limiter method of the above (3), the orthogonal / polar form conversion circuit 16, the amplitude limiter 17, and the polar / orthogonal form conversion circuit 18 are used to generate data (d-axis and q-axis) of the orthogonal coordinate system. The PI control calculation signal) is once converted into polar coordinate system data (amplitude control calculation signal and angle signal), a limiter is added in the radial direction, and the orthogonal coordinate system data (primary d-axis voltage signal v _1d and primary q). It is necessary to convert back to the axial voltage signal v _1q ). For this reason, there are disadvantages that the calculation becomes complicated and the calculation time becomes long.

Therefore, a technical problem of the present invention is that, when limiting the d-axis and q-axis PI control calculation signals, the limiter method can limit the amplitude and phase of the vector represented by these signals as close to the ideal as possible. And to provide a limiter arithmetic unit.

Another technical object of the present invention is to provide a limiter method and a limiter calculation device which are simple in calculation and have a short calculation time.

[0029]

According to the limiter method of the present invention, a signal having two components on two orthogonal coordinate axes falls within a predetermined range on a coordinate plane defined by the two coordinate axes. A limiter method for limiting, wherein the predetermined range is a regular octagon that vertically crosses each of the two coordinate axes.

Further, the limiter computing device of the present invention, at least the first and second control-computed signals representing the first and second control computation values on the orthogonal first and second coordinate axes, respectively. The absolute value of the signal value of is limited within a predetermined range not exceeding a predetermined limit value, and the first and second
In a limiter computing device that outputs first and second limited signals that represent the limiting value of, the sum of absolute values of the first and second control-calculated signals is obtained, and the value of the sum is obtained. When the limit value is √2 times or less, the first and second control-calculated signals are left as they are, and when the sum value is √2 times the limit value or more, the first value is calculated. And a variable gain multiplication circuit that outputs a signal obtained by multiplying the second control-calculated signal by √2 times by the sum value, and outputs first and second converted signals, and the first conversion A first limiter circuit for limiting the absolute value of the processed signal so that the absolute value does not exceed the predetermined limit value and outputting the first limited signal; and the second converted signal,
A second limiter circuit for limiting the absolute value so as not to exceed the predetermined limit value and outputting the second limited signal; and the first and second control operations. It is possible to limit the generated signal to within a regular octagon on the first and second coordinate axes.

In the limiter calculation device, the variable gain multiplication circuit receives the signal which has been subjected to the first control calculation, obtains a first absolute value of the first control calculation value, and obtains the first absolute value. A first absolute value circuit that outputs a first absolute value signal that represents the second absolute value of the second control arithmetic value, and a second absolute value of the second control arithmetic value. A second absolute value circuit that outputs a second absolute value signal that represents the absolute value of, and the first absolute value and the second absolute value that receive the first and second absolute value signals. An adder that outputs a sum signal representing the sum value, and the sum signal. When the sum value is within √2 times the limit value, the sum value is limited to the limit value. If the sum value is equal to or greater than the limit value √2 times, the value is directly converted to the sum value, A conversion circuit that outputs a converted signal that represents the converted value; a divider that receives the converted signal, divides √2 by the converted value, and outputs a divided signal that represents the division value; Receiving a first control-calculated signal and the divided signal, the first control-calculated value is multiplied by the divided value, and the first multiplied signal representing the multiplication result is converted into the first multiplied signal. A first multiplier that outputs the converted signal, the second control-calculated signal, and the divided signal, and the second control-calculated value is multiplied by the divided value, A second multiplier that outputs a second multiplied signal representing a multiplication result as the second converted signal;
It is characterized by having.

Further, according to the limiter method of the present invention, an input signal having d and q components on the coordinate axes of the d and q axes which are orthogonal to each other is input to the d axis and the q axis and the value on the coordinate axes is 1.
And -1 to limit it to a regular octagon that traverses vertically at -1, where the d and q components are
√2 and −√2 on the d-axis and the q-axis, respectively
Restricting to a first constrained d component and a first constrained q component within a regular quadrangle connecting the four points of, and the first constrained d component and the first constrained d component. Limiting each q component to a second limited d component and a second limited q component, each of which has an absolute value of 1 or less.

[0033]

Embodiments of the present invention will now be described with reference to the drawings.

The limiter method according to the present invention uses two orthogonal 2
A limiter method for limiting a signal having two components on one coordinate axis (d-axis and q-axis) to a predetermined range on a coordinate plane defined by the two coordinate axes, wherein the predetermined range is two. It is a regular octagon that crosses each of the coordinate axes vertically.

The limiter arithmetic unit for realizing the limiter method according to the present invention will be described in detail below with reference to FIG. This limiter arithmetic unit includes a variable gain multiplication circuit 2 between the d-axis and q-axis PI control arithmetic units 12d and 12q and the d-axis and q-axis limiter circuits 13d and 13q.
It has the same configuration as that shown in FIG. 9 except that 0 is inserted. Therefore, elements having the same functions as those shown in FIG. 9 are designated by the same reference numerals, and their description will be omitted.

The variable gain multiplication circuit 20 finds the sum of the absolute values of the d-axis and q-axis PI control calculation signals. If the value of this sum is less than √2 times the limit value, the d-axis and q-axis PI When the value of the sum is √2 times the limit value or more with the control operation signal as it is, the signals obtained by multiplying the d-axis and q-axis PI control operation signals by √2 are respectively divided by the value of the sum,
The d-axis and q-axis converted signals are output.

The d-axis and q-axis converted signals are respectively d
It is supplied to the axis limiter circuits 13d and 13q for the q-axis. The d-axis limiter circuit 13d limits the d-axis converted signal so that its absolute value does not exceed a predetermined limit value, and outputs this limited signal as a primary d-axis voltage signal V _1d . Similarly, the q-axis limiter circuit 13q is
The q-axis converted signal is limited so that its absolute value does not exceed a predetermined limit value, and this limited signal is output as the primary q-axis voltage signal V _1q .

The variable gain multiplication circuit 20 is for the d-axis and q-axis.
Axis absolute value circuits 21 and 22, adder 23, conversion circuit 24, divider 25, d-axis and q-axis multiplier 26
And 27.

The d-axis absolute value circuit 21 receives the d-axis PI control calculation signal, obtains the d-axis absolute value of the d-axis PI control calculation result, and outputs the d-axis absolute value signal representing the d-axis absolute value. To do. Similarly, the q-axis absolute value circuit 22 receives the q-axis PI control calculation signal, obtains the q-axis absolute value of the q-axis PI control calculation result, and outputs the q-axis absolute value signal representing the q-axis absolute value. To do.

The adder 23 receives the d-axis and q-axis absolute value signals, calculates the sum of the d-axis absolute value and the q-axis absolute value, and outputs a sum signal representing the value of this sum. The conversion circuit 24 receives the sum signal, and if the sum value is within √2 times the limit value, converts the sum value into a value √2 times the limit value, and the sum value is √ the limit value. If it is more than double, use the sum as it is,
Output a converted signal that represents the converted value. Divider 25
Receives the converted signal and divides √2 by the converted value,
A divided signal representing this divided value is output.

The d-axis multiplier 26 receives the d-axis PI control calculation signal and the divided signal, multiplies the d-axis PI control calculation result by a division value, and represents the d-axis multiplication result by the d-axis multiplication. The generated signal is output as a d-axis converted signal. Similarly, q
The axis multiplier 27 receives the q-axis PI control calculation signal and the divided signal, multiplies the q-axis PI control calculation result by the division value, and outputs the q-axis multiplied signal representing the q-axis multiplication result. Output as a d-axis converted signal.

With such a configuration, the d-axis and q-axis PI
The control calculation signal can be limited to the d-axis and the regular octagon on the d-axis. In other words, the primary d-axis voltage signal V _1d and the primary q-axis voltage signal V _1q obtained from the d-axis and q-axis limiter circuits 13d and 13q of the limiter arithmetic unit shown in FIG. As shown, the two coordinate axes, the d axis and the q axis, are each constrained to fall within a regular octagon. In the example of FIG. 2, the limit value is set to 1.

In this method, the maximum radius is 1 / cos (22.5 °) = 1.082 times the radius of the inscribed circle.
The error in the radial direction can be reduced as compared with the case of limiting to the range of the square indicated by 0.

Further, the phase shift can be reduced by the procedure described later.

With reference to FIG. 2, an input signal having a d component Xd and a q component Xq on the orthogonal d-axis and q-axis coordinate axes will be described below with respect to the d-axis and the q-axis. A limiter method for restricting to a regular octagon that crosses vertically at -1 and -1 will be described. Here, the radius of the inscribed circle to be limited is set to 1.0.

First, the d component Xd and the q component Xq are defined as a first limited d component and a first limited d component in a regular quadrangle connecting four points of √2 and −√2 on the d axis and the q axis, respectively. Limit to a limited q component of 1.

For example, the d component Xd and the q component Xq are the first
In the case of the quadrant, the limit is within the straight line of Qp-dp in FIG. To realize this, first, d component X
The sum Xl = | Xd | + | Xq | of the absolute value | Xd | of d and the absolute value | Xq | of the q component Xq is obtained.

I) If Xl> √2, the input signal is Qp-
Since it is outside the straight line of dp, the d component Xd is the first limited d component Xd ′ = (√2 / X1) × Xd, and the q component Xq is the first limited q component Xq ′ = ( √2 / X
l) x Xq.

Ii) If Xl≤√2, the input signal is Qp-
Since it is within the straight line of dp, d component Xd and q component X
q remains as it is, that is, the first limited d component Xd
Let '= Xd and the first restricted q-component Xq' = Xq.

Next, the absolute value of each of the first limited d component Xd 'and the first limited q component Xq' is within 1, that is, within a range of ± 1.0. A second limited d component Xd ″ and a second limited q component Xq ″.

In other words, the limiter method of the present invention divides the first quadrant into four regions, that is, a region I, a region II, a region III, and a region IV, as shown in FIG.

Since the area I is within the regular octagon, no limit is applied to the signal in the area I.

The area II is outside the straight line connecting the √2 of the d-axis and the √2 of the q-axis, and is 2 in the counterclockwise direction from the d-axis.
It is a region above the straight line rotated by 2.5 ° and below the straight line rotated 22.5 ° in the clockwise direction from the d-axis. As for the signal in the region II, as shown in FIG. 4, the d component Xd and the q component Xq of the signal are equal to each other in X ratio.
Limit to d'and Xq '. Therefore, this limited signal (Xd ′, Xq ′) is on the straight line connecting the d-axis √2 and the q-axis √2.

The region III is a region outside the regular octagon and is a region inside a straight line connecting the d-axis √2 and the q-axis √2. For the signal in the region III, only one of the d component Xd and the q component Xq of the signal may be limited. For example, as shown in FIG. 5, in a region where the signal is III, a region surrounded by a d-axis, a straight line of d = 1, and a straight line connecting √2 of the d-axis and √2 of the q-axis In the case of, the d component Xd of the signal is set to the d component Xd ″ equal to 1, and the q component Xq of the signal remains unchanged (Xq ″ = Xq).

Region IV is a region in the first quadrant excluding the above three regions, that is, region I, region II, and region III. As for the signal in the area III, as shown in FIG. 6, a combination of the operation in the area II described above (restriction of equal ratio) and the operation in the area III (restriction of only one component). Limit by.

[0056]

As described above, according to the present invention, when a signal having two components on two orthogonal coordinate axes is limited within a predetermined range on a coordinate plane defined by the two coordinate axes. Since the above predetermined range is a regular octagon that crosses each of the two coordinate axes vertically, the maximum difference in the radial direction is 1.0.
It can be suppressed to about 8 times. Orthogonal biaxial axes for the first and second control arithmetically operated signals representing the first and second control arithmetical values on the orthogonal first and second coordinate axes without performing complicated arithmetic operations such as polar coordinate conversion. Above, we can constrain it to a regular octagon close to a circle.

[Brief description of drawings]

FIG. 1 is a block diagram showing a limiter calculation device according to an embodiment of the present invention, which realizes a limiter method of the present invention.

FIG. 2 is a diagram showing a range, a regular octagon, which is limited by the limiter computing device of FIG.

FIG. 3 is a diagram for explaining the limiter method of the present invention.
FIG. 4 is a diagram in which the first quadrant of is divided into four regions.

FIG. 4 is a diagram for explaining a signal limiter method in a region II of FIG.

5 is a diagram for explaining a limiter method for signals in the area III in FIG. 3;

FIG. 6 is a diagram for explaining a limiter method for signals in the area IV of FIG.

FIG. 7 is a block diagram showing a limiter calculation device that realizes a conventional limiter method on three-phase coordinates.

8 is a diagram showing a regular hexagon, which is a range limited by the limiter computing device of FIG. 7.

FIG. 9 is a block diagram showing a limiter calculation device that realizes a conventional limiter method on orthogonal two-axis coordinates.

FIG. 10 is a diagram showing a range, a square, and a circle that are limited by the limiter computing device of FIGS. 9 and 11.

FIG. 11 is a block diagram showing a limiter calculation device that realizes a conventional limiter method on polar coordinates.

[Explanation of symbols]

 10 ... 3-phase / 2-phase converter 11d, 11q ... Subtractor 12d, 12q ... PI control calculator 13d, 13q ... Limiter circuit 15 ... 2-phase / 3-phase converter 20 ... Variable gain multiplication circuit

Claims (4)

[Claims] 1. A limiter method for limiting a signal having two components on two orthogonal coordinate axes within a predetermined range on a coordinate plane defined by the two coordinate axes, wherein the predetermined range is equal to 2 A limiter method characterized by a regular octagon that crosses each of the two coordinate axes vertically. 2. The first on the first and second coordinate axes orthogonal to each other
And the first and second control-calculated signals representing the second control-calculated value are limited to a predetermined range in which the absolute value of the value of each signal does not exceed a predetermined limit value, and respectively. In a limiter computing device that outputs first and second limited signals representing first and second limited values, a sum of absolute values of the first and second control-calculated signals is obtained, and the sum is calculated. When the value of is less than or equal to √2 times the limit value, the signals obtained by the first and second control operations are left as they are, and when the value of the sum is equal to or more than √2 times the limit value. A variable gain multiplication circuit that divides a signal obtained by multiplying the first and second control-calculated signals by √2 times by the sum value, and outputs first and second converted signals; The absolute value of the first converted signal is equal to the predetermined limit value. And a first limiter circuit that outputs the first limited signal, and a second converted signal that has an absolute value that does not exceed the predetermined limit value. And a second limiter circuit for outputting the second limited signal, and the first and second control-calculated signals on the first and second coordinate axes. Limiter calculation device that can be restricted to within a regular octagon. 3. The variable gain multiplication circuit receives the first control-calculated signal, obtains a first absolute value of the first control-calculated value, and expresses the first absolute value as a first absolute value. A first absolute value circuit that outputs an absolute value signal of the second control signal, and a second absolute value of the second control calculation value that is obtained by receiving the second control calculation signal and obtains the second absolute value. A second absolute value circuit for outputting a second absolute value signal, and a sum of the first absolute value and the second absolute value for receiving the first and second absolute value signals An adder that outputs a sum signal that represents the sum value; and a sum value that is the limit value √2
If the sum is less than fold, the sum value is converted into a value that is √2 times the limit value. If the sum value is √2 times the limit value or more, the sum value is used as it is and converted. A conversion circuit that outputs a converted signal that represents a value; a divider that receives the converted signal, divides √2 by the converted value, and outputs a divided signal that represents the division value; Of the control-calculated signal and the divided signal, the first control-calculated value is multiplied by the divided value, and the first multiplied signal representing the multiplication result is converted into the first multiplied signal.
A first multiplier for outputting as a converted signal, the second control-calculated signal and the divided signal, multiplying the second control-calculated value by the divided value, The second multiplied signal representing the multiplication result is converted into the second signal.
The second multiplier for outputting as the converted signal of, and the limiter arithmetic unit according to claim 2. 4. A positive octave that vertically crosses an input signal having d and q components on orthogonal d and q coordinate axes on the d axis and the q axis at values 1 and −1 on the coordinate axes. A limiter method for limiting the d component and the q component to a rectangular shape, wherein the d component and the q component are respectively formed in a regular quadrangle connecting four points of √2 and −√2 on the d axis and the q axis, respectively. Limiting the first limited d component and the first limited q component to the first limited q component, and the first limited d component and the first limited q component each having an absolute value of 1 Limiting to a second constrained d component and a second constrained q component, which is within the limiter method.