JPH05326912A - Image sensor - Google Patents

Abstract

PURPOSE:To provide the constitution of an image sensing element, which can reduce the residual charge when resetting is performed, in an image sensor, which is formed by using a plurality of photodiodes in order to take out a signal that has undergone photoelectric conversion. CONSTITUTION:A first photodiode 1 and a diode 3 are connected in series in the same direction. A voltage in the forward direction or in the reverse direction is applied on the photodiode and the diode. At this time, a connecting point CP of two diodes is switched to the low impedance side and the high impedance side relatively. A second photodiode 2, which is connected to the connecting point CP is made to be the reset state or the storing state. Thus, the impedance at the connecting point can be always suppressed to the low value absolutely without the effect of the amount of light, which is cast on the second photodiode 2. The second photodiode 2 is saturated within the reset time, and the generation of residual charge is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor used for reading an image in a facsimile or an image scanner, and more particularly to a device for extracting a photoelectrically converted signal by using a plurality of diodes.

[0002]

2. Description of the Related Art An image sensor used for reading an image in a facsimile or the like uses, for example, an image pickup element line having substantially the same length as a document width, and reads an image signal of one line on the document surface by electrical scanning in the line direction. At the same time, the document is moved by the document feeder (in the sub-scanning direction), and the electrical scanning is sequentially performed to read the entire surface of the document. In this type of image sensor, for example, as shown in FIG. 19, an imaging device 100 is formed in which a photodiode PD and a blocking diode BD are connected in series so that their polarities are opposite to each other. It has been proposed that a plurality of lines are arranged in a one-dimensional array. The image sensor array is formed by a thin film process using an amorphous semiconductor such as amorphous silicon or a polycrystalline semiconductor as a semiconductor layer.

One image pickup device 10 of the above image sensor
The reading of the image signal at 0 will be described with reference to the timing chart of FIG. That is, the photodiode PD already charged at the point b is irradiated with the reflected light from the document surface (not shown), and the photocurrent proportional to the irradiation light amount of the light flows into the anode side of the photodiode PD to The potential Vcp at the midpoint between the diode PD and the blocking diode BD is discharged toward the ground, and charges are accumulated in the node CP (bc period, accumulation period).

Subsequently, a voltage Vh due to a driving pulse Vpulse is applied to the anode side of the blocking diode BD, the blocking diode BD is turned on, the potential Vcp at the connection point at the midpoint between the diodes becomes substantially the voltage Vh, and at the same time, the photodiode PD becomes The battery is charged with the voltage Vh and reset (signal reading and reset period). Next, drive pulse V
When the pulse voltage becomes Vlow, the photodiode PD
The diode BD is turned off, and when the photodiode PD is irradiated with light in this state, the accumulation period is repeated.

Therefore, the electric charge accumulated in the node CP during the accumulating period is discharged during the signal reading period and flows to the outside. In other words, the same amount of charges as the positive charges of the cathode electrode of the photodiode PD, which flowed out as a photocurrent during the accumulation period, are replenished from the outside by the signal reading operation, and the charging current Iout flows. By integrating the charging current Iout with the reading circuit (integrator) 5, the exposure amount of the incident light can be detected and an image signal output can be obtained. The above operation is performed for each image pickup element arranged in a line, and the image signal of one line on the original can be obtained in time series.

[0006]

However, when an image signal is read by the image pickup device having the above structure, there is a problem that the afterimage of the original image in the paper feeding direction deteriorates the resolution. That is, when the photodiode having amorphous silicon as a semiconductor layer is irradiated with light of high illuminance during the accumulation period and the charging current during the signal reading period is large, as shown in FIG.
The differential resistance ΔV / ΔI of D (gradient at point A in the figure) is small, and the time constant constituted by this resistance and the capacitance Cp is sufficiently small.

However, when the illuminating light has a low illuminance, the electric charge stored in the node CP is small and the charging current during the signal reading period (at the time of resetting) is also small. Therefore, as shown in FIG. Differential resistance of ΔV / ΔI
(Inclination at point B in the figure) becomes large. As a result, the time constant also increases and the time required for the connection point potential Vcp to saturate becomes longer. Therefore, the reset operation may become insufficient within the preset signal reading period. In other words, since the time constant changes depending on the amount of incident light, there is a disadvantage that residual charges are generated when the irradiation light has low illuminance, and an afterimage is generated when the next line of the original is read, which deteriorates the resolution.

Further, since the charges generated in the photodiode PD are accumulated in the capacitances of both the photodiode PD and the blocking diode BD, a current flows from the photodiode PD to the blocking diode BD through the signal reading circuit, which causes noise. Become.

The present invention has been made in view of the above circumstances, and in order to take out a photoelectrically converted signal, in an image sensor including a combination of a photodiode PD and a blocking diode BD, a residual charge is reduced when resetting is performed. It is an object of the present invention to provide an image sensor having a structure in which a current does not flow from the photodiode PD to the blocking diode BD.

[0010]

In order to solve the problems of the conventional example, an image sensor according to claim 1 comprises a rectifying element group comprising a first photodiode and a diode connected in series in the same direction, A second photodiode connected to a connection point between the diodes and having the same polarity side as the connection point side with respect to the first photodiode, and an anti-connection point side of the second photodiode. In order to switch the reading circuit, the capacitance portion connected in parallel to the second photodiode, and the connection point between two states of a relatively low impedance state and a high impedance state, the rectifying element group is provided. Power supply means for applying a forward or reverse voltage. And the first
And the capacitance ratio between the photodiode and the diode,
The capacitance ratio between the photodiode and the capacitance section is substantially equal.

An image sensor according to a second aspect is the image sensor according to the first aspect, wherein the second photodiode is formed by sandwiching a photoelectric conversion layer between a lower electrode and an upper transparent electrode, and the upper transparent electrode. The above-mentioned capacitance portion is formed by shielding a part of the light.

An image sensor according to a third aspect is the image sensor according to the first aspect, wherein the power source means applies a constant voltage to the diode side to reverse bias the rectifying element group, and a power source means to the first photodiode side. A constant voltage Vb of the DC power supply, a high level voltage Vh of the pulse voltage, and a low level voltage Vl of absolute value | Vl | <| Vb | <
| Vh | is satisfied.

An image sensor according to a fourth aspect is the image sensor according to the first aspect, wherein the photodiode and the diode are formed by sandwiching a photoelectric conversion layer between a lower electrode and an upper electrode. This photoelectric conversion layer is a non-doped a-Si: H layer from the electrode side that blocks electrons during reverse bias,
Inner doping a-Si: H layer, inner doping a-
Outer doping a-S having a smaller specific resistance than the Si: H layer
i: H layer.

An image sensor according to a fifth aspect is the image sensor according to the first aspect, wherein the photodiode and the diode are formed by sandwiching a photoelectric conversion layer between a lower electrode and an upper electrode. This photoelectric conversion layer has a non-doped a-Si: H outside from the electrode side that blocks electrons during reverse bias.
Layer, an inner non-doped a-Si: H layer deposited at a higher substrate temperature than the outer non-doped a-Si: H layer, and a doped a-Si: H layer.

According to another aspect of the image sensor of the present invention, a photoelectric conversion layer is formed on each of the lower electrodes, and an upper electrode is formed on each of the photoelectric conversion layers to form a first photodiode and a second photodiode. In addition to the above structure, a photoelectric conversion layer and an electrode are arranged below the first photodiode and the second photodiode to form a diode.

The image sensor of claim 7 is the image sensor of claim 6, wherein the doped a-S is used.
The i: H film forms the lower electrode.

[0017]

According to the image sensor of the first aspect, the reset and read operations of the second photodiode are performed by applying a constant voltage to the rectifying element group in the forward direction to cause a current to flow. The accumulation operation is performed by applying a constant voltage in the reverse direction to the rectifying element group to reverse bias all the diodes. That is, at the time of resetting the second photodiode, the impedance at the connection point between the first photodiode and the diode is the current flowing due to the voltage applied to the rectifying element group and the light to the first and second photodiodes. The charge current at the time of discharging the electric charge accumulated by the incident is determined. Therefore, if the voltage applied to the rectifying element group is selected so that a current sufficiently larger than the charging current flows,
The impedance of the connection point can be absolutely kept low without being affected by the amount of light applied to the photodiode. When a reverse bias voltage is applied to the rectifying element group during the accumulation operation of the second photodiode, the connection point becomes high impedance, so that the current from the second photodiode can be accumulated. Further, by making the capacitance ratio of the first photodiode and the diode substantially equal to the capacitance ratio of the second photodiode and the capacitance section, the second photodiode flows out to the first photodiode and the diode. Noise due to current can be reduced.

Further, according to the image sensor of the second aspect, the capacitance portion can be formed at the same time in the step of manufacturing the second photodiode.

According to the image sensor of the third aspect, the pulse applying device for generating the pulse voltage and the DC power supply are connected to both ends of the rectifying element group, and the constant voltage Vb of the DC power supply and the high level voltage Vh of the pulse voltage are connected. , When the absolute values of the low-level voltage Vl satisfy | Vl | <| Vb | <| Vh |, a forward voltage or a reverse voltage can be applied to the rectifying element group.

According to the image sensor of claim 4, since the photodiode and the diode have a thin film structure and the photoelectric conversion layer is a doped a-Si: H layer, the forward current is increased and the electrons are blocked during the reverse bias. Since the non-doped a-Si: H layer was formed on the electrode side to be
It is possible to suppress the dark current and maintain a good P / D ratio.

According to the image sensor of claim 5,
Non-doped a-Si in which a photodiode and a diode have a thin film structure and a photoelectric conversion layer is deposited at a high substrate temperature:
Since the H layer is used, the forward current is increased, and the non-doped a-Si: H layer formed at the substrate temperature lower than that of the non-doped a-Si: H layer is formed on the electrode side that blocks electrons during reverse bias. It is possible to suppress the dark current and maintain a good P / D ratio.

According to the image sensor of claim 6, since the diode and the first photodiode and the second photodiode have a two-layer structure, when the area of one pixel is limited, the first sensor is used. Photodiode and second
It is possible to widen the light receiving area of the photodiode.

According to the image sensor of claim 7, since the lower electrode is formed of the doped a-Si: H film, the first photodiode and the second photodiode are formed on the diode.
The manufacturing process can be simplified when the photodiode of (1) is formed with a two-layer structure.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One pixel of an image sensor according to one embodiment of the present invention will be described with reference to the equivalent circuit diagram of FIG. The image pickup device 100 constituting one pixel is formed of a first photodiode 1, a second photodiode 2, a diode 3 and a diode 4 each made of an amorphous or polycrystalline semiconductor. That is, the cathode side of the first photodiode 1 and the anode side of the diode 3 are connected to form a rectifying element group formed by connecting them in series in the same direction. At the connection point CP of the first photodiode 1 and the diode 3, the second photodiode 2
Of the first photodiode 1 and the second photodiode 2 of the same polarity are connected to each other at the connection point CP.

Anti-connection point CP of the second photodiode 2
The side is connected via a signal reading line 6 to an integrator 5 for reading a charging current according to the light incident on the second photodiode 2. In addition, the cathode side of the diode 4 is connected to the connection point CP, and the opposite polarity sides of the diode 3 and the diode 4 are connected to each other at the connection point CP, and the opposite connection point side of the diode 4 is It is connected to the signal reading line 6. Therefore, the diode 4
Are connected in parallel to the second photodiode 2. Further, the capacitance ratio between the first photodiode 1 and the diode 3 and the capacitance ratio between the second photodiode 2 and the diode 4 are made substantially equal.

On the cathode side of the diode 3, a constant voltage V is applied to reverse bias the first photodiode 1, the second photodiode 2, the diode 3 and the diode 4.
A DC power supply 7 for applying b is connected via a bias voltage application line 8. Further, a pulse applying device 9 for applying a pulse voltage to the anode side of the first photodiode 1
Are connected via a pulse voltage applying line 10, a constant voltage Vb of the DC power supply 7 and a high level voltage Vh of the pulse voltage.
, The low level voltage Vl is set to satisfy Vl <Vb <Vh. Therefore, when the high level voltage Vh is applied to the anode side of the first photodiode 1, the connection point CP is in a low impedance state, and when the low level voltage Vl is applied,
The connection point CP is in a high impedance state. Further, the diode 4 is always in the reverse bias state regardless of the application of the pulse voltage, and therefore functions only as the capacitance section.

Next, a specific structure of the image pickup device will be described with reference to FIGS. 2, 3 and 4. The first photodiode 1, the second photodiode 2, the diode 3, and the diode 4 are made of an amorphous or polycrystalline semiconductor with a lower electrode made of chromium and an upper electrode made of ITO (indium tin oxide). It is formed so as to sandwich the photoelectric conversion layer. The photoelectric conversion layer has a pin (ni
It may have any structure of p), in (ni), and pi (ip). That is, chromium is deposited and patterned on the insulating substrate 11, and the first photodiode 1 and the second photodiode 2 are formed.
A lower electrode 12 which is common to the photodiodes 2 and 4 of FIG. 4, a lower electrode of the diode 3 and a chromium pattern 13 which becomes the bias voltage applying line 8 and a chromium pattern 14 which becomes the pulse voltage applying line 10 are formed respectively. ..

Next, amorphous silicon (a-Si)
And ITO are continuously deposited and patterned to have the same shape, and the photoelectric conversion layer 2 of the first photodiode 1 is formed.
1 and upper electrode 31, photoelectric conversion layer 22 and upper electrode 32 of second photodiode 2, photoelectric conversion layer 23 and upper electrode 33 of diode 3, photoelectric conversion layer 2 of diode 4
4 and the upper electrode 34 are formed respectively. Upper electrode 32
The upper electrode 34 and the upper electrode 34 are connected by a neck portion 35.
In each diode, the areas where the lower electrode, the photoelectric conversion layer, and the upper electrode overlap are a, b, c, and d, respectively, so that a / c = b / d is established. Therefore, since each diode is manufactured in the same manufacturing process, the characteristics are uniform, the capacitance ratio at the time of reverse bias is the same as the area ratio, and when the capacitance ratios are Ca, Cb, Cc, and Cd,
Ca / Cc = Cb / Cd.

Next, an insulating film 40 is deposited and patterned on the entire surface, and contact holes 41, 42, 43 and 44 are formed on the upper electrodes 31, 33 and 34, the extended portion 12a of the lower electrode 12 and the chrome pattern 14. , 45 are formed respectively. Subsequently, aluminum is deposited and patterned, and the signal read line 51 (6) covering the upper electrode 34, the wiring 52 covering the contact hole 41 and the contact hole 45, and the contact hole 42.
A wiring 53 is formed to cover the contact hole 43 and the contact hole 43. At this time, since the upper electrode located below the end side of the signal reading line 51 is the neck portion 35, even if a deviation occurs during the pattern formation of aluminum, the area ratio error can be prevented and the processing accuracy can be ensured. it can. The diode 4 has the same structure as the photodiodes 1 and 2, but since the upper electrode 34 is shielded by the signal reading line 51, it serves as a diode that performs only a rectifying function. Similarly, since the upper electrode 33 of the diode 3 is shielded from light by the wiring 53, it serves as a diode that performs only a rectifying function.

With the above configuration, the first photodiode 1 and the second photodiode 2 are connected to each other at their cathode sides by sharing the lower electrode 12. Further, the cathode side of the second photodiode 2 and the diode 3 are formed by extending the extending portion 12a of the lower electrode 12.
The transparent electrode 33 is connected to the transparent electrode 33 by a wiring 53 through a contact hole 42 formed in the insulating film 40. The anode side of the first photodiode 1 is connected to the chrome pattern 14 (pulse voltage application signal line 10) via the wiring 52, the cathode side of the diode 3 (chrome pattern 13) is connected to the bias voltage application line 8, and the second photo diode is formed. The anode sides of the diode 2 and the diode 4 are connected to the signal read line 51 (6), respectively.

Image sensor 100 constructed as described above
As shown in FIG. 5, a plurality of lines are arranged side by side, and the anode side of each first photodiode 1 is connected to the output terminals Q0 to QN of the shift register 60 via the pulse voltage application line 10, respectively. .. Further, the cathode side of each diode 3 has one DC power supply 7 for the image pickup device line.
Are connected to each rectifying element group consisting of the first photodiode 1 and the diode 3 in such a polarity as to be reverse biased. The anode side of each of the second photodiodes 2 and 4 is connected to a common signal reading line 6 which is one for the image pickup device line, and the signal reading line 6 is connected to the input terminal of the integrator 5. ing. The integrator 5 is configured to be reset by a switch 61 that opens and closes according to a control signal.

The shift register 4 sequentially shifts and outputs the pulses from the output terminals Q0 to QN by applying the start pulse. The high level voltage Vh and the low level voltage Vl of the pulse are the constant voltage Vb of the DC power supply 7.
On the other hand, Vl <Vb <Vh is satisfied.

Next, the operation of one pixel forming the image pickup element array will be described with reference to FIGS. FIG. 6 shows the pulse output from the shift register 60 and the waveform of the connection point potential Vcp superimposed on each other. By applying a pulse from the shift register 60 to the anode side of the first photodiode 1, the high potential Vh and the low potential Vl are intermittently applied to the anode side. On the cathode side of the diode 3, a constant voltage Vb having a polarity opposite to that of the pulse voltage and satisfying Vl <Vb <Vh is constantly applied. Therefore, when the anode side of the first photodiode 1 becomes the high potential Vh at the point o in FIG.
The voltage (Vh-Vb) is applied to both ends of the rectifying element group consisting of the photodiode 1 and the diode 3 in the forward direction, the first photodiode 1 and the diode 3 are turned on, and the connection point of the connection point CP is connected. The potential Vcp is determined by the equivalent resistance of the first photodiode 1 and the diode 3 (reset state). For example, when the four capacitors Ca, Cb, Cc, and Cd are all equal, the potential is (Vh-Vb) /
It becomes 2.

Next, when the anode side of the first photodiode 1 has a low potential Vl at point p, the voltage (Vb-Vl) is reversed in the opposite direction across the rectifying element group consisting of the first photodiode 1 and the diode 3. Then, the first photodiode 1, the second photodiode 2, the diode 3 and the diode 4 function as a capacitance portion, and the connection point CP becomes high impedance. When light is applied to the first photodiode 1 and the second photodiode 2 in this state, a photocurrent flows and the potential of the potential Vcp begins to discharge toward the ground, and electric charges are generated according to the area ratio. Then, it is distributed and accumulated in four capacitors Ca, Cb, Cc, and Cd (accumulation state). These capacities are
Since Ca / Cc = Cb / Cd as described above, the charges generated in the second photodiode are Ca and Cc,
The charges generated in the second photodiode are distributed to Cb and Cd, respectively, and the voltages are balanced, so that the current flowing out to the signal reading line 6 is not generated.

Next, at a point q after a certain period of time, the anode side of the first photodiode 1 is again at the high potential Vh.
Then, the first photodiode 1 and the diode 3 are biased in the forward direction and a current flows. At this time, the potential Vcp at the connection point CP is determined by the equivalent resistance of the first photodiode 1 and the diode 3, and the second photodiode 2 and the diode 4 are charged with this potential. At this time, since charging is performed through the integrator 5 connected to one ends of the second photodiode 2 and the diode 4, the integrated signal Vout according to the charging current Iout can be read. The impedance at the connection point CP is defined by the current Id flowing by the voltage applied to the rectifying element group and the charging current Iout flowing outside when the charge accumulated by the light incident on the second photodiode 2 is discharged. ,
If the applied voltages Vh and Vb to the rectifying element group are selected so that a current Id sufficiently larger than the charging current Iout flows, the impedance of the connection point CP is not affected by the amount of light applied to the second photodiode 2. Can be suppressed to a substantially constant value at all times, and the reset operation can be performed in a short time by reducing the time constant during charging.

That is, in the case of the conventional configuration, the time constant becomes large, so that the rising edge of the potential change due to the charging current draws a rising curve as shown by the dotted line in FIG. Therefore, during the pulse width period of the pulse voltage Vpulse, the photodiode PD in FIG. 10 is not completely saturated, and the amount which is insufficient to the saturation level becomes the residual charge, and this residual charge remains as the residual charge amount in the accumulation period after reset. , Which causes afterimage on the next line. According to this embodiment, the time constant can be set small, and the rising curve shown by the solid line in FIG. 7 can be obtained, and the second photodiode 2 can be completely saturated during the pulse width period of the pulse voltage Vpulse. it can. Therefore, by detecting and integrating the charging current Iout, it is possible to know the exposure amount of the light incident on the second photodiode 2 without generating residual charges.

Next, the operation of the image sensor array consisting of n image sensors will be described with reference to FIGS. Since the pulses are sequentially shifted and output from the respective outputs Qn of the shift register 60 as shown in FIG. 8, the above operation is performed in time series, and the common signal read line 6 receives the signal current (shown in FIG. 8). Charging current Iout is output. Spike noise is superimposed on the charging current (signal current) at the rising edge of each pulse of the shift register 60, and spike noise having the opposite polarity to the noise appears at the falling edge. However, by matching the rising and falling times of adjacent pulses, it is possible to cancel the rising and falling noises. Therefore, in the signal current Iout, as shown in FIG. 8, the rising spike noise of the first pulse of the shift register 60 (superimposed on the charging current) and the falling spike noise of the nth pulse (output to the lower side) ) Is output to the signal reading line 6. Therefore, by integrating the signal current Iout, the integrated output Vout shown in FIG. 8 can be obtained.
Reset in FIG. 8 indicates the timing at which the reset switch 61 resets the integrator 5.

FIG. 9 shows another embodiment of one pixel of the image pickup device, in which the directions of the first photodiode 1, the second photodiode 2, the diode 3 and the diode 4 are all reversed. The same components as those in FIG. 1 are designated by the same reference numerals. In this case, the polarities of the DC voltage applied to the diode 2 and the pulse voltage applied to the first photodiode 1 are also opposite, and the high level voltage V
h and the low level voltage Vl are constant voltage V of the DC power supply 7.
For b, each absolute value is | Vl | <| Vb | <| Vh |
Set to satisfy.

10 (a) and 10 (b) are sectional explanatory views of another embodiment of the image sensor according to the present invention. The plan view is the same as that of FIG. 2 in the above embodiment, and in FIG. 10, portions having the same configurations as those of FIGS. 2 to 4 are denoted by the same reference numerals. In this embodiment, the first
The photoelectric conversion layer 21 of the photodiode 1, the photoelectric conversion layer 22 of the second photodiode 2, the photoelectric conversion layer 23 of the diode 3, and the photoelectric conversion layer 24 of the diode 4 as the upper electrode 31 for blocking electrons during reverse bias, 32, 33,
From the 34 side, non-doped a-Si: H layers 21c, 22
c, 23c, 24c, doping a-Si: H doped with phosphorus (P) so that the specific resistance is 1 MΩ · cm or more
Layers 21b, 22b, 23b, 24b, specific resistance of 1 kΩ
The doping a-Si: H layers 21a, 22a, 23a, and 24a doped with phosphorus (P) so as to have a thickness of cm or less are formed.

The photoelectric conversion layer is formed by depositing and patterning chromium on the insulating substrate 11, and the lower electrode 12 common to the first photodiode 1, the second photodiode 2 and the diode 4 and the diode. A lower electrode 3 and a chrome pattern 13 to be the bias voltage applying line 8;
After forming the chromium pattern 14 which becomes the pulse voltage application line 10, it is manufactured by the following procedure.

100% silane (S
0.1 to 1 of phosphine (PH ₃ ) gas in iH ₄ ) gas
% Ohmic contact is made between the chromium pattern 14 and the substrate, the substrate temperature is 180 to 350 ° C., the film thickness is 1000 angstroms or less, and the specific resistance is 1 kΩ · cm or less. 1
The doping a-Si: H film is deposited. Next, PC
Using a gas in which phosphine (PH ₃ ) gas is doped by 0.01% or less in 100% silane (SiH ₄ ) gas by the VD method, the specific resistance becomes 1 MΩ · cm or more at a substrate temperature of 180 to 350 ° C. 2 doping a-Si: H
Deposit the membrane. Then, a non-doped amorphous silicon (a-Si: H) film is deposited. The total thickness of the second doping a-Si: H film and the non-doped a-Si: H film is 0.3 to 2 μm, and the second doping a-
The Si: H film is formed thicker than the non-doped a-Si: H film.

Further, the first doping a-Si: H film,
Second doped a-Si: H film, non-doped a-S
The deposition of the i: H film is performed in successive steps. However, when each step is performed by breaking the vacuum, the first doping a-Si: H film is oxidized with BHF (buffered hydrofluoric acid). After removing the film, the second doping a-Si:
After the H film is deposited and the oxide film on the second doping a-Si: H film is removed, the non-doped a-S film is removed.
i: The H film is deposited.

Next, as in the embodiment of FIGS. 2 to 4,
IT with a film thickness of 800 Å by the sputtering method
After depositing O (indium tin oxide) and patterning ITO by photolithography, the a-Si: H film and the doping a-Si: H film are patterned by dry etching to form the first photodiodes 1 and 2. And the diodes 3 and 4 are formed. C for the dry etching
A gas such as F ₄ or SF ₆ is used.

According to the above embodiment, the specific resistance is 1 MΩ · c.
Since the doping a-Si: H layers 21b, 22b, 23b, and 24b are formed of the second doping a-Si: H film having a thickness of m or more, the mobility / lifetime product of electrons can be increased, and the first A large forward current can be passed through the photodiode and the diode 3 within a short time. That is, for example, as shown in FIG. 11, according to the diode having the structure of the present embodiment, the second doping a-S
i: diode without H film (first doping a-Si with specific resistance of photoelectric conversion layer of 1 kΩ · cm or less:
The forward current at the same applied voltage can be increased as compared with the H film and the non-doped a-Si: H film).

On the other hand, when the doped a-Si: H film is used as the photoelectric conversion layer, for example, when the photoelectric conversion layer is made of the first doped a-Si: H film and the second doped a-Si: H film. As shown in FIG. 12, the reverse current at the time of dark output increases and the dark current characteristic deteriorates. On the other hand, according to the present embodiment, the non-doped a-Si: H layers 21c, 22c, 23c, 2 are provided on the side of the electrodes that block electrons during reverse bias.
Since 4c is formed, the electron mobility can be reduced, the dark current can be suppressed in the first photodiode, the second photodiode, the diode 3 and the diode 4, and the P / D ratio (bright current and dark current Ratio) can be made good. Therefore, since the forward current can be increased while maintaining a good P / D ratio, it is possible to obtain an image sensor that does not cause an afterimage even during high-speed reading.

13 (a) and 13 (b) are sectional explanatory views of another embodiment of the image sensor according to the present invention. The plan view is the same as FIG. 2 in the above-described embodiment, and in FIG. 13, parts having the same configurations as those in FIGS. In this embodiment, the first
The photoelectric conversion layer 21 of the photodiode 1, the photoelectric conversion layer 22 of the second photodiode 2, the photoelectric conversion layer 23 of the diode 3, and the photoelectric conversion layer 24 of the diode 4 as the upper electrode 31 for blocking electrons during reverse bias, 32, 33,
Non-doped a- formed at different deposition temperatures from the 34 side
Si: H layers 21z, 22z, 23z, 24z and non-doped a-Si: H layers 21y, 22y, 23y, 24y.
(Non-doped a-Si: H layers 21z, 22z, 23z,
The deposition temperature of 24z is set to the non-doped a-Si: H layer 21y,
22y, 23y, and 24y), and the lower layer below is doped with phosphorus (P) a-Si:
The H layers 21x, 22x, 23x, 24x are formed.

The photoelectric conversion layer is formed by depositing and patterning chromium on the insulating substrate 11, and the lower electrode 12 common to the first photodiode 1, the second photodiode 2 and the diode 4 and the diode. A lower electrode 3 and a chrome pattern 13 to be the bias voltage applying line 8;
After forming the chromium pattern 14 which becomes the pulse voltage application line 10, it is manufactured by the following procedure.

100% silane (S
iH ₄ ) gas with 1% doping of phosphine (PH ₃ ) gas is used, the substrate temperature is 180 to 350 ° C., and the doping a-S is performed at a film thickness of 1000 angstrom.
i: Deposit H film. Then, the first non-doped aS
The i: H film and the second non-doped a-Si: H film are deposited at different substrate temperatures so that the total film thickness is 0.3 to 2 μm. In the deposited film, the first non-doped a-Si: H
The substrate temperature of the film is 230 to 350 ° C., and the substrate temperature of the second non-doped a-Si: H film is the first non-doped a-
180 to 250 ° C. lower than the substrate temperature of the Si: H film,
The first non-doped a-Si: H film is thicker than the second non-doped a-Si: H film.

The first non-doped a-Si: H film and the second non-doped a-Si: H film are formed by two reaction layers having different temperatures but are formed as a single reaction layer. In some cases, allow sufficient time for the substrate temperature to drop to the set temperature in the reaction layer, or use the first non-doped a-S
After the i: H film was deposited, when the vacuum was once broken to change the temperature, the oxide film on the first non-doped a-Si: H film was removed with BHF (buffered hydrofluoric acid). After that, the second non-doped a-Si: H film is deposited.

Next, similarly to the embodiment of FIGS. 2 to 4,
IT with a film thickness of 800 Å by the sputtering method
After depositing O (indium tin oxide) and patterning ITO by photolithography, the first and second non-doped a-Si: H films and the doped a-Si: H film are patterned by dry etching. 1 photodiodes 1 and 2 and diodes 3 and 4 are formed. A gas such as CF ₄ or SF ₆ is used for the dry etching.

According to the above embodiment, the first non-doped a-Si: H film deposited at a relatively high temperature is used as the non-doped a-.
Since the Si: H layers 21y, 22y, 23y, and 24y are formed, a film having a small localized level can be formed, and a large forward current can flow in the first photodiode and the diode 3 within a short time. .. That is, for example, as shown in FIG. 14, according to the diode having the structure of the present embodiment (two-layer structure in which the non-doped a-Si: H layer is deposited at the substrate temperature of 250 ° C. and 230 ° C.), the non-doped a-Si is used. :
In comparison with a diode (a photoelectric conversion layer made of a doped a-Si: H film and a second non-doped a-Si: H film) formed by a single layer in which an H layer is deposited at a substrate temperature of 230 ° C. The forward current at the same applied voltage can be increased.

On the other hand, when the photoelectric conversion layer is formed only by the non-doped a-Si: H film deposited at the substrate temperature of 250 ° C., the reverse current at dark output increases and the dark current increases as shown in FIG. The characteristics deteriorate. On the other hand, according to this embodiment, 230
Non-doped a-Si: H layers 31z, 32 deposited at ℃
By forming z, 33z, and 34z, the barrier height between the ITO film and the ITO film is increased at the interface between ITO and silicon, so that the dark current is suppressed in the first photodiode, the second photodiode, the diode 3, and the diode 4. P / D ratio (ratio of bright current and dark current)
Can be good. That is, from FIG.
The dark current characteristics can be substantially the same as the case where the photoelectric conversion layer is formed only by the non-doped a-Si: H film deposited at the substrate temperature of 0 ° C. Therefore, since the forward current can be increased while maintaining a good P / D ratio, it is possible to obtain an image sensor that does not cause an afterimage even during high-speed reading.

16 and 17 show another embodiment of the present invention, which is an example applied to a two-dimensional color image sensor. In the image sensor (one pixel) shown in FIG. 2, the signal reading lines 6 and the pulse voltage applying lines 10 are alternately arranged in the horizontal direction, and the bias voltage applying lines 8 are arranged in the vertical direction. If a portion surrounded by is one pixel, a planar structure as shown in FIG. 18 is obtained. In FIG. 18, parts having the same configurations as those in FIG. 2 are designated by the same reference numerals. According to the color image sensor of FIG. 18, since the photodiode and the diode of each pixel are formed on the same plane, the presence of the diode 3 shielded by the wiring 53 in one pixel contributes to the photoelectric conversion. 1 light receiving area A and photodiode 2
The area of the light receiving region B is limited, and the sensitivity is lowered.

In this embodiment, as shown in FIG. 16, the signal reading lines 6 and the pulse voltage applying lines 10 are alternately arranged in the horizontal direction, and the bias voltage applying lines 8 are arranged vertically in the lower layer of the photodiode 2. By arranging, the area of the light receiving regions A and B in one pixel is expanded. That is, the diode 3 is formed by disposing the chromium pattern 13 under the photodiode 2 with the photoelectric conversion layer interposed therebetween, and the photodiode 2 and the diode 3 having the anode and the cathode connected to each other have a laminated structure. 16, parts having the same configuration as in FIG. 2 are given the same reference numerals.

Next, the manufacturing method of this embodiment will be described with reference to FIG. 17A to 17D are sectional views of the image sensor of FIG. Insulating substrate 11
A metal film made of chromium and having a thickness of about 700 angstroms is deposited thereon by a vapor deposition method or a sputtering method, and patterned by a photolithography method to form a chromium pattern 13 to be the lower electrode of the diode 3 and the bias voltage application line 8. .. Next, an amorphous silicon (a-Si) film is deposited by P-CVD method. This amorphous silicon (a-Si) film has a film thickness of 0.5 to 1.5 μm.
m, and the configuration is pin (nip), in (n
Either i) or pi (ip) may be used. Then, a metal film of Cr or the like is deposited to a film thickness of 700 angstrom by the vapor deposition method or the sputtering method, and is patterned by the photolithography method to form the upper electrode 33 of the diode 3. The upper electrode 33 is formed by the first photodiode 1,
The lower electrode 12, which is common to the second photodiode 2 and the diode 4, is also used. Amorphous silicon (a-Si) film is dry-etched to form a photoelectric conversion layer 23 having a size of about one pixel of the diode 3. A gas such as CF ₄ or SF ₆ is used for the dry etching.

Next, an amorphous silicon (a-Si) film is deposited again by the P-CVD method. This amorphous silicon (a-Si) film has a film thickness of 0.5 to 1.5 μm.
m, and the configuration is pin (nip), in (n
Either i) or pi (ip) may be used. Then, a transparent conductive film of indium tin oxide or the like is deposited to a thickness of 800 Å by vapor deposition or sputtering,
The upper electrode 31 of the first photodiode 1, the upper electrode 32 of the second photodiode 2, and the upper electrode 34 of the diode 4 are patterned by the photolithography method (the upper electrode 32 and the upper electrode 34 are integrated). Respectively, and the amorphous silicon (a-Si) film is dry-etched to perform the photoelectric conversion layer 21 of the first photodiode 1 and the photoelectric conversion layer 2 of the second photodiode 2.
2, the photoelectric conversion layer 24 of the diode 4 (the photoelectric conversion layer 22 and the photoelectric conversion layer 24 are integrated) is formed, and the first
The photodiode 1, the second photodiode 2, and the diode 4 are formed so as to be located on the photoelectric conversion layer 23. In each diode, the area of the portion where the lower electrode, the photoelectric conversion layer, and the upper electrode overlap is a,
If b, c, and d are set, a / c = b / d is formed. Therefore, since each diode is manufactured in the same manufacturing process, the characteristics are uniform, the capacitance ratio at the time of reverse bias is the same as the area ratio, and the capacitance ratios are Ca, Cb, Cc, C.
If d, then Ca / Cc = Cb / Cd.

Next, an insulating film 40 is deposited and patterned on the entire surface, and contact holes 41, 41 are formed on the upper electrodes 31, 34.
43 is formed, and then aluminum is deposited and patterned to cover the upper electrode 34 with the signal read line 51.
The pulse voltage application line 14 (10) is formed so as to cover (6) and a part of the upper electrode 31. The diode 4 has the same structure as the photodiodes 1 and 2, but since the upper electrode 34 is shielded by the signal reading line 51, it serves as a diode that performs only a rectifying function. In addition, the upper electrode 33 of the diode 3
Is a diode formed of a metal film so as to shield light from above and only perform a rectifying function. Note that, in FIG. 17, the same reference numerals are given to parts having the same configurations as those in FIGS. 3 and 4.

According to this embodiment, since the photodiode 2 and the diode 3 have a laminated structure, the portion of the diode 3 shown as the wiring 53 in FIG. 18 can also be used as a light receiving region. The area occupied by the light receiving region A of the diode 1 and the light receiving region B of the photodiode 2 can be increased.

In the above embodiment, the upper electrode 33 of the diode 3 (the lower electrode 12 of the photodiode 1 and the photodiode 2) is formed of a metal film, but it is formed of a doped a-Si: H film. Good. In this case, the photoelectric conversion layer 23 of the diode 3, the upper electrode 33 of the diode 3 (the lower electrode 12 of the photodiode 1 and the photodiode 2), the photoelectric conversion layers 21 and 22 of the photodiode 1 and the photodiode 2 in FIG. Since the film can be deposited, the manufacturing process can be simplified.

The doped a-Si: H film is
For example, 100% silane (SiH
₄ ) By using a gas obtained by doping phosphine (PH ₃ ) gas at 1% with a substrate temperature of 180 to 350 ° C. to form a doped a-Si: H layer having a specific resistance of about 100 Ω · cm. can do.

[0061]

According to the image sensor of the first aspect, at the time of resetting the second photodiode, the impedance at the connection point of the rectifying elements is the current flowing due to the voltage applied to the rectifying element group and the second photodiode. The charge current when the charge accumulated by the light incident on the diode is discharged can be obtained. Therefore, if the applied voltage to the rectifying element group is selected so that a current sufficiently larger than the charging current flows, the impedance at the connection point can always be suppressed to a low level without being affected by the amount of light emitted to the second photodiode. Therefore, the photoelectric conversion element is saturated within the reset time to prevent generation of residual charges. As a result, the residual image due to the residual charges disappears, and the resolution of the image sensor can be improved. In addition, by connecting a capacitance section in parallel to the second photodiode and making the capacitance ratio of the first photodiode and the diode substantially equal to the capacitance ratio of the second photodiode and the capacitance section, The noise due to the current flowing from the second photodiode to the first photodiode and the diode can be reduced to improve the resolution of the image sensor.

According to the image sensor of the second aspect, it is possible to simultaneously form the capacitor portion in the step of manufacturing the second photodiode, and it is possible to simplify the manufacturing.

According to the image sensor of the third aspect, the pulse applying device for generating the pulse voltage and the DC power source are connected to both ends of the rectifying element group, and the constant voltage Vb of the DC power source and the high level voltage Vh of the pulse voltage are applied. , When the absolute values of the low-level voltage Vl satisfy | Vl | <| Vb | <| Vh |, a forward voltage or a reverse voltage can be applied to the rectifying element group.

According to the image sensor of claim 4, since the photodiode and the diode have a thin film structure and the photoelectric conversion layer is a doped a-Si: H layer, the forward current is increased and the electrons are blocked during the reverse bias. Since the non-doped a-Si: H layer was formed on the electrode side to be
A dark current can be suppressed to maintain a good P / D ratio, and an image sensor that does not cause an afterimage even during high-speed reading can be provided.

According to the image sensor of claim 5,
Non-doped a-Si in which a photodiode and a diode have a thin film structure and a photoelectric conversion layer is deposited at a high substrate temperature:
Since the H layer is used, the forward current is increased, and the non-doped a-Si: H layer formed at the substrate temperature lower than that of the non-doped a-Si: H layer is formed on the electrode side that blocks electrons during reverse bias. A dark current can be suppressed, a good P / D ratio can be maintained, and an image sensor that does not cause an afterimage even during high-speed reading can be provided.

According to the image sensor of claim 6, since the diode and the first photodiode and the second photodiode have a two-layer structure, when the area of one pixel is limited, Photodiode and second
It is possible to widen the light receiving area of the photodiode of
The sensitivity can be improved.

According to the image sensor of claim 7, since the lower electrode is formed of the doped a-Si: H film, the first photodiode and the second photodiode are formed on the diode.
The manufacturing process can be simplified when the photodiode of (1) is formed with a two-layer structure.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of one pixel in an embodiment of an image sensor according to the present invention.

FIG. 2 is an explanatory plan view of one pixel in one embodiment of the image sensor according to the present invention.

FIG. 3 is a cross-sectional explanatory view taken along line XX ′ of FIG.

4 is a cross-sectional explanatory view taken along the line YY 'of FIG.

FIG. 5 is an equivalent circuit diagram showing an embodiment of the image sensor according to the present invention.

FIG. 6 is a timing chart diagram for explaining the operation of one pixel of the image sensor according to the present invention.

FIG. 7 is a waveform diagram for explaining a comparison with a conventional example when a reading and resetting operation is performed in the image sensor of the present embodiment.

FIG. 8 is a timing chart diagram for explaining a reading operation of the image sensor of FIG.

FIG. 9 is an equivalent circuit diagram of one pixel showing another embodiment of the image sensor according to the present invention.

10A and 10B are cross-sectional explanatory views of one pixel of an image sensor according to another embodiment of the present invention.

11 is a characteristic diagram of the forward current of the photodiode according to the embodiment of FIG.

12 is a characteristic diagram of the reverse current of the photodiode according to the embodiment of FIG.

13A and 13B are cross-sectional explanatory views of one pixel of an image sensor according to another embodiment of the present invention.

FIG. 14 is a characteristic diagram of a forward current of a photodiode according to the example of FIG.

FIG. 15 is a characteristic diagram of the reverse current of the photodiode according to the embodiment of FIG.

FIG. 16 is a plan view showing another embodiment of the present invention when applied to a color image sensor.

17A to 17D are sectional explanatory views of the color image sensor of FIG. 16, FIG. 17A is a sectional explanatory view taken along the line I-I, FIG. 17B is a sectional explanatory view taken along the line II-II, and FIG. c) is III-I
II line sectional explanatory drawing, (d) is IV-IV line sectional explanatory drawing.

18 is an explanatory plan view of a color image sensor in which the image sensor of FIG. 2 is two-dimensionally arranged.

FIG. 19 is an equivalent circuit diagram showing a configuration of one pixel of a conventional image sensor.

FIG. 20 is a timing chart diagram for explaining a reading operation of the image sensor of FIG.

FIG. 21 is a graph showing voltage-current characteristics of an amorphous silicon diode.

[Explanation of symbols]

1, 2 ... Photodiode, 3, 4 ... Diode,
Reference numeral 5 ... Integrator, 6,51 ... Signal reading line, 7 ... DC power supply, 8 ... Bias voltage applying line, 9 ... Pulse applying device, 10 ... Pulse voltage applying line, 13 ... Chrome pattern, 21, 22, 23, 24 ... Photoelectric conversion layer, 21
a, 22a, 23a, 24a ... Doping a-Si: H
Layers (specific resistance is 1 kΩ · cm or less), 21b, 22b,
23b, 24b ... Doping a-Si: H layer (specific resistance is 1 MΩ · cm or more), 21c, 22c, 23c, 24
c ... Non-doped a-Si: H layer, 21x, 22x, 2
3x, 24x ... Doping a-Si: H layer, 21y,
22y, 23y, 24y ... Non-doped a-Si: H layer (high temperature deposition film), 21z, 22z, 23z, 24z ... Non-doped a-Si: H layer (low temperature deposition film), 31, 32,
33, 34 ... Upper electrode, 60 ... Shift register, 1
00 ... Image sensor

Claims (7)

[Claims] 1. A rectifying element group formed by connecting a first photodiode and a diode in series in the same direction, and a rectifying element group connected to a connection point between the diodes and having the same polarity side with respect to the first photodiode. A second photodiode on the side of the connection point; a reading circuit connected to the side opposite to the connection point of the second photodiode; and a capacitor section connected in parallel to the second photodiode, Power source means for applying a forward or reverse voltage to the rectifying element group in order to switch the connection point between two states of a relatively low impedance state and a high impedance state. An image sensor characterized in that a capacitance ratio between diodes and a capacitance ratio between the second photodiode and the capacitance portion are substantially equal to each other. 2. The second photodiode is formed by sandwiching a photoelectric conversion layer between a lower electrode and an upper transparent electrode, and the capacitor section is formed by shielding a part of the upper transparent electrode from light. 1. The image sensor according to 1. 3. A DC power source for applying a constant voltage to the diode side to reverse bias the rectifying element group,
And a constant voltage Vb of the DC power source, a high level voltage Vh of the pulse voltage, and a low level voltage V of the pulse voltage.
The image sensor according to claim 1, wherein each absolute value of l satisfies | Vl | <| Vb | <| Vh |. 4. The image sensor according to claim 1, wherein the photodiode and the diode are formed by sandwiching a photoelectric conversion layer between a lower electrode and an upper electrode, and the photoelectric conversion layer is an electrode side that blocks electrons during reverse bias. To an undoped a-Si: H layer, an inner doping a-Si: H layer, and an outer doping a-Si: H layer having a smaller specific resistance than the inner doping a-Si: H layer. 5. The image sensor according to claim 1, wherein the photodiode and the diode are formed by sandwiching a photoelectric conversion layer between a lower electrode and an upper electrode, and the photoelectric conversion layer is on an electrode side that blocks electrons during reverse bias. From the outer non-doped a-Si: H layer, the outer non-doped a-Si:
Inner non-doped a- deposited at substrate temperature higher than H layer
An image sensor that forms a Si: H layer and a doped a-Si: H layer. 6. A photoelectric conversion layer is formed separately on the lower electrode, and an upper electrode is formed on the photoelectric conversion layer to form a first photodiode and a second photodiode. The image sensor according to claim 1, wherein a photoelectric conversion layer and an electrode are arranged below the first photodiode or the second photodiode to form a diode. 7. The image sensor according to claim 6, wherein the lower electrode is formed of a doped a-Si: H film.