JPH05326360A - Method and apparatus for manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the integration density of the title semiconductor device by increasing the alignment accuracy of the following: a substratum pattern which is formed before an epitaxial process; and a pattern which is formed through a lithographic process after the epitaxial process. CONSTITUTION:In a method of manufacturing of a semiconductor device, an epitaxial layer 2 whose impurity concentration is lower than that of heavily doped regions 3 is formed, by an epitaxial growth operation, on a semiconductor substrate 1 in which the heavily doped regions 3 have been formed in parts on the surface, the epitaxial layer 2 is irradiated with a beam of referene light, and an alignment signal for a next lithographic process is obtained by detecting and processing a beam of diffracted light. In the manufacturing method, infrared rays whose wavelength is 10mum or higher are used as the beam of reference light. In the manufacturing method of the semiconductor device, an infrared-ray generation device 17 whose wavelength is 10mum or higher is used as a light source for the beam of reference light.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device manufactured through a number of steps including an epitaxial growth step and a lithography step, and a manufacturing apparatus for carrying out this method.

[0002]

2. Description of the Related Art Among semiconductor integrated circuits, an integrated circuit having a bipolar transistor as a basic element is generally manufactured through an epitaxial growth process. Also, recently C
In many cases such as -MOS and CCD, an epitaxial layer formed by an epitaxial growth process is used to improve the characteristics. When the manufacturing process includes the epitaxial growth process as described above, it is necessary to detect the position of the underlying pattern of the semiconductor substrate above the epitaxial layer and below the epitaxial layer in order to align the next lithography process.

The position detection of the underlying pattern in the manufacturing process of the bipolar transistor will be described below. The npn transistor, which is the most important basic element in the bipolar integrated circuit, has a plane structure shown in FIG.
The cross-sectional structure as shown respectively in (b), p ^- high concentrations disposed at the interface of the shape the substrate 1 and the n-type epitaxial layer 2 of n ⁺
Buried layer 3, p ⁺ diffused to surround it
A type isolation region 4, a p type base region 5 formed in the n type epitaxial layer 2 separated thereby, an n ^{+ type} emitter region 6 in which a high concentration n type impurity is diffused therein, and this n ^{+ type} Simultaneously with the formation of the emitter region 6, the n ^{+ -type} collector region 7 is formed for collector contact. On the surface of this transistor,
A silicon oxide film 8 is formed and protected on the entire surface except for the contact holes.

When manufacturing this transistor, first,
p ^- previously formed an n ⁺ region serving as the n ⁺ -type buried layer 3 on the form board 1, then forming an n-type epitaxial layer 2 by an epitaxial growth process. Then, a p ^{+ -type} isolation region 4, a p-type base region 5, an n ⁺ -type emitter region 6, and an n ^{+ -type} collector region 7 are sequentially formed through a photolithography process. At this time, each region formed after the n-type epitaxial layer 2 has to be accurately aligned in the horizontal relative position with respect to the n ^{+ -type} buried layer 3 below this region.

Thus, in order to match the position of the pattern formed in the photolithography process after the epitaxial growth with the underlying pattern before the epitaxial growth,
A step of several hundred nanometers is formed on the substrate surface before epitaxial growth, and unevenness that reflects the step is generated on the substrate surface after epitaxial growth, and alignment is performed based on this unevenness when forming the first pattern after epitaxial growth. ..

FIG. 5 is a schematic configuration diagram of a conventional manufacturing apparatus for detecting unevenness after epitaxial growth to obtain an alignment signal in a photolithography process. In the figure, the laser beam emitted from the laser beam generator 11 is slitted by the beam shaping optical system 12 and irradiates the wafer. At that time, the diffracted light due to the step is detected by the detector 13, and the detection signal is guided to the signal processing system 14. The signal processing system 14 includes an AD converter, a memory, a CPU, etc., converts the detection signal into a digital signal and stores the digital signal, and further performs a predetermined process on the stored data, for example, a convex portion (or a concave portion). ) Is detected and added to the alignment control system 15 for the next lithography process.

[0007]

As described above, when epitaxial growth is performed on a stepped pattern, as shown in FIG.
As shown in FIG. 5, the surface pattern after the epitaxial growth is slightly different in position and shape from that of the base substrate, and a pattern sag 9 or a gap 10 appears. If this sagging or misalignment occurs, the center position shifts and the pattern cannot be accurately aligned in the next lithography process, and in an extreme case, the pattern may even disappear. The sagging / deviation of such a pattern can be improved to some extent by optimizing the epitaxial growth conditions, but could not be completely eliminated. In addition, the optimum condition for improving the pattern deformation may not be compatible with the condition for improving other characteristics such as film quality.

Thus, the conventional method of manufacturing a semiconductor device allows for a certain amount of positional deviation between the underlying pattern having steps and the surface pattern after epitaxial growth,
There was a problem in that the design had to have a dimensional allowance, which reduced the degree of integration.

The present invention has been made in order to solve the above-mentioned problems, and improves the alignment accuracy between a base pattern formed before an epitaxial process and a pattern formed through a lithography process after the epitaxial process. It is an object of the present invention to provide a manufacturing method and a manufacturing apparatus of a semiconductor device that can be increased and thereby increase the degree of integration.

[0010]

According to a method of manufacturing a semiconductor device of the present invention, an impurity concentration is lower than that of a high concentration region by epitaxial growth on a semiconductor substrate having a high concentration region of impurity formed on a part of its surface. An epitaxial layer is formed and reference light is emitted from the epitaxial layer,
When the alignment signal for the next lithography process is obtained by detecting and processing the diffracted light, the wavelength of about 10 is used as the reference light.
Infrared rays of μm or more are used.

The semiconductor device manufacturing apparatus according to the present invention emits reference light from above the epitaxial layer, and
When detecting the position of the underlying pattern of the semiconductor substrate under the epitaxial layer by detecting and processing the diffracted light,
An infrared ray generator having a wavelength of about 10 μm or more is used as a reference light source.

[0012]

In the present invention, since the infrared light having a wavelength of about 10 μm or more is irradiated as the reference light from above the epitaxial layer and the diffracted light is detected and processed, the underlayer pattern formed before the epitaxial process is processed. It can be directly detected, and the alignment accuracy with the pattern formed through the lithography process after the epitaxial process can be improved. As a result, the misalignment expected at the time of designing can be reduced and the integration degree can be increased.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing method and manufacturing apparatus according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. Figure 1
FIG. 3 is an explanatory view of a method for manufacturing a semiconductor device according to the present invention and an apparatus for carrying out this method. In the figure, the same reference numerals as those in FIGS. 4 and 5 denote the same elements. Here, an infrared ray generator is used instead of the laser light generator 11.
The point using 17 and the unevenness for alignment are eliminated and n ⁺
4 and FIG. 5 are such that the embedded buried layer is directly detected.
Is different from

This is because when a high-concentration n ^{+ -type} buried layer 3 is formed at the interface between the p ⁻ -type substrate 1 and the n-type epitaxial layer 2, infrared rays are irradiated from above the n-type epitaxial layer 2. Then, this infrared ray is reflected by the n-type epitaxial layer 2
Is transmitted, is reflected by the n ^{+ -type} buried layer 3 and the p ⁻ -type substrate 1, and is transmitted through the n-type epitaxial layer 2 again to be emitted. Therefore, the diffracted light is detected by the detector 13 and a detection signal is output. By processing in the processing system 14, an alignment signal for the next lithography process is obtained. In this case, the n ⁺ -type buried layer 3 and p ^- Comparing shape substrate 1, by utilizing the reflectance of the high n ⁺ -type buried layer 3 of high impurity concentration is n ⁺
The buried layer 3 can be detected directly.

The reason why the n ^{+ -type} buried layer 3 can be directly detected by using infrared rays in this way will be described below. The light absorption coefficient α of silicon changes depending on the wavelength as shown in FIG. That is, light absorption is large in the visible light region and small in the long wavelength region. Therefore, it is considered that even if the layer is thin, it is blocked in the visible light region, but light is transmitted in the infrared region when the layer is thin.

Generally, light is well reflected at the interface where the refractive index changes greatly. The refractive index n of silicon is about 10 μm at the wavelength, as shown in FIG.
The following light has little dependency on the impurity concentration, but the refractive index decreases as the impurity concentration increases in the wavelength range of about 10 to 40 μm. By the way, the impurity concentration of the n ^{+ -type} buried layer 3 is higher than that of the p ^{− -type} substrate 1 of the npn transistor shown in FIG. 4, and the impurity concentration of the n-type epitaxial layer 2 is higher than that of the n ^{+ -type} buried layer 3. And it is getting lower. Therefore, when an infrared ray having a wavelength of about 10 μm or more is irradiated as a reference light from above the n-type epitaxial layer, it is reflected at the interface between the n-type epitaxial layer 2 and the n ^{+ -type} buried layer 3, and the n-type epitaxial layer 2 and the p-type ^- form the substrate 1
Almost no reflection occurs at the interface with.

Accordingly, infrared rays are irradiated from above the n-type epitaxial layer 2, the diffracted light is detected by the detector 13, and the detection signal is processed by the signal processing 14, whereby the position of the n ^{+ -type} buried layer 3 is determined. Can be detected directly.

Although the integrated circuit having the npn transistor as the main element has been described in the above embodiments, the present invention is not limited to this application, and a high-concentration impurity region is formed on a part of the surface. On the semiconductor substrate, an epitaxial layer with a lower impurity concentration than the high-concentration region is formed by epitaxial growth, the reference light is emitted from the epitaxial layer, and the diffracted light is detected and processed to provide the alignment signal for the next lithography process. Can be applied to almost all semiconductor devices.

[0019]

As is apparent from the above description, according to the present invention, infrared light having a wavelength of about 10 μm or more is irradiated as reference light from the epitaxial layer, and the diffracted light is detected and processed. Therefore, the underlying pattern formed before the epitaxial process can be directly detected, and the alignment accuracy with the pattern formed through the lithography process after the epitaxial process can be improved. Since it becomes smaller, the degree of integration can be increased. Further, according to the present invention, since there is no influence of pattern deviation / difference due to epitaxial growth, the degree of freedom in epitaxial growth conditions is increased, and as a result, other characteristics such as film quality can be improved. Furthermore, according to the present invention, it is not necessary to form an uneven alignment mark on the underlying pattern, and the manufacturing process is simplified.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an apparatus for carrying out the present invention.

FIG. 2 is a diagram showing the relationship between the light absorption coefficient of Si and the wavelength for explaining the operation of the present invention.

FIG. 3 is a diagram showing the relationship between the refractive index of Si and the wavelength for explaining the operation of the present invention.

FIG. 4 is a plan view and a cross-sectional view showing a configuration of a general integrated circuit to which the present invention is applied.

FIG. 5 is a schematic configuration diagram of a conventional semiconductor device manufacturing apparatus.

FIG. 6 is a cross-sectional view of an integrated circuit for explaining a conventional method for manufacturing a semiconductor device.

[Reference Numerals] 1 p ^- forms a substrate 2 n-type epitaxial layer 3 n ⁺ form buried layer 4 p ⁺ form isolation region 5 p-type base region 6 n ⁺ -type emitter region 7 n ⁺ form collector region 12 the beam shaping optics 13 Detector 14 Signal processing system 15 Positioning control system 17 Infrared ray generator

Claims (2)

[Claims] 1. An epitaxial layer having an impurity concentration lower than that of the high-concentration region is formed by epitaxial growth on a semiconductor substrate having a high-concentration impurity region formed on a part of its surface, and a reference light is emitted from the epitaxial layer. In a method of manufacturing a semiconductor device which emits and detects and processes diffracted light to obtain an alignment signal in the next lithography process, an infrared ray having a wavelength of about 10 μm or more is used as the reference light. Method of manufacturing semiconductor device. 2. A semiconductor device manufacturing apparatus for detecting the position of a base pattern of a semiconductor substrate under the epitaxial layer by emitting reference light from the epitaxial layer and detecting and processing diffracted light. An apparatus for manufacturing a semiconductor device, wherein an infrared ray generator having a wavelength of about 10 μm or more is used as a light source of light.