JPH05325554A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the access time at the time of reading operation by reducing the floating capacity of a data line. CONSTITUTION:A function which is selected when a write enable signal WEb is at an inactive level and precharges 1st and 2nd data lines DL1 and DL2 to a specific level is added to a writing circuit 1. Further, this memory is provided with a delay element D1 which delays the timing of disconnection of the writing circuit 1 from the 1st and 2nd data lines DL1 and DL2 after writing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having a structure in which a write data line is precharged to a predetermined level.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory of this type has a plurality of memory cells M having first and second data input / output terminals arranged in a row direction and a column direction as shown in FIG.
C, a plurality of word lines WL that bring the plurality of memory cells MC into a selected state in a row unit at the selection level, and a memory cell in a selected state of a corresponding column provided for each column of the plurality of memory cells MC. A plurality of pairs of first and second data lines DL1 for supplying data to the first and second data input / output terminals and transmitting data from the first and second data input / output terminals of the memory cell. , DL2, a word selection decoder 6 that sets one of a plurality of word lines WL to a selection level according to a row address signal ADr, and a column when a write enable signal WEb is at an active level (low level). A column selection decoder 7c for writing and a column selection circuit 2 for selecting one pair of the first and second data lines forming a plurality of pairs according to the address signal ADc.
a and write data D including inverters IV3 to IV5
A write circuit 1a for setting one of the first and second data lines DL1 and DL2 selected according to Tw to a high level and the other to a low level, and a write enable signal WEb from an active level to an inactive level (high level). ), A precharge control circuit 9 for generating a low-level, one-shot precharge pulse P, and a pair of first and second data lines DL1 and DL1 according to the precharge pulse P. A precharge circuit 8 for precharging and balancing DL2 to a high level (power supply potential level) and first and second data lines DL1 and DL2 forming a pair, which include transistors Q5 and Q6, are pulled up to a high potential. Pull-up circuit 4 and a plurality of pairs of data lines DL according to the column address signal ADc.
, A column selection decoder for reading 7b and a column selection circuit 2b for selecting one of the first and second data lines DL1 and DL2, and a sense amplifier for amplifying data between the first and second data lines DL1 and DL2 forming the selected pair. 5 and 5.

Next, the operation of this semiconductor memory will be described. FIG. 6 is a waveform diagram of signals at various parts for explaining the operation of the semiconductor memory.

At the time of reading, one row of the memory cell MC is selected by the word selection decoder 6 which receives the row address signal ADr. The potentials of the data lines DL1 and DL2 are determined by the potentials held by the inverters IV1 and IV2 of the memory cell MC. The potentials of the data lines DL1 and DL2 are transmitted to the sense amplifier 5 through the transistors Q7 and Q8 which are turned on by the column selection decoder 7b, amplified by the sense amplifier 5 and output as read data DTr. At this time, the write enable signal W
Since Eb is at a high level, the column select decoder 7 for writing is used.
The transistors Q3 and Q4 are turned off by c, and the output of the write circuit 1a is the data lines DL1 and DL2.
Has been separated from.

At the time of writing, the column selection decoder 7c turns on the selected transistors Q3 and Q4 by the write enable signal WEb and the column address signal ADc. Depending on the stored content of the selected memory cell MC, the inverter IV1
Current flows through the path of (IV2), transistor Q1 (Q2), transistor Q3 (Q4), and inverter IV4 (IV5). The on resistance of the transistor of the inverter IV4 (IV5) is made smaller than the on resistance of the transistor of the inverter IV1 (IV2), and the inverter IV1 (IV
By lowering the potential at the output end of 2) below the inversion level of the inverter IV2 (IV1), the output levels of the inverters IV1 and IV2 of the memory cell MC are inverted and data is written.

At the end of writing, one of the potentials of the data lines DL1 and DL2 has dropped to the ground potential level, and the address signal changes in this state to select the selected memory cell M.
When C changes, inverters IV1 and IV2 are temporarily
The output of one of them may drop and the data may be inverted or destroyed. In order to prevent this, the precharge control circuit 9 outputs a pulse for a certain period after writing, and the pulses (P) turn on the transistors Q9 to Q11 to set the data lines DL1 and DL2 to a high level. Charge and balance. The period of the active level (low level) of the pulse (P) is until the potential of the data lines DL1 and DL2 is precharged to a potential equal to or higher than the inversion level of the inverters IV1 and IV2 of the memory cell MC,
It depends on the current drive capability gm of the transistors Q9 to Q11.

[0007]

In this conventional semiconductor memory, the potential of the data line after writing drops below the data inversion level of the memory cell MC, and when the memory cells selected from this state are overlapped, the potential is temporarily increased. Since the potential of the data held in the memory cell may be lower than the inversion level and the data may be inverted or destroyed, the data lines DL1 and DL2 are written by the precharge control circuit 9 and the precharge circuit 8 after writing. The memory cell MCN was precharged to a level higher than the data inversion level. Also, the data line D
Since the precharge time of L1 and DL2 depends on the current drivability gm of the transistors Q9 to Q11 of the precharge circuit, if the current drivability gm of these transistors is increased for high speed access, the data line DL1,
There is a problem that the floating capacitance of DL2 increases and the access time at the time of reading data is rather delayed.

An object of the present invention is to provide a semiconductor memory capable of shortening the access time when reading data.

[0009]

A semiconductor memory of the present invention has a plurality of memory cells arranged in rows and columns having first and second data input / output terminals, and the plurality of memory cells are arranged in units of rows. A plurality of word lines in the selected state and a supply of data to the first and second data input / output terminals of the memory cells in the selected state of the corresponding column provided for each column of the plurality of memory cells, A memory cell array having a plurality of pairs of first and second data lines for transmitting data from the first and second data input / output terminals of the memory cell, and a delay for delaying a write enable signal for a predetermined time. An element and a column selection circuit for selecting a predetermined one of the plurality of pairs of first and second data lines according to a column address signal when a delayed write enable signal output from the delay element is at an active level. While the first of the first and second data lines, wherein the write enable signal forms the pair selected in accordance with the write data when the active level
And a writing circuit for setting the other level to the second level and setting both the first and second data lines to the first level when the level is an inactive level.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory shown in FIG. 5 in that the write circuit 1 receives the inverter IV3 for inverting the level of the write data DTw, the write data DTw and the write enable signal WEb. First to do
NOR gate G1, a second NOR gate G2 to which the output data of the inverter IV3 and the write enable signal WEb are input, and the NOR gate G1 via the transistor Q3.
Of the inverter I for supplying the output data of the above to the data line DL1
V4 and an inverter IV that supplies the output data of the NOR gate G2 to the data line DL2 via the transistor Q4.
5 and one of the pair of data lines DL1 and DL2 selected according to the write data DTw is set to a high level and the other is set to a low level when the write enable signal WEb is at an active level (low level), and an inactive level ( At the time of high level), the data lines forming these pairs are both set to a high level, a delay element D1 for delaying the write enable signal WEb for a predetermined time is provided, and the write column selection decoder 7a is provided with this delay element D1. Column address signal A when the delayed write enable signal output from is at active level
This is a circuit that selects one pair of the plurality of pairs of data lines DL1 and DL2 according to Dc, and does not require the conventional precharge control circuit 9 and precharge circuit 8.

Next, the operation of this embodiment will be described.
2 to 4 are waveform diagrams of signals of respective parts for explaining the overall operation of this embodiment, a transistor level circuit diagram and characteristic diagrams for explaining a read operation, and a transistor level for explaining a write operation. 3 is a circuit diagram and a characteristic diagram of FIG.

First, at the time of reading, the transistors Q1 and Q2 of the memory cell MC are turned on by the word line WL. As shown in FIG. 3, the potentials of the data lines DL1 and DL2 are determined by the output potentials of the inverters IV1 and IV2 of the memory cell MC. The potentials of the data lines DL1 and DL2 are designed to be higher than the potential at which the level of the memory cell MC is inverted, so that data is not destroyed when the selected memory cell is switched. The transistors Q7 and Q8 are turned on by the output signal (Scr) of the column selection decoder 7b, the potential difference between the data lines DL1 and DL2 transmitted through these transistors Q7 and Q8 is amplified by the sense amplifier 5, and the read data signal DTr is output. .. At this time, the delayed write enable signal causes the transistors Q3, Q
4 is turned off, and the output of the writing circuit 1 is the data line DL.
1, DL2 is separated.

At the time of writing, the transistors Q3 and Q4 are turned on by the output signal (Scw) of the column selection decoder 7a which receives the delayed write enable signal and the column address signal ADc. On the other hand, the word line WL turns on the transistors Q1 and Q2 of the memory cell MC, and as shown in FIG. 4, the inverter IV2 (IV1) and the transistor Q1 are turned on.
(Q2), transistor Q3 (Q4), inverter IV
The current i flows through the path of 4 (IV5). Inverter IV
The on resistance of the transistor of No. 4 (IV5) is set to the inverter I.
The potential of the output N1 of the inverter IV2 is set to be smaller than the on resistance of the transistor of V2 (IV1), and
By setting the voltage lower than the inversion level of V1, the memory cell M
The outputs of the C inverters IV1 and IV2 are inverted and data is written.

At the end of writing, one of the potentials on the data lines DL1 and DL2 is lower than the inversion level of the inverters IV1 and IV2. When the address signal changes and the selected memory cell MC changes, the next The outputs of the inverters IV1 and IV2 of the memory cell selected as “1” may drop and the data may be inverted or destroyed. To prevent this phenomenon, the write enable signal WEb is simultaneously written at the end of writing.
As a result, the outputs of the inverters IV4 and IV5 of the write circuit 1 become high level, and the potentials of the data lines DL1 and DL2 are pulled up through the transistors Q3 and Q4. Data line DL
After the potentials of DL1 and DL2 become higher than the inversion levels of the inverters IV1 and IV2, the column selection decoder 7a that receives the write enable signal WEb delayed by the delay element D1 turns off the transistors Q3 and Q4, and the write circuit. The output of 1 is disconnected from the data lines DL1 and DL2.

By doing so, the data lines DL1, DL
Data line DL after completion of writing without increasing stray capacitance of 2
Inverter IV of memory cell MC
It is possible to make it higher than the inversion level of 1 and IV2, and the access time at the time of reading can be shortened.

[0018]

As described above, the present invention adds the function of precharging the selected first and second data lines to a predetermined level when the write enable signal is at the inactive level. Further, the precharge control circuit and the precharge circuit of the conventional example can be eliminated by providing the delay element that delays the disconnection timing between the write circuit after writing and the first and second data lines. Therefore, the floating capacitance of the data line can be reduced, and thus the access time at the time of reading can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of signals of respective parts for explaining the overall operation of the embodiment shown in FIG.

3A and 3B are a transistor level circuit diagram and a characteristic diagram for explaining a read operation of the embodiment shown in FIG.

FIG. 4 is a transistor-level circuit diagram and a characteristic diagram for explaining a write operation of the embodiment shown in FIG.

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor memory.

FIG. 6 is a waveform diagram of signals of respective parts for explaining the operation of the semiconductor memory shown in FIG.

[Explanation of symbols]

 1, 1a write circuit 2a, 2b column selection circuit 3 memory cell array 4 pull-up circuit 5 sense amplifier 6 word selection decoder 7a to 7c column selection decoder 8 precharge circuit 9 precharge control circuit D1 delay element DL1, DL2 data line G1, G2 NOR gate IV1 to IV5 inverter Q1 to Q11 transistor WL1 word line

Claims (3)

[Claims] 1. A plurality of memory cells having first and second data input / output terminals and arranged in a row direction and a column direction, a plurality of word lines for selecting the plurality of memory cells in a row unit, and Supplying data to the first and second data input / output terminals of the memory cells provided in each column of the plurality of memory cells and in the selected state of the corresponding column, the first of the memory cells
And a memory cell array having a plurality of pairs of first and second data lines for transmitting data from the second data input / output terminal, a delay element for delaying the write enable signal for a predetermined time, and this delay A column select circuit for selecting a predetermined one of the plurality of pairs of first and second data lines according to a column address signal when the delayed write enable signal output from the element is at an active level; and the write enable signal Is an active level, one of the pair of first and second data lines selected according to write data is set to a first level and the other is set to a second level. Both data lines are first
And a write circuit for setting the level of the semiconductor memory. 2. The semiconductor memory according to claim 1, wherein the first level is a precharge potential of the first and second data lines. 3. A write circuit has an inverter that inverts the level of write data, a first NOR gate that receives the write data and a write enable signal, and supplies an output to a first data line, and an output of the inverter. 2. The semiconductor memory according to claim 1, further comprising a second NOR gate which receives the data and the write enable signal and supplies the output to the second data line.