JPH05325433A - Information reproducing device and its bit error measuring device - Google Patents

Abstract

PURPOSE:To easily detect a bit error by adding the minimum number of circuits, and to easily realize the measurement of a bit error rate at a low cost. CONSTITUTION:A reproducing is A/D-converted, and outputted to a Viterbi decoder 52 and a ternary level detecting circuit 53. The Viterbi decoder 52 and the ternary level detecting circuit 52 are constituted as one circuit for realizing simultaneously these functions, and a comparing circuit 54 compares results of decoding, regards a different one as an error outputs a result of error detection to a counter 55. The counter 55 counts the number of errors based on a command from a control circuit 56, and outputs a result of counting as the number of errors. The number of detected bit errors is roughly equal to the number of errors at the time when a ternary level detection is executed. The result of actual decoding uses that which is subjected to Viterbi decoding, therefore, by having their conversion table, to what extent an error is contained in an output from the Viterbi decoder 52 can easily be estimated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus and a bit error measuring apparatus therefor, and more specifically, information for reproducing predetermined recording data recorded on a magnetic recording medium or an optical recording medium by utilizing a partial response method. The present invention relates to a reproducing device and a bit error measuring device suitable for use in an information reproducing device.

[0002]

2. Description of the Related Art Conventionally, in a general video tape recorder as an information reproducing apparatus of this type, for example, a magnetic reproducing apparatus, a video signal is recorded and reproduced by an analog signal which is frequency-modulated. In this case, it is considered that if the video signal is converted into a digital signal and recorded on the magnetic tape, the image quality deterioration can be effectively recovered regardless of the number of times of dubbing.

However, when recording and reproducing a digital signal on a magnetic tape, the occurrence of a bit error cannot be avoided, and the bit error rate is measured in order to reduce the bit error.

[0004]

By the way, in order to measure the bit error rate of a recording device or the like, it is usually necessary to process an enormous amount of data, and in order to perform it efficiently, it can be processed in real time. Is desirable. For that purpose, it is necessary to prepare a dedicated hardware and compare the reproduced data with expected data at high speed to detect a bit error.

In the conventional information reproducing apparatus, a circuit for generating the above-mentioned expected data is required separately, and a circuit for generating this in synchronization with the reproduced data is also required, so that the circuit scale is inevitable. There was a problem that it would grow. Furthermore, it is necessary to have the correct data that should have been recorded, and the error rate cannot be self-diagnosed by the drive alone of the information reproducing apparatus.

Therefore, the present invention aims to provide an information reproducing apparatus and a bit error measuring apparatus therefor capable of easily detecting a bit error by adding a minimum number of circuits and easily realizing a bit error rate measurement at a low cost. Has a purpose.

[0007]

In order to achieve the above object, the information reproducing apparatus according to claim 1 is an information reproducing apparatus for reproducing predetermined recording data recorded on a recording medium by using a partial response system. An analog-digital conversion circuit that converts a signal level of a reproduction signal reproduced from the recording medium into a digital signal at a predetermined cycle, and decodes the reproduction signal by Viterbi decoding based on output data output from the analog-digital conversion circuit A Viterbi decoding circuit, a level detection decoding circuit that compares the signal level of the reproduction signal with a predetermined reference value for decoding, a decoded data by the Viterbi decoding circuit, and a decoded data by the level detection decoding circuit. And error detecting means for detecting these disagreements.

As a preferred mode, the information reproducing apparatus according to claim 1 has an error correction circuit for performing error correction on the decoded data output from the Viterbi decoding circuit or the level detection decoding circuit, The operation mode of the error correction circuit is switched based on the detection result of the error detection means.

An information reproducing apparatus according to a first or a second aspect of the present invention is characterized in that it has output means for outputting information indicating a failure state of the apparatus itself to the outside based on the detection result of the error detecting means.

A bit error measuring device according to claim 4 is
An analog-digital conversion circuit for converting a signal level of a reproduction signal obtained by reproducing predetermined recording data recorded on a recording medium using a partial response system into a digital signal at a predetermined cycle, and output from the analog-digital conversion circuit A Viterbi decoding circuit for decoding the reproduction signal by Viterbi decoding based on the output data, a level detection decoding circuit for comparing the signal level of the reproduction signal with a predetermined reference value and decoding, and a decoding by the Viterbi decoding circuit. It is characterized by further comprising an error detecting means for comparing the data and the decoded data by the level detection decoding circuit and detecting a mismatch between them.

[0011]

In the present invention, the level detection and Viterbi decoding circuits are maximally shared, and both functions are realized at the same time with almost no increase in circuit scale. Further, the error bit is detected by checking the difference between the decoding results of the two. Therefore, the measurement of the bit error rate can be easily realized at low cost. Further, it is not necessary to have the correct data that should have been recorded, and the error rate can be self-diagnosed by the drive alone of the information reproducing apparatus.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the description of the embodiments, the principle of the present invention will be sequentially described, and a circuit of a device that realizes the principle will be described later to give an easy-to-understand description.

First, the partial response of the modulation code in the magnetic recording apparatus or the optical recording apparatus which is the object of the present invention will be described. A partial response is used for the modulation code in the magnetic recording device or the optical recording device. As the type of the partial response, the one commonly used is shown in the arithmetic circuit 1 shown in FIG. 1A and FIG. 1B. There is a system using the arithmetic circuits 2 and 3. In addition,
PRS (1,1), PRS (1, -1) and PRS (1,0, -1) are the condition judgments of the operation example. Each of these system polynomials is G
Since (D) = 1 + D and G (D) = 1-D ² , the arithmetic circuit 1 is considered to be provided with independent arithmetic circuits 2 and 3 which are so-called two-nested. D is a delay operator.

That is, the arithmetic circuit 1 shown in FIG.
In (Partial response is PRS (1,0, -1)), the calculation is performed between the input data and the sample two before, so
There is no relationship between the odd-numbered sample and the even-numbered sample, and each is an independent partial response.
It can be regarded as a series of PRS (1, -1).

In the arithmetic circuits 2 and 3 shown in FIG. 1B, two series of odd-numbered samples and even-numbered samples with respect to input data are switched by switches 4 and 5 to be divided into two. The calculation is being performed. That is, the decoding of the arithmetic circuits 2 and 3 (PRS (1, -1) for partial response) and the arithmetic circuit 1 (PRS (1,0, -1) for partial response) are essentially the same. The partial response PRS (1,0, -1) will be described as an example.

The partial response PRS (1,0, -1) itself has a property of propagating an error, and if a 1-bit error occurs under a certain condition, a catastrophic error may occur. Therefore, precoding before recording is performed. You need to do it. For this, it suffices to add a device that performs inverse conversion of the partial response. In this case, the configuration of the entire device is
It is shown as in FIG.

In FIG. 2, 11 is a precoder for executing the processing of (1 / 1-D ² ), and the recording data is subjected to the arithmetic processing of (1 / 1-D ² ) by the precoder 11. For example, it is converted into precode data that changes between the values 1 and -1 of the recording data by utilizing the correlation between the recording data, and is output to the recording channel circuit 12. In the recording channel circuit 12, (1-D) arithmetic processing is performed on the output of the precoder 11 in the arithmetic processing circuit 13, and the arithmetic result is added to the adder 14
The noise is added in and output to the arithmetic processing circuit 15 in the subsequent stage. In the arithmetic processing circuit 15, (1 + D) arithmetic processing is performed on the output from the recording channel circuit 12, and the arithmetic result is decoded and output by the decoder 16.

The signal obtained from the recording channel circuit 12 has a signal level of ± 2, as shown in FIG.
2, 0, +2} are taken, and a fixed threshold is used to decode this into binary data.
Value level detection and Viterbi decoding, which is maximum likelihood decoding, can be considered.

The ternary level detection sets a threshold level having a fixed value between 0 and +2 and 0 and -2, and decodes it depending on which area the sample point falls in. The circuit is very simple. However, the detection ability is not so high. On the other hand, maximum likelihood decoding (Viterbi decoding) is a method in which the most probable sequence is estimated as one sequence by using the values of the sample points before and after, and the detection is higher than the ternary level detection. If the same data is decoded, the bit error rate is from 1 digit to 2 digits as shown in the example in FIG.
Digit is improved.

Here, in decoding exactly the same data, there are four possible output results of the two decoders shown in Table 1 below.

[0021]

[Table 1]

In Table 1, ∘ indicates that the recorded data was correctly decoded, and x indicates that an error occurred. As an example, it is assumed that the bit error rate as a result of decoding by ternary detection is P _L and the result of Viterbi decoding is P _V. That is, the probability of occurrence of pattern 3) or 4) in Table 1 above is P _L , and pattern 2) or 4).
The probability of occurrence is P _V.

That is, it is expressed by the relationship of P _L = P ₃ + P ₄ and P _V = P ₂ + P ₄ . Here, as described above, P _V <<
Since P _L can be set, there is a relation of P ₄ ≦ P ₂ + P ₄ = P _V , and P ₄ ≦ P _L. Therefore, P ₄ has a negligible value with respect to P _L and can be regarded as P _L ≈P ₃ . From the relationship of P ₂ + P ₄ << P ₃ + P ₄ ,
Since P2 << P _3, the probability that both the decoding results are different pattern 2) and pattern 3), that can be regarded as an error occurrence probability in ternary level detection.

By utilizing this property, even if the information about what was written before is not correctly obtained, both the ternary level detection and the Viterbi decoder are operated at the same time and the decoding results of both are compared. The error rate can be measured. Further, in an actual device, the output from the Viterbi decoder is adopted as the decoding result. However, depending on the quality of the signal input to the decoder, the error rate at the time of detecting the ternary level and the error rate at the time of the Viterbi decoding are detected. If the error rates are associated in advance, it is possible to estimate the error rate when the Viterbi decoding is performed using the error rate of the ternary level detection measured by the above method.

Next, a circuit example of the Viterbi decoder will be shown.
Viterbi decoding will be explained as a preparation before that. FIG. 5 shows a trellis diagram for one system (that is, the partial response PRS (1, -1)) taken out every other bit from the system using the partial response PRS (1,0, -1). Here, the branch metric is also displayed. In order to find a path that maximizes the sum of these branch metrics, the path metric L _k up to a certain sample time _k is the path metric value L _k −2 up to the previous sample time k-2.
Can be expressed as in the following formulas (1) and (2).

[0026]

[Equation 1]

[0027]

[Equation 2]

In order to output the optimum path while calculating this metric, three squarers, six adders and two comparators are required. Furthermore, a serial shift / parallel load register for storing the path is required. Therefore, instead of faithfully calculating the path metric, the algorithm using the differential metric reported by Wood et al. Is used to simplify the circuit.

Now, consider the Viterbi algorithm when there are only two states. The Viterbi algorithm is to determine data for each state at a certain time k while narrowing down one path having the largest likelihood to reach that state. The above-mentioned decoding circuit (decoder) is for realizing it faithfully.

As an example, when there are only two states, the branches that survive at that time can have only the following three patterns. State <-1> → state <-1> and state <-1> → state <+1
> State <-1> → State <-1> and State <+1> → State <+1
> State <+1> → State <+1> and State <+1> → State <-1
>

Therefore, it is easily understood that the pattern of the state <+1> → the state <−1> and the state <−1> → the state <+1> is impossible. Each of these patterns →
We will write ↑, →→, → ↓. Then, for each branch, which of these patterns survives is determined by calculating the path metric. Now, there are only two states,
The difference between the respective path metrics is expressed by the following mathematical expression (3).

[0032]

[Equation 3]

Focusing on this equation (3), let us consider whether it can be used to determine which pattern survives. From the above equations (1) and (2), the following equation (4)
The relationship is established.

[0034]

[Equation 4]

[0035] In this case, 4y _k -ΔL _k - since ₂ is common, by determining the magnitude by comparing this value with 4 and -4, or reveals selected either branch. By calculating this, it is possible to determine which pattern of the branch described above survives. That is, even if the path metric itself is not calculated, if the differential metric is calculated, the path can be determined in the process. From Equation (3) described above 4y _k -ΔL _k - When thus by case analysis on the three ways by _two values, are expressed by Equation (5).

[0036]

[Equation 5]

Further, if variable conversion is performed with ΔL _k = 4y _p -4β, it can be expressed as the following formula (6).

[0038]

[Equation 6]

Now, let us consider the meanings of β and 4y _p .
β takes a value represented by the following formula (7).

[0040]

[Equation 7]

Β is the immediately preceding state transition candidate (location p)
Represents the transition pattern in. In other words, it represents the type of transition at the point where the transition (→ ↑ or → ↓) other than the first parallel path going back from the current time is considered as a candidate. On the other hand, y _p is the value of y at that time.

For example, when it seems that → ↑ has occurred in the previous branch (that is, the last branch that has not been fixed), β =
+1, and the update rule judgment condition and β and y _p at that time is as shown in FIG. In other words, the meaning of β can be regarded as having a role of adding an offset to the threshold value for the determination in the above equation.

In this way, the probability of the previous state transition candidate (location p) and the certainty of the transition at the current sample point (location k) are compared, and the more probable one is determined as a new state transition candidate. Repeat.
Since the person who loses the judgment is regarded as having no transition, the memory for storing the path needs to be randomly accessible so that the information at the p point or the k point can be updated.

When a circuit is realized based on such an algorithm, its block diagram is as shown in FIG. Figure 7
In FIG. 7, the reproduction data from the recording channel is divided into odd-numbered column samples and even-numbered column samples for arithmetic processing, and FIG. 7 shows the case of even-numbered column samples in detail as an example. That is, the even column samples from the recording channel are supplied to the subtraction circuit 22 and the register 23 via the switch 21. The register 23 stores the value of the previous state transition candidate y _p , and the subtraction circuit 22 subtracts the value of the register 23 from the even column sample and outputs it to the comparison circuit (comparator) 24.

The comparator circuit 24 has a threshold value of +2,
0 and -2 are given, and arithmetic processing is performed on the output from the subtraction circuit 22 and the output from the register 25 storing β. Here, the operation of the comparison circuit 24 may be performed as shown in Tables 2 and 3 below, and the output data shown in Tables 2 and 3 are output from the comparison circuit 24.

[0046]

[Table 2]

[0047]

[Table 3]

26 operates based on the PLL clock,
k is an address register for storing, 27 is an address register for storing p, 28 is a selection circuit for selecting (selecting) k or p, and 29 is output data from the comparison circuit 24 (RAM data) using the output of the selection circuit 28 as an address. ) For storing RAM) is a counter that counts up based on a reference clock, and the data of the RAM 29 is read by using the output of the counter 30 as an address and sent to the switch 31. The switch 31 returns the odd-column sample and the even-column sample to the original array, and the data output is obtained.

With such a configuration, the squarer is 0
This requires only one, one adder, and two comparators. However, in addition to this, RA for storing the path
It is necessary to prepare M29. An example of operation when a certain signal is input to this circuit will be given below.
The RAM refers to the RAM 29.

Operation Example When an input waveform as shown in FIG. 8 is observed, the operation of the comparator (comparison circuit 24) and the manner of change of each parameter are shown below. However, initial values are y _p = −2 and β = −1. Since k = 0: input k ₀ = 1.6 y _k −y _p > 2, it can be determined that the condition F is satisfied. In other words, the upward divergence (hereinafter, appropriately referred to as divergence) because it is, the β +1, and _{p = 0, y p = y} 0.

Since k = 1: input k ₁ = 0.2 −2 <y _k −y _p ≦ 0, it can be determined that the condition B is satisfied. In other words, it means that the parallel path, β, y _p
Is written as it is, and data 0 is written to address 1.

K = 2: Since input k ₂ = −0.2 −2 <y _k −y _p ≦ 0, it can be determined that Condition B was satisfied. In other words, it means that the parallel path, β, y _p
Is written as it is, and data 0 is written to address 2.

Since k = 3: input k ₃ = 2 y _k −y _p > 2, it can be determined that the condition C is satisfied. In other words, because it is upward diverg-ence, the β +1, and _{p = 3, y p = y} 3. Here, since the previous candidate was lost, data 0 is stored in RAM at address 0.
Write.

K = 4: Since input k ₄ = 0.2 −2 <y _k −y _p ≦ 0, it can be determined that the condition B was satisfied. In other words, it means that the parallel path, β, y _p
Is written as it is, and data 0 is written to address 4.

Since k = 5: input k ₅ = −0.4 y _k −y _p > −2, it can be determined that the condition A was satisfied.
In other words, because it is a downward dive-rgence, the β -1, and _{p = 5, y p = y} 5. Here, since the previous candidate is correct, the data 1 is written in the address 3 of the RAM.

K = 6: Input k ₆ = −0.2 0 ≦ y _k −y _p ≦ + 2, so it can be determined that the condition E was satisfied. In other words, it means that the parallel path, β, y _p
Is written as it is, and data 0 is written to address 6.

K = 7: Since the input k ₇ = −2.0 y _k −y _p ≦ 0, it can be determined that the condition D was satisfied. In other words, because it is down diverg-ence, the β -1, and _{p = 7, y p = y} 7. Here, since the previous candidate has been lost, data 0 is stored in the address 5 of the RAM.
Write.

K = 8: input k ₈ = 0.20 ≦ y _k −y _p ≦ + 2, so it can be determined that the condition E was satisfied. In other words, it means that the parallel path, β, y _p
Is written as it is, and data 0 is written to address 8.

Next, a circuit for ternary level detection will be described. This can easily be realized in the form of a Viterbi decoder subset. That is, since only the sample value at the present time is focused on for decoding, it is not necessary to store the value of the previous state transition candidate y _p or p. Similarly, the value of β is also unnecessary. Therefore, 3
The value level detection circuit is configured as shown in FIG.

In FIG. 9, the reproduction data from the recording channel is divided into odd-numbered column samples and even-numbered column samples for arithmetic processing, and FIG. 9 shows the case of even-numbered column samples in detail as an example. That is, the even column samples from the recording channel are supplied to the comparison circuit 42 via the switch 41. Threshold values +1 and −1 are given to the comparison circuit 42, and even-numbered column samples are compared with these threshold values +1 and −1 to perform arithmetic processing. The comparison result is stored in the RAM 43 as RAM data. To be done.

44 operates based on the PLL clock,
The RAM 43 is an address register that stores k, and the RAM 43 uses the output of the address register 44 as an address.
The output data from 2 (RAM data) is stored. 45
Is a counter that counts up based on the reference clock, and the data of the RAM 43 is read by using the output of the counter 45 as an address and sent to the switch 46. Switch 46 returns the odd column samples and the even column samples to the original array, and the data output is obtained.

Here, a part for dividing into an even-numbered sequence and an odd-numbered sequence, and a part for returning these to one sequence again can be shared with the above Viterbi decoder. Also, an address register 44 for writing the decoded result in the RAM 43.
A function as a ternary level detection circuit can be added to the Viterbi decoder by sharing (the one that stores k) and the control circuit necessary for reading this, without increasing the circuit scale.

The number of errors can be counted by simultaneously implementing the Viterbi decoder and the ternary level detection circuit as described above, comparing the decoding results, and adding a circuit which regards different ones as an error. become able to. This block diagram is shown in FIG.

In FIG. 10, a reproduction signal obtained by reproducing predetermined recording data recorded on, for example, a magnetic recording medium as an analog signal by using the partial response method is given to an A / D conversion circuit 51 which performs analog-digital conversion. ,
The A / D conversion circuit 51 converts an analog reproduction signal into an A / D signal.
Viterbi decoder 5 for converting and digital data input
The 2- and 3-value level detection circuit is output to 53.

Specifically, the A / D conversion circuit 51 has a cycle in which the signal level of the reproduced signal rises and falls,
The signal level of the output signal is converted into a digital value, and the resulting input data is output to the Viterbi decoder 52 and the ternary level detection circuit 53. The Viterbi decoder 52 and the ternary level detection circuit 53 can be configured as one circuit that simultaneously realizes these functions by the method described above.

Comparison circuit (corresponding to error detection means) 54
Is a Viterbi decoder 52 and a ternary level detection circuit 53.
The decoding results are compared, the decoding result is output, and the error detection result in which a different one is regarded as an error is output to the counter 55. The counter 55 counts the number of errors based on a command from the control circuit 56, and outputs the count result as the number of errors.

The number of bit errors detected in this way is almost equal to the number of errors when three-level detection is performed. Since the actual decoding result uses Viterbi decoding, it is possible to easily estimate how much error is included in the output from the Viterbi decoder 52 by having these conversion tables.

That is, not only can it be used as an evaluation device for a recording device, but an error can be measured only by the device on the receiving side, so that the drive itself can perform self-diagnosis. In other words, when a large number of errors occur in the decoding result, the error correction circuit should not make erroneous corrections.
Information such as invalidating the entire predecoded data can be sent to the error correction circuit.

FIG. 11 shows an example of a circuit block for error correction.
Shown in. In FIG. 11, a data input, which is an analog-digital conversion of a reproduction signal, is input to the decoder 61. The decoder 61 has, for example, a function of simultaneously realizing the above-mentioned Viterbi decoder and a ternary level detection circuit,
The input data is decoded by a Viterbi decoder and ternary level detection, and the error correction circuit 6 is used as a decoding result.
Output to 2.

The decoding results of the Viterbi decoder and the ternary level detection are compared by the error detection circuit 63, and different ones are regarded as an error, and the detection result of the error detection circuit 63 is detected by the controller as a retry / abnormality detection signal, for example. To 64. The controller 64 determines the error correction circuit 62 based on the detection result of the error detection circuit 63.
Control the output of, and output a control signal to the host computer, for example.

For example, assuming that the error correction circuit 62 has a specification capable of correcting up to k errors, the number of bit errors detected by this detection method is n, and as a result, Viterbi decoding is performed. When there are m errors in the data, m> k
It is presumed that the correction cannot be made when.

A circuit is provided for detecting that correction is not possible when normal correction is not possible, and erroneous correction is prevented by this circuit. There is a possibility that there is a possibility.

Since the erroneous correction is the most unavoidable thing in the memory device, when m> k in advance, the correction circuit itself is invalidated, and by taking an algorithm of assuming that the correction is impossible and repeating the retry, It is also possible to make the probability of erroneous correction very small. That is, the operation mode of the error correction circuit 62 is switched based on the error detection result. If the recorded information is music information or image information, interpolation processing may be performed when many errors are predicted.

As described above, the error information obtained here is used not only for reproducing the information correctly in the drive, but also for sending to the host computer to monitor the number of errors in the sector from the outside. Will be able to. In other words, if there are a large number of errors in a particular sector due to long-term use, etc., move the information to another sector in advance before the sector becomes completely unreadable, and copy that sector to the bad sector. As 2
You can choose not to use it frequently.

Further, when the number of errors in the entire medium is increasing, it is possible to inform the user that the life of the medium is approaching (information indicating a failure state of the apparatus itself).

The application of the present invention is such that if the partial response method is utilized, not only the magnetic recording medium such as the magnetic tape but also the predetermined recording data recorded on the optical recording medium is reproduced. It can be applied to magnetic or optical reproducing devices. Further, although the above embodiment is an example of reproducing a digital video signal, the present invention is not limited to this,
It can be widely applied when reproducing various digital signals.

[0077]

As described above, according to the present invention,
The level detection and Viterbi decoding circuits can be shared as much as possible, both functions can be realized at the same time without increasing the circuit scale, and the bit error rate can be easily measured at low cost. Further, it is not necessary to have the correct data that should have been recorded, and the error rate can be self-diagnosed by the drive alone of the information reproducing apparatus. That is, the error can be self-detected only by the circuit on the receiving side. As a result, this information can be used for transmitting error information to the next block such as ECC.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a partial response of an embodiment of an information reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing an example of an apparatus for performing inverse conversion of a partial response in the same embodiment.

FIG. 3 is a diagram showing a signal level mode of the information reproducing apparatus in the embodiment.

FIG. 4 is a diagram showing a decoding mode result for information reproduction in the example.

FIG. 5 is a diagram showing a trellis diagram for information reproduction in the example.

FIG. 6 is a diagram illustrating a Viterbi algorithm for reproducing information in the embodiment.

FIG. 7 is a block diagram showing an example of a circuit that implements a Viterbi algorithm for reproducing information in the embodiment.

FIG. 8 is a diagram showing an example of an input waveform for information reproduction in the example.

FIG. 9 is a block diagram showing an example of a circuit for ternary level detection in the same embodiment.

FIG. 10 is a block diagram showing an example of a circuit for information reproduction in the same embodiment.

FIG. 11 is a block diagram showing an example of a circuit that performs error correction in the same embodiment.

[Explanation of symbols]

 1 to 3 arithmetic circuit 11 precoder 12 recording channel circuit 13, 15 arithmetic processing circuit 16, 61 decoder 21, 31, 41, 46 switch 22 subtraction circuit 23, 25 register 24, 42 comparison circuit (comparator) 26, 27, 44 Address register 28 Selection circuit 29, 43 RAM 30, 45, 55 Counter 51 A / D conversion circuit 52 Viterbi decoder 53 Three-level level detection circuit 54 Comparison circuit (error detection means) 56 Control circuit 62 Error correction circuit 63 Error detection circuit 64 controller

Claims (4)

[Claims] 1. An information reproducing apparatus for reproducing predetermined recording data recorded on a recording medium by using a partial response method, wherein a signal level of a reproduction signal reproduced from the recording medium is converted into a digital signal at a predetermined cycle. An analog-digital conversion circuit, a Viterbi decoding circuit that decodes the reproduction signal based on output data output from the analog-digital conversion circuit by Viterbi decoding, and compares the signal level of the reproduction signal with a predetermined reference value. A level detection decoding circuit for decoding, the decoded data by the Viterbi decoding circuit, and the error detection means for comparing the decoded data by the level detection decoding circuit, and detecting these disagreements, characterized in that Playback device. 2. An error correction circuit for performing error correction on the decoded data output from the Viterbi decoding circuit or the level detection decoding circuit, and the error correction circuit based on the detection result of the error detection means. 2. The information reproducing apparatus according to claim 1, wherein the operation mode is switched. 3. The information reproducing apparatus according to claim 1, further comprising output means for outputting information indicating a failure state of the apparatus itself to the outside based on a detection result of the error detecting means. 4. An analog-digital conversion circuit for converting a signal level of a reproduction signal obtained by reproducing predetermined recording data recorded on a recording medium using a partial response system into a digital signal at a predetermined cycle, and the analog. A Viterbi decoding circuit that decodes the reproduction signal by Viterbi decoding based on output data output from a digital conversion circuit, a level detection decoding circuit that decodes by comparing a signal level of the reproduction signal with a predetermined reference value, and A bit error measuring device comprising: an error detecting means for comparing the decoded data by the Viterbi decoding circuit with the decoded data by the level detection decoding circuit to detect a mismatch between them.