JPH05324698A - Vector data processor and data transferring system used therefor - Google Patents

Abstract

PURPOSE:To keep task switching processing high-speed, and to keep the speed of a whole vector data processor fast by transferring only necessary data between a main storage device and a physical vector register group in the vector data processor to operate in a multitask. CONSTITUTION:A page converting means 50 coordinates a virtual logical vector register divided into a page unit and a real physical vector register with each other. A page managing means 60 manages the physical vector register by the page unit, and during the execution of some task, it loads the vector data of a logical page portion to access upon the physical vector register group 20 through a data transferring means 40 as occasion demands. A time supervising means 70 checks the physical vector register at every another prescribed time, and saves the disused vector to the main storage device 10. A page absence processing suppression circuit 80 suppresses the allocation of the logical vector register to the physical vector register to the minimum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector data processing device capable of multitask processing, and more particularly to a data transfer system between a main memory device and a vector register when switching tasks.

[0002]

2. Description of the Related Art Conventionally, vector data processing is performed as follows. A conventional vector data processing device will be described below with reference to FIG.

A conventional vector data processing device has a main storage device 300, an arithmetic and logic operation unit 303, a physical vector register group 301, an instruction control unit 304, and a data transfer means 302.

The physical vector register group 301 holds vector data to be supplied to the arithmetic logic operation unit 303 during task execution and the processing result in the arithmetic logic operation unit 303. The instruction control unit 304 receives an instruction from software (not shown) and issues a vector data save request and a vector data load request. When the data transfer means 302 receives the vector data save request, it writes all the vector data of the physical vector register group 301 to the address designated by the software on the main storage device 300, and when the vector data load request is received, The physical vector register group 3 is read out from the address specified by the software on the main storage device 300 in an amount corresponding to the physical vector register group 301.
Output to 01.

The process at the time of task switching is performed as follows. According to the instruction from the software, the instruction control unit 304 issues a vector data save request to the data transfer means 302. Data transfer means 302
Supplies all vector data of the physical vector register group 301 to the main storage device 300. Data transfer means 3
04 stores all of the vector data in the main storage device 30.
Write to the address specified by the software in 0. Subsequently, the instruction control unit 304 which receives the vector data load instruction from the software transfers the data transfer means 302.
Issue a vector data load request to.

In this way, the conventional vector data processing device saves all the vector data in the physical vector register group in the main memory device at the time of task switching, and then saves the vector data in the main memory device. All the data in the physical vector register group.

[0007]

As described above, the conventional vector data processing device saves all the vector data in the physical vector register group in the main memory at the time of task switching, and then uses the vector data as the main data. All the data saved in the storage device is loaded into the physical vector register group, so if only part of the data in the physical vector register group is updated when switching tasks, or if it is saved in the main storage device. Even if only a part of the vector data stored in the physical vector register is needed, the amount of vector data equivalent to the total vector data stored in the physical vector register group must be saved and loaded. It had the drawback of slowing down. Further, as the task switching increases, an enormous amount of vector data is transferred, so that there is a drawback that the speed of the entire vector data processing device is significantly reduced.

Therefore, an object of the present invention is to maintain the speed of task switching processing at a high speed by transferring only necessary vector data in the transfer of vector data at the time of task switching, and further, the entire vector data processing apparatus. An object of the present invention is to provide a vector data processing device capable of maintaining a high processing speed.

[0009]

[Means for Solving the Problems] The above-mentioned problems are solved.
For processing vector data according to the first aspect of the present invention.
The device is a vector data processor that processes multiple tasks in a time-sharing manner.
Data processing device, which holds the actual vector data
A set of vector registers, each with a physical page number
Objects divided into physical pages of a given size with
Physical vector register group; main memory device;
Transfers data between the toll register group and the main memory
Data transfer means; receiving software instructions
Controls the physical vector register group and is currently executing
A command control unit that holds a task number that identifies the
In the vector data processing device that has each task,
It is a set of individual virtual vector registers.
It has the same size as the physical page with a logical page number.
Logical vector register that is equally divided into logical pages with size
Assuming a group of data, the logical pages required when executing each task
To the corresponding physical page in the physical vector register group
When the logical page is
The vector data on the physical page to which the
By saving to the storage device,
To share the physical vector register group with each logical page.
Corresponding to the physical page that allocates the logical page.
The page number and the physical page number are currently invalid values.
The logical page information consisting of
However, the task number and the logical page are sent from the instruction control unit.
Page number is entered, refer to the logical page information above.
The physical page number to which the logical page is assigned.
Output to the command control section and the page absence display
Page conversion means for outputting a page absence processing request
Corresponding to the physical page, the usage status information of each physical page and
A history of task numbers accessed at the end of the physical page
The physical page information consisting of
In response, the logical page is selected from the physical page information.
Search the physical page to be newly allocated to
Among the physical page information and the logical page information, the corresponding page
Page information is updated and stored in the main storage device.
The vector data of the logical page is newly allocated
Said data transfer means for loading onto a physical page
And a page management unit for controlling.

A vector data processing device according to a second aspect of the present invention is a vector data processing device for processing a plurality of tasks in a time-division manner, and is a set of actual vector registers for holding vector data, each of which is A physical vector register group divided into physical pages of a predetermined size to which a physical page number is assigned; a main storage device; a data transfer means for performing data transfer between the physical vector register group and the main storage device; An instruction control unit that receives a software instruction to control the physical vector register group and holds a task number for identifying a task that is currently being executed; Is a set of vector registers,
Assuming a logical vector register group that is logically divided into logical pages having the same size as the physical page by assigning a logical page number to each of them, and the logical page required when executing each task is stored in the physical vector register group. When the execution of a task is allocated to the corresponding physical page and the vector data on the physical page to which the logical page is allocated is saved in the main memory device, the physical vector register group is shared by the plurality of tasks. The logical page information corresponding to each logical page, the physical page number allocating the logical page, and the page absent display indicating that the physical page number is currently invalid. When the task number and the logical page number are input from the control unit, the logical page information is referred to and the logical page is referred to. Outputs the physical page number to the instruction control unit to allocate a page translation means for outputting a page fault processing request by the page fault display,
Corresponding to each physical page, it has physical page information consisting of usage status information of each physical page and a history of the task number accessed at the end of the physical page, and in response to the page absence request, the physical page A physical page to be newly allocated to the logical page is searched from the information, and the corresponding page information in the physical page information and the logical page information is updated and stored in the main storage device. Stores the page management means for controlling the data transfer means so as to load the vector data of the logical page onto the newly allocated physical page, the timer for outputting the monitoring start request at a prescribed interval, and the history of software instructions. And a buffer for reading out information related to a physical page in use from the physical page information in response to the monitoring start request. Compared to the respective history instruction by the software, for matching the software command is not physical pages, having, and time monitoring means for requesting an update of the physical page information to the page management means.

A vector data processing device according to a third aspect of the present invention is a vector data processing device that processes a plurality of tasks in a time-division manner, and is a set of actual vector registers for holding vector data. A physical vector register group divided into physical pages of a predetermined size to which a physical page number is assigned; a main storage device; a data transfer means for performing data transfer between the physical vector register group and the main storage device; An instruction control unit that receives a software instruction to control the physical vector register group and holds a task number for identifying a task that is currently being executed; Is a set of vector registers,
Assuming a logical vector register group that is logically divided into logical pages having the same size as the physical page by assigning a logical page number to each of them, and the logical page required when executing each task is stored in the physical vector register group. When the execution of a task is allocated to the corresponding physical page and the vector data on the physical page to which the logical page is allocated is saved in the main memory device, the physical vector register group is shared by the plurality of tasks. The logical page information corresponding to each logical page, the physical page number allocating the logical page, and the page absent display indicating that the physical page number is currently invalid. When the task number and the logical page number are input from the control unit, the logical page information is referred to and the logical page is referred to. Outputs the physical page number to the instruction control unit to allocate a page translation means for outputting a page fault processing request by the page fault display,
Corresponding to each physical page, it has physical page information consisting of usage status information of each physical page and a history of the task number accessed at the end of the physical page, and in response to the page absence request, the physical page A physical page to be newly allocated to the logical page is searched from the information, and the corresponding page information in the physical page information and the logical page information is updated and stored in the main storage device. Stores the page management means for controlling the data transfer means so as to load the vector data of the logical page onto the newly allocated physical page, the timer for outputting the monitoring start request at a prescribed interval, and the history of software instructions. And a buffer for reading out information related to a physical page in use from the physical page information in response to the monitoring start request. The history of each instruction by the software is compared, and for a physical page for which there is no matching software instruction, a time monitoring means for requesting the page management means to update the physical page information, and the logic specified by the software. From the physical page information regarding the physical page to which the page is allocated,
The task history is read and compared with the currently executed task number obtained from the instruction control unit, and if the two numbers are equal, a page fault processing stop request is output to the page management means. And a circuit.

Further, the data transfer system according to the present invention is
In a vector data processing device that processes a plurality of tasks in a time-division manner, when the first task is switched to the second task, the execution result of the first task from the vector data held in the physical vector register group Means for saving only the vector data updated by the main memory device, and only the vector data necessary for executing the second task among the vector data saved in the main memory device. And a means for loading the register group.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of a vector data processing apparatus according to an embodiment of the present invention and an information processing system to which a data transfer method used therein is applied.

The vector data processing device shown in the figure is managed by software, and includes an input / output device (not shown), a main memory device 10, and an arithmetic logic unit 11.
, Physical vector register group 20, and instruction control unit 30
It has a data transfer means 40, a page conversion means 50, a page management means 60, a time monitoring means 70, and a page absence processing suppression circuit 80.

The software assumes a logical vector group which is a virtual array of logical vector registers.

The logical vector register group is a set of virtual vector registers for each task. The logical vector register group is divided into units called logical pages each including a plurality of consecutive logical vector registers. A logical page number is assigned to each logical page. The size of the logical page and the size of the physical page described later are equal. However, since this logical page is just a virtual page,
It is always allocated to any physical page in the physical vector register group 20.

The page absent processing means that the page management means 60 described later allocates a certain logical page to a new physical page and resets a physical page absent bit described later.

The main storage device 10 is used as a save area for storing vector data on a specific area when each logical page is not allocated to an appropriate physical page by software. .. In the main storage device 10, the save areas for the previous logical pages are regularly reserved in the order of the task numbers assigned to the tasks input from the instruction control unit 30.

The arithmetic logic operation unit 11 processes the vector data supplied from the physical vector register group 20 and outputs the result to the physical vector register group 20.

Vector data physical vector register group 2
0 is a set of actual vector registers that holds vector data, and is divided into physical pages of a predetermined size, each of which is assigned a physical page number.

The instruction control unit 30 receives a software instruction, controls the physical vector register group 20, and holds a task number for identifying a task currently being executed.
The instruction control unit 30 assigns this task number to the main storage device 10.
And page conversion means 50 and page management means 60. Further, the instruction control unit 30 outputs the logical page number to the page converting means 50.

The data transfer means 40 transfers data between the main memory 10 and the physical vector register group 20.

The page converting means 50 corresponds to each logical page and comprises a logical page number to which this logical page is allocated and a page absent indication indicating that the physical page number is currently invalid. It has page information. In addition, when the task number and the logical page number are input from the instruction control unit 30, the page conversion unit 50 refers to the logical page information and issues a physical page number to which the corresponding logical page is assigned. Output to the control unit 30. Further, the page conversion unit 50 issues the page absence processing request by the page absence display described above to the page management unit 6.
Supply for 0.

The page management means 60 has physical page information including, for each physical page, usage status information of each physical page and a history of the task number of the last accessed physical page. Also, the page management means 60
Responds to the above-described page absence request, and searches the above-mentioned physical page information for a physical page to be newly allocated to the corresponding logical page. Further, the page management means 60
Updates the corresponding page information in the above-mentioned physical page information and the above-mentioned logical page information. Furthermore, the page management unit 60 also loads the vector data of the logical page stored in the main storage device 10 onto the newly allocated physical page described above.
Control 0.

The time monitoring means 70 has a timer 71, which will be described later, which outputs monitoring start requests at prescribed intervals, and a buffer 72, which will be described later, which stores the history of software instructions. From the physical page information,
Information regarding the physical page in use is read and compared with the history of each instruction by the software described above, and for the physical page for which there is no matching software instruction, the page management means 60 is requested to update the physical page information.

The page-absence inhibiting circuit 80 reads the task history from the above-mentioned page information regarding the above-mentioned physical page to which the above-mentioned logical page designated by the above-mentioned software is allocated, and obtains it from the instruction control unit 30 at present. Compared with the running task number, if they are equal,
A page absence processing cancellation request is output to the page management unit 60.

Next, FIGS. 2 to 6 will be described. 2 to 6 are block diagrams showing in more detail the configuration of a vector data processing device according to an embodiment of the present invention and an information processing system to which the data transfer method used therein is applied. The configuration itself is the same as in FIG.
The detailed structure of each means and circuit shown in FIG. Therefore, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

Referring to FIG. 2, the instruction control unit 30 includes an instruction decoder 31, a register 32, a register 33, and
An adder 34 and a register 35 are provided. Upon receiving the page switching instruction at the time of task switching, the instruction decoder 31 issues a reset U1 request described later to the page management unit 62 described later. In addition, the instruction decoder 31
Holds any instructions received from the software. The register 32 stores the task number and the logical vector register number accessed by the corresponding task. Register 3
3 stores a logical page descriptor describing a logical page of a certain task under execution, which is retrieved from a page table 51 described later. The adder 34 inputs the physical page address in the register 33 and adds the physical page number of the physical page address and the relative register number in the logical page obtained from the register 32. The physical number corresponding to the logical number obtained as a result is output to the register 35. The register 35 inputs the physical number obtained by the adder 34. Further, the register 35 supplies the input physical number to the physical vector register group 20 and a history unit 73 described later.

Referring to FIG. 3, page conversion means 50
Includes a page table 51 and a page conversion control circuit 52. The page table 51 is an array of the same number of logical page descriptors as all the logical pages that can be possessed by all the tasks executed in the vector data processing device. The page conversion control circuit 52 fetches a logical page descriptor describing a logical page accessed by the task being executed from the page table 51 and stores it in the register 33. When the page conversion control circuit 52 receives a reset U2 request and a physical page address, which will be described later, the page conversion control circuit 52 receives this as a set request and sets the physical page absent bit of the logical page descriptor having the physical page address.

Referring to FIG. 4, page management means 60
Is a page management table 61, a page management control circuit 62,
Decoder 63, register 64, and address generation circuit 6
5 and. The page management table 61 is an array of physical page descriptors of the same number as all physical pages included in the physical vector register group 20. The page management control circuit 62 resets the status bit U1 of the physical page descriptor described later.
The page management control circuit 62 also searches the page management table 61 for the usage status of the physical page. Upon receiving the page absence request, the page management control circuit 62 stops the search for the physical page descriptor. Then, the page management control circuit 62
Indicates the corresponding physical page address in the register 64 described later.
The page management table 61 is controlled to be stored in. Also,
When allocating a new physical page to a certain logical page, the page management control circuit 62 finds the physical page descriptor from the page management table 61. Then, the page management control circuit 62 stores the corresponding physical page address in the register 64 described later. Further, the page management control circuit 62 which has received the page absence request supplies the content of the register 64 described later to the data transfer means 40. On the other hand, the page management control circuit 62 issues a vector data load request to the data transfer means 40. When the physical page address of the logical page descriptor is input from the page table 51 of the page conversion unit 50, the decoder 63 sets the physical page descriptor describing the corresponding physical page in the page management table 61.
Supply to. The register 64 supplies the physical page address being executed to the page table 51. The address generation circuit 65 calculates the save area address on the main memory of the logical page obtained from the task history 73 described later by the method described later and writes it in the register 64.

Referring to FIG. 5, the time monitoring means 70 is
A timer 71, a buffer 72, a history unit 73, a time monitoring control circuit 74, a register 75, a task comparison circuit 76, a register 77, and a page comparison circuit 78 are provided. The timer 71 subtracts the value from the specified timer value every clock, and when the timer value becomes 0, it sends a signal to the time monitoring control circuit 74, which will be described later, to start the time monitoring. The buffer 72 sequentially and temporarily stores the data sent from the page management table 61. Then, the buffer 72 takes out a physical page address of an arbitrary physical page descriptor and supplies the physical page address to a register 75 described later according to a request of a time monitoring control circuit 74 described later. The history means 73 records the task number being executed and the corresponding logical page number and physical number as a set. Upon receiving the signal from the timer 71, the time monitoring control circuit 74 issues a start request to the page management control circuit 62. Further, the time monitoring control circuit 74 controls the buffer 72 to store the above-mentioned physical page address in the register 7.
Hold at 5. At the same time, the time monitoring control circuit 74
Controls to output the task number corresponding to the above-mentioned physical page address from the buffer 72 to the task comparison circuit described later to 76. Further, the time monitoring control circuit 74
Controls the history means 73. Then, the time monitoring control circuit 74 determines from the latest access history of the software,
Only the physical page address having the same number as the current task history is fetched and saved in the register 77 described later. The register 75 holds the page address of an arbitrary physical page descriptor supplied from the buffer 72. The task comparison circuit 76 compares the task number of the physical page descriptor obtained from the buffer 72 with the running task obtained from the page conversion control circuit. If the above two numbers are not equal, a signal of "task number mismatch" is sent to the time monitoring control circuit 74. The register 77 uses the history means 7
The physical page address obtained from 3 is held. The page comparison circuit 78 compares the contents held in the registers 75 and 77 and supplies the result to the time monitoring control circuit 74.

Referring to FIG. 6, the page fault processing inhibiting circuit 80 includes a register 81 and a comparing circuit 82. The register 81 stores the task history held in the page table 61. The comparison circuit 82 inputs the task number being executed and the task history from the register 81 and compares the two. Then, the comparison circuit 82, when the task number being executed and the task history are equal, page management table 6
2. Send the page fault request to 2.

Each line of the wirings 101 to 136 is a data line, a control line and a signal line for connecting each device provided in each circuit and means.

In this embodiment, the physical vector register group 2
The number l (l = 0, 1,
2, 3, ...) and each vector register is described as “physical number 1”. The physical vector register group 20 is divided into units called physical pages each including a plurality of continuous vector registers. A page number m (m = 0, 1, 2, 3, ...) Is assigned to this physical page. .. And
Each physical page is described as "physical page m". Further, among the vector registers forming the physical page m, the physical number of the first register is specifically called a physical page address.

Similarly, the task number assigned to each task input from the instruction control unit 30 includes the task number i
Sift (i = 0, 1, 2, 3, ...). Further, in the above logical page, the logical page number j (j = 0, 1, 2,
3, ...) is referred to as “logical page j”. Further, as a result, the logical page descriptor having the same number as the logical page j of the task with the task number i will be represented as the logical page descriptor ij.

In this embodiment, U1 and U2 are set as status bits.

When the status bit U1 is "0", it indicates that the physical page m is not allocated with the logical page of the task being executed. When the status bit U1 is "1", it indicates that the logical page of the task being executed is allocated to the physical page m.

When the status bit U2 is "0", it indicates that the vector data on the physical page m is saved in the main memory 10. When the status bit U2 is "1", it indicates that the vector data on the physical page m has not been saved in the main memory 10 yet.

With these status bits U1, U2,
Physical pages are defined in the following four types of states.

Unused state (U1 = 0, U2 = 0) Other task used state (U1 = 0, U2 = 1) Semi-used state (U1 = 1, U2 = 0) Used state (U1 = 1, U2 = 1) ) That is, if the status is, the logical page of the task being executed is not allocated. In this state, the logical page of another task is allocated, and the vector data on the page has not been saved in the main storage device 10 yet.
In this state, the logical page of the task being executed is allocated, but the vector data on the page has been saved in the main storage device 10. In this state, the logical page of the task being executed is allocated, and the vector data on the page is not saved in the main storage device 10.

By the way, the start address of the save area of the logical page j of the task of task number i is SAij, SAij = (start address of save area S00) + i × (size of logical vector register group that one task can have That)
It can be expressed as + jx (size of one logical page).

In this embodiment, a task and task number a
Task A is operating in a time-sharing manner, a task switching routine is started, and a certain task is about to switch to task A.

In this embodiment, it is assumed that the task A is trying to access the logical page p, and the relative register number in the logical page corresponding to this is q.

The operation of the vector data processing device according to the present invention and the data transfer method used therein will be described below with reference to FIGS.

By the way, as described above, since the logical page is a virtual page, it must be allocated to any physical page in the physical vector register group 20. Which physical page is assigned to a certain logical page is managed by software assuming a logical vector register using a page table 51 and a page management table 61 shown in FIG. The page management method of the page table 51 and the page management table 61 will be described below.

As described above, the page table 51 is an array of the same number of logical page descriptors as all the logical pages that can be possessed by all the tasks executed in the vector data processing device. The logical page descriptor ij is the information of the logical page j of the task with the task number i, that is, the logical page j.
Describes the physical page address m of the physical page m to which is allocated and the physical page absent bit. When the physical page absent bit is “1”, the vector data on the physical page m indicated by the physical page address m is the logical page j.
Indicates that it does not necessarily match the one above. Therefore, when the physical page absent bit of the logical page descriptor ij is “1”, the physical page address m of the logical page descriptor ij is invalid.

As described above, the page management table 61 is an array of the same number of physical page descriptors as all the physical pages of the physical vector register group 20. Physical page descriptor m
Describes the physical page m information, that is, the physical page address of the physical page m, the status bits U1 and U2, and the task history m in which the task number of the task that last accessed the physical page is recorded. As described above, the physical page is defined by the state bits U1 and U2, and is defined by the above four types.

Next, the operation when switching tasks will be described.

The task switching routine inputs a page switching instruction to the instruction decoder 31 in the instruction control unit 30 through the control line 101. Upon receiving the page switching request, the instruction decoder 31 issues a reset U1 request to the page management control circuit 62 in the page management means 60 through the control line 102. The page management control circuit 62 that has received the reset U1 request resets the status bit U1 of all physical page descriptors through the control line 103. This completes the task switching process, and the execution of task A is started.

Next, the processing when task A specifies a logical vector register in some instruction will be described.

When the physical page absent bit is "0",
A match between the data on the logical page and the data on the physical page to which the logical page is allocated is guaranteed. Therefore, it is not necessary to perform the page absent process for page allocation.

When the physical page absent bit is "1",
It cannot be guaranteed that the data on the logical page matches the physical data to which the logical page is allocated. Therefore, the page absent process is interrupted.

However, even when the physical page absent bit is "1", the page absent processing inhibiting circuit 8 indicates that the data on the logical page matches the data on the physical page.
0 may be detected. In this case, the page fault processing is suppressed and the physical page fault bit is only reset.

Next, assuming that the task A has accessed the logical page p, but the logical page p has not been allocated to the physical vector register, the operation of the physical page absence processing will be described below.

When the execution of task A starts, task A
An arbitrary software instruction is input to the instruction decoder 31 in the instruction control unit 30 through the control line 101. Then, the task number a and the logical vector register number (p, q) to be accessed are stored in the register 32 in the instruction control unit 30. The data in the register 32 is transferred through the data line 104 to the page conversion control circuit 5 in the page conversion means 50.
Entered in 2. The page conversion control circuit 52 sends a logical page descriptor ap, which is input from the data line 104 and describes the logical page p of the task A, to the control line 105.
It is taken out from the page table 51 in the page conversion means 50 and is sent through the data line 106 to the register 33 in the instruction control unit 30.
To store. It is assumed that the physical page address r having the physical page number r exists in the register 32. The adder 34 in the instruction control unit 30 inputs the physical page address r in the register 33 through the data line 107 and adds it to the relative register number q in the logical page through the data line 108. Then, the adder 34 outputs the physical number pq corresponding to the logical number (p, q) to the register 35 in the instruction control unit 30 through the data line 109.
In this way, the physical vector register pq is obtained from the logical vector register (p, q) designated by the software.

However, at this time, the logical page descriptor ap
The physical page absent bit of is “1”. Therefore, because the physical page address r is invalid, the output of the register 35 is suppressed by the control line 110, and a page fault processing request is issued to the page fault management control circuit 62 in the page management means 60.

The page management control circuit 62 in the page management means 60 which receives the page absence processing request receives the page management table 6 from the page management control circuit 62.
From 1, the control line 103 first searches for a physical page descriptor (U1 = 0, U2 = 0) that describes that the above-mentioned physical page is in an unused state. If the page descriptor is not in the unused state, a physical page descriptor (U1 = 1, U2 = 0) describing a physical page in the semi-used state is searched from the page management table 61 by the control line 103.

On the other hand, the decoder 63 uses the physical page descriptor a.
The physical page address r of p is through the data line 106,
When input from the page table 51 in the page conversion means 50, the physical page descriptor r describing the physical page r is supplied to the page management table 61 via the control line 111. The task history r in the physical page descriptor r in the page management table 61 supplied from the decoder 63 is stored in the register 81 of the page management inhibition circuit 80 through the data line 112. The task number a in the register 32 in the instruction control unit 30 is stored in the register 81 via the data line 104. The comparison circuit 82 uses the register 81 to indicate the task number a being executed through the data line 113 and the data line 1
The task history r is input through 14 and both are compared.

As a result of the comparison in the comparison circuit 82, when the task number a and the task history r are equal, it is confirmed that the data on the logical page p and the physical page r match. Therefore, no page fault processing is required. Therefore, when the task number a and the task history r are equal, the comparison circuit 82
Sends a page absence processing request to the page management table 62 through the signal line 115. The page fault processing inhibiting circuit 62 that has received the page fault processing request cancels the search for the physical page descriptor described above. Then, using the control line 103, the page management table 61 is controlled so that the physical page address r obtained from the page table 51 through the data line 106 is stored in the register 64 through the data line 116. Register 6
The physical page address r in 4 and the value “0” for resetting the physical page absent bit are input to the page table 51 through the data line 117. Page conversion control circuit 5
The logical page descriptor ap indicated by 2 is rewritten. However, in this case, only the physical page absent bit is reset. The updated contents of the logical descriptor ap are stored in the register 33 through the data line 106. However, this time, since the physical page absent bit is "0", the page absent request is not issued and the output of the register 35 is not suppressed. Therefore, the physical vector register number pq in the register 35 is output through the data line 118.

As a result of the comparison in the comparison circuit 82, if the task number a and the task history r are not equal, the data on the physical page r is confirmed to belong to another task. Therefore, the page fault process is continued. When the page management control circuit 62 finds the physical page descriptor r'which describes the physical page r'to which the logical page p is newly allocated using the control line 103, the physical page address r'is registered through the data line 116 in the register 64. Hold on. At the same time, the control line 103 writes the task number a obtained through the data line 104 into the task history r ′ of the physical page descriptor r ′, and sets the status bits U1 and U2. On the other hand, the address generation circuit inputs the task number a being executed and the logical page number p through the data line 104, and the save area S of the logical page p calculated as described above.
Aap is stored in the register 64 through the data line 119. Further, the register 64 contains a value “0” for resetting the physical page absent bit of the page table 51.

The page management control circuit 62 which has received the page-absence processing request receives the register 6 by the control line 120.
The contents in 4 are supplied to the data transfer means 40 through the data line 121. Along with this, the page management control circuit 6
2 issues a vector data load request to the data transfer means 40 through the control line 120. Upon receiving the vector data load request, the data transfer means 40 transfers the vector data in the save area SAap of the main storage device 10 to the data line 122.
Through the data line 123
Through the physical page address r '. At the same time, the value “0” in the register 64 and the physical page address r ′ are written to the logical page descriptor ap indicated by the page conversion control circuit 52 through the data line 117. As a result, the physical page absent bit of the logical page descriptor ap is reset. Then, the physical page address is updated. A new physical number pq 'corresponding to the logical number (p, q) obtained as described above by the updated physical page address r'supplied by the data line 106 is stored in the register 35. However, since the physical page absent bit is reset this time,
The data in register 35 is not suppressed and the data line 118
Through the physical vector register group 20.
Also, no page fault processing request is issued. The data transfer means 40 is controlled to finish transferring the vector data on the logical page p to the physical vector register group 20 by the time the physical number pq 'is set in the register group 35.

The operation after the time monitoring start request accompanying the above operation will be described below.

Upon receiving the signal from the timer 71, the time monitoring control circuit 74 issues a monitoring start request to the page management control circuit 62 via the control line 125. In response to this start request, the page management control circuit 62 causes the control line 103
Is used to search the page management table 61 for the physical page descriptors in the above-described in-use state and semi-in-use state (U2 = 1). Then, the retrieved physical page descriptor is set to the data line 11
It outputs to the buffer 72 of the time starting means through 6. The time monitoring control circuit 74 uses the control line 126 to send the buffer 72.
To retrieve the page address r of an arbitrary physical page descriptor r and to send it to the register 7 through the data line 127.
Store in 5. Then, the time monitoring control circuit 74 sends the task number i to the task comparison circuit 76 via the data line 128.
Output to. Further, the time monitoring control circuit 74 uses the control line 1
The history means 73 is controlled by 29 to fetch only the physical page address r from the latest access history of the software and store it in the register 77 through the data line 136.

Hereinafter, in the above-mentioned operation, the task comparison circuit 76 compares the task number of the physical page descriptor r obtained from the data line 128 with the running task number a obtained from the data line 128, The explanation will be continued assuming that the numbers are not the same.

When the task number of the physical page descriptor r and the task number a in execution are not equal, the task comparison circuit 76 sends the data line 128 to the time monitoring control circuit 74 a "task number mismatch" signal. .. The time monitoring control circuit 74 which has received the signal of "task number mismatch" unconditionally issues a reset request U2 to the page management control circuit 62 and the page conversion control circuit 52 through the control line 125. Then, the time monitoring control circuit 74 notifies the page management control circuit 62 and the page conversion control circuit of the above-mentioned physical page address r stored in the register 75 through the data line 131. At the same time, the time monitoring control circuit 74
Interrupts the address generation circuit 65 through the signal line 132. Then, the time monitoring control circuit 74 inputs the logical page number assigned to the corresponding physical page to the address generation circuit 65 through the data line 133. Page management control circuit 62 that has received the reset U2 request
Uses the control line 103 to reset both state bits U1 and U2 of the physical page descriptor r having the physical page address r obtained from the data line 131. Then, the page management control circuit 62 keeps the physical page address r.
Is written in the register 64 through the data line 116.

Here, following the above-mentioned operation, the page management means 62 outputs a vector data save request to the data conversion means 40. The operation at the time of requesting vector data will be described below.

The page management means 62 supplies a vector data save request to the data transfer means 40 through the control line 120. Then, the content of the register 64 is the data line 12
1 to the data transfer means 40. Upon receiving the vector data save request, the data transfer means 40
The vector data on the physical page r obtained from the data line 121 is read out through the data line 123. Similarly, the data conversion means 40 uses the logical page j obtained from the data line 121.
The vector data read out to the save area SAij is written in the main storage device through the data line 122. Further, since the reset U2 request output from the control line 125 and the physical page address output from the data line 131 are also input to the page conversion control circuit 52, the page conversion control circuit 52 regards this as a set request. receive. Then, the page conversion control circuit 52 sets the physical page absent bit of the logical page descriptor having the physical address.

Meanwhile, the time monitoring control circuit 74 fetches a new physical page descriptor s from the buffer 72 using the control line 126. Then, the physical page address s is written in the register 75 through the data line 127. Further, the time monitoring control circuit 74 inputs the task number a to the task comparison circuit 76 through the data line 128.

Hereinafter, assuming that the above-mentioned physical page descriptor s is written in the register 75, the operation accompanying the comparison of physical page descriptors will be described.

When the task comparison circuit 76 does not send the above-mentioned "task number mismatch" signal to the time monitoring control circuit 74, the processing is continued. The page comparison circuit 78 inputs the value of the register 75 from the data line 131, while inputting the value of the register 77 from the data line 134, and compares the value of the register 75 with the value of the register 77. The comparison result of the page comparison circuit 78 is the signal line 13
5 to the time monitoring control circuit 74.

In the page comparison circuit 78, the register 7
If it is determined that the value of 5 and the value of the register 78 are “equal to each other”, it can be determined that the access to the corresponding physical page was within the monitoring time. A new physical page descriptor from the buffer 72.

In the page comparison circuit 78, the register 7
When it is determined that the value of 5 is not equal to the value of the register 78, the time monitoring control circuit 74 controls the history means 73 using the control line 129. Subsequently, the time monitoring control circuit 74 extracts only the physical page address from the new access history and writes it in the register 77 through the data line 136.

In this method, if the page comparison circuit 78 cannot determine that the values obtained from the register 75 and the register 78 are equal even if the physical page descriptor s is compared with all the data of the history means 73, become that way. That is, the time monitoring control circuit 78 determines that an access to the corresponding physical page has not been made within the monitoring time, and issues the above-mentioned reset U2 request to the page management control circuit 62 and the page conversion control circuit 52 through the control line 125. put out.
Then, the time monitoring control circuit 78 sends the page address s stored in the register 75 to the page management control circuit 62 and the page conversion control circuit 52 through the data line 131.
Let me know. At the same time, the time monitoring control circuit 78
The signal line 132 interrupts the address generation circuit 65, and the logical page number assigned to the corresponding physical page is input to the address generation circuit 65 through the data line 133. Further, the operation described so far is repeated. The above operation is repeated until there are no more physical page descriptors in the buffer 72.

As described above, by the page management means,
Vector data for logical pages accessed by a task during execution is loaded onto the physical vector register group when necessary. Therefore, it is not necessary to transfer data from the main storage device to the physical vector register group when switching tasks.

The time monitoring means saves the vector data on the physical vector register group independently of the software instruction during the task execution. For this reason,
There is no need to transfer data from the physical vector register group to the main memory when switching tasks.

Further, the trigger for saving the vector data is not given by the task switching, but is divided by a certain fixed time. Therefore, when data transfer is performed between the main memory device and the physical vector register group,
The amount of data transfer does not depend on the number of task switching.
That is, even if the number of task switching is increased, the processing speed does not decrease due to the vector data transfer.

Further, by having a page fault suppression circuit, even for a logical page allocated in the same state as before, from the value of the physical page fault bit,
It is possible to omit useless operations such as unconditionally performing physical page absence processing. For this reason, performance does not occur due to vector data loading of each software instruction,
Furthermore, the processing speed of the entire apparatus can be maintained at a high speed.

[0079]

The present invention is based on the above-described method.
Since the vector data is processed and the data used for it is transferred, the following effects can be obtained.

At the time of task switching, there is no need to transfer data from the main storage device to the physical vector register group, and it is sufficient to transfer a required amount of data as necessary. Therefore, the main storage device and the physical vector register group can be transferred. It is possible to minimize the load of vector data to and from the group.

Therefore, since the minimum necessary vector data need only be transferred, the saving of vector data from the physical vector register group into the main storage device can be minimized.

By the time monitoring means, during task execution,
Since the vector data on the physical vector register group may be saved independently of the software instruction, the software instruction can be executed regardless of the vector data transfer.

Since the trigger for saving the vector data is not given by the task switching but is divided by a certain fixed time, when the data transfer is performed between the main storage device and the physical vector register group, the data transfer amount Does not depend on the number of times of task switching, so that even if tasks are switched frequently, the processing speed can be kept high without lowering the speed of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a vector data processing device according to an embodiment of the present invention and an information processing system to which a data transfer method used therein is applied.

FIG. 2 is a block diagram showing a detailed configuration of an instruction control unit included in the vector data processing device shown in FIG.

FIG. 3 is a block diagram showing a detailed configuration of page conversion means provided in the vector data processing device shown in FIG.

FIG. 4 is a block diagram showing a detailed configuration of page management means provided in the vector data processing device shown in FIG.

5 is a block diagram showing a detailed configuration of a time monitoring means provided in the vector data processing device shown in FIG.

6 is a block diagram showing a detailed configuration of a page fault processing suppression circuit provided in the vector data processing device shown in FIG.

FIG. 7 is a block diagram showing a configuration of a conventional vector data processing device.

[Explanation of symbols]

10,300 Main storage device 11,303 Arithmetic and logic operation unit 20,301 Physical vector register group 30,304 Instruction control unit 31 Instruction decoder 32,33,35,64,75,77,81 register 34 Adder 40 Data transfer means 50 page conversion means 51 page table 52 page conversion control circuit 60 page management means 61 page management table 62 page management control circuit 63 decoder 65 address generation circuit 70 time monitoring means 71 timer 72 buffer 73 history means 74 time monitoring control circuit 76 task comparison Circuit Page 78 Comparison Circuit 80 Page Absence Processing Suppression Circuit 82 Comparison Circuit

Claims (4)

[Claims] 1. A vector data processing device for processing a plurality of tasks in a time-division manner, which is a set of actual vector registers for holding vector data, each of which has a predetermined size with a physical page number. A physical vector register group divided into physical pages; a main memory device; a data transfer means for transferring data between the physical vector register group and the main memory device; and a software instruction to control the physical vector register group. And a vector data processing device having an instruction control unit for holding a task number for identifying a task currently being executed, each task is a set of virtual vector registers individually, and a logical page number for each task. Assuming a logical vector register group that is evenly divided into logical pages having the same size as the physical page. , The logical page required when executing each task is allocated to the corresponding physical page in the physical vector register group, and when the execution of the task is completed, vector data on the physical page to which the logical page is allocated is stored in the main storage device. By saving the physical vector register group to the plurality of tasks, and the physical page number allocating the logical page corresponding to each logical page and the physical page number are currently invalid values. When the task number and the logical page number are input from the instruction control unit, the physical page information is displayed by referring to the logical page information. The page number is output to the command control unit and the page fault processing request by the page fault display is output. Page conversion means and physical page information consisting of the usage status information of each physical page and the history of the task number accessed at the end of the physical page corresponding to each physical page, and responding to the page absence request. Then, the physical page information is searched for a new physical page to be allocated to the logical page, and the corresponding page information is updated in the physical page information and the logical page information. A vector data processing device comprising: a page management unit that controls the data transfer unit so that vector data of the logical page stored in the physical page is loaded onto the newly allocated physical page. 2. A vector data processing device for processing a plurality of tasks in a time-sharing manner, which is a set of actual vector registers for holding vector data, each of which has a predetermined size with a physical page number. A physical vector register group divided into physical pages; a main memory device; a data transfer means for transferring data between the physical vector register group and the main memory device; and a software instruction to control the physical vector register group. And a vector data processing device having an instruction control unit for holding a task number for identifying a task currently being executed, each task is a set of virtual vector registers individually, and a logical page number for each task. Assuming a logical vector register group that is evenly divided into logical pages having the same size as the physical page. , The logical page required when executing each task is allocated to the corresponding physical page in the physical vector register group, and when the execution of the task is completed, vector data on the physical page to which the logical page is allocated is stored in the main storage device. By saving the physical vector register group to the plurality of tasks, and the physical page number allocating the logical page corresponding to each logical page and the physical page number are currently invalid values. When the task number and the logical page number are input from the instruction control unit, the physical page information is displayed by referring to the logical page information. The page number is output to the command control unit and the page fault processing request by the page fault display is output. Page conversion means and physical page information consisting of the usage status information of each physical page and the history of the task number accessed at the end of the physical page corresponding to each physical page, and responding to the page absence request. Then, the physical page information is searched for a new physical page to be allocated to the logical page, and the corresponding page information is updated in the physical page information and the logical page information. A page management means for controlling the data transfer means so as to load vector data of the logical page stored in the new physical page to be allocated, and a timer for outputting a monitoring start request at a prescribed interval. A buffer for storing the history of software instructions, and in response to the monitoring start request, the physical page information regarding the physical page in use is selected from the physical page information. Information that is read and compared with the history of each instruction by the software, and for physical pages for which there is no matching software instruction, time monitoring means that requests the page management means to update the physical page information, Vector data processing device having. 3. A vector data processing device for processing a plurality of tasks in a time-sharing manner, which is a set of actual vector registers holding vector data, each of which has a predetermined size with a physical page number. A physical vector register group divided into physical pages; a main memory device; a data transfer means for transferring data between the physical vector register group and the main memory device; and a software instruction to control the physical vector register group. And a vector data processing device having an instruction control unit for holding a task number for identifying a task currently being executed, each task is a set of virtual vector registers individually, and a logical page number for each task. Assuming a logical vector register group that is evenly divided into logical pages having the same size as the physical page. , The logical page required when executing each task is allocated to the corresponding physical page in the physical vector register group, and when the execution of the task is completed, vector data on the physical page to which the logical page is allocated is stored in the main storage device. By saving the physical vector register group to the plurality of tasks, and the physical page number allocating the logical page corresponding to each logical page and the physical page number are currently invalid values. When the task number and the logical page number are input from the instruction control unit, the physical page information is displayed by referring to the logical page information. The page number is output to the command control unit and the page fault processing request by the page fault display is output. Page conversion means and physical page information consisting of the usage status information of each physical page and the history of the task number accessed at the end of the physical page corresponding to each physical page, and responding to the page absence request. Then, the physical page information is searched for a new physical page to be allocated to the logical page, and the corresponding page information is updated in the physical page information and the logical page information. A page management means for controlling the data transfer means so as to load vector data of the logical page stored in the new physical page to be allocated, and a timer for outputting a monitoring start request at a prescribed interval. A buffer for storing the history of software instructions, and in response to the monitoring start request, the physical page information regarding the physical page in use is selected from the physical page information. And comparing the history of each instruction by the software, and for a physical page for which there is no matching software instruction, time monitoring means for requesting the page management means to update the physical page information, The task history is read out from the physical page information related to the physical page to which the logical page designated by software is allocated, and compared with the currently executing task number obtained from the instruction control unit, and both are equal. Then, a vector data processing device comprising: a page fault processing inhibiting circuit that outputs a page fault process cancellation request to the page management means. 4. A vector data processing device for processing a plurality of tasks in a time-division manner, wherein when switching a first task to a second task, the first data is stored in a physical vector register group, Means for saving only vector data updated according to the execution result of the task in the main storage device, and vector data necessary for executing the second task among the vector data saved in the main storage device. And a means for loading only the physical vector registers into the physical vector register group.