JPH05324376A - Duplexing mechanism in information processor - Google Patents

Abstract

PURPOSE:To reduce the pin number of a chip and also to secure the coincidence of operations in the respective chips when the function of a main processor is realized by one chip to duplex it. CONSTITUTION:The duplexing mechanism of an information processor which is provided with the main processor constituted by the plural chips of same configuration is characterized in such a way that an input signal being common to all the chips and an identification signal being intrinsic in the respective chips are adopted as an input to the respective chips, the respective chips selects generating means 31 and 41 generating a signal and the generated signal in accordance with the identification signal and output means 32 and 42 for outputting are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplication mechanism of an information processing apparatus for realizing the function of a main processing unit by one chip and duplicating it.

[0002]

2. Description of the Related Art Conventionally, when the function of a main processing unit is realized by one chip and is duplicated, each chip has no discrimination regarding output signals, all chips output the same, and the matching check is performed. , Guaranteed to match the operation of all chips.

[0003]

In this conventional duplication mechanism of the information processing apparatus, all the chips output the same, so that each chip has to output all of the output signals required as the main processing unit. , The number of pins on the chip increases. If the number of pins of the chip does not fall within the limit, there is a problem that it is necessary to reduce the functions and output signals. Further, since the coincidence check is performed for all of the large number of output signals, there is a problem that the amount of hardware increases.

[0004]

According to another aspect of the present invention, there is provided a duplication mechanism for an information processing apparatus, which is an input signal common to all chips in the duplication mechanism for an information processing apparatus including a main processing unit configured by a plurality of chips having the same configuration. And an identification signal peculiar to each chip as an input to each chip, each chip having a generation means for generating a signal and an output means for selecting and outputting the generated signal according to the identification signal. ..

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, in this embodiment, a main processing unit 1 is composed of two LSIs 3 and 4. The main processing device 1 also has a checking means 5 and is connected to the main storage device 2 and the diagnostic device 6. The following description will be made only for accessing the main storage device 2.

When the main processing unit 1 reads data from the main storage unit 2, the generation unit 31 generates a command CMD1 and an address ADR1 indicating the read of the main storage unit 2, and the generation unit 41 also outputs the command CMD2 and address AD.
Generate R2. The commands CMD1 and CMD2 and the addresses ADR1 and ADR2 have the same value.

The command CMD1 and the address ADR1 are
It is input to the selector 33 in the output means 32. The identification signal ID1 is input to the selector 33, and the identification signal I
The command CMD1 is selected from the command CMD1 and the address ADR1 according to D1 and is output as the signal CDAD1. On the other hand, the command CMD2 and the address ADR2 are similarly selected by the selector 43 in the output means 42 according to the identification signal ID2, and the address ADR2 is output as the signal CDAD2. In this way, the signal CDAD1 representing the command CMD1 is output from the LSI3, and the signal CDAD2 representing the address ADR2 is output from the LSI4 and input to the main storage device 2.

Further, in the generating means 31, the command CMD1
The parity signal CMDP1 and the parity signal ADRP1 of the address ADR1 are generated and output through the output means 32. The generation unit 41 also generates the parity signal CMDP2 of the command CMD2 and the parity signal ADRP2 of the address ADR2, and outputs the parity signal ADRP2 through the output unit 42. These signals are input to the checking means 5,
The comparator 51 outputs the parity signal CMDP1 and the parity signal CMDP2, and the comparator 52 outputs the parity signal CMRP1.
And the parity signal ADRP2 are compared with each other, and if they do not match, they are reported to the diagnostic device 6 as error signals ER1 and ER2, respectively.

The parity signal CMDP1 and the parity signal ADRP2 are input to the main memory 2 and used as the parity of the signals CDAD1 and CDAD2, respectively. In the main memory 2, signals CDAD1 and CDA
The read data MRD corresponding to D2 is output. The read data MRD is the LSI 3 and the LSI 4 of the main processing unit 1.
Entered in. Since the command and the address are usually composed of several bytes, only the parity is output in this example, and the number of output pins of the LSIs 3 and 4 is greatly reduced.

Referring to FIG. 2 showing the second embodiment of the present invention, this embodiment also comprises two LSIs 30 and 40, and each of the LSIs 30 and 40 has a check means 39.
And 49, and the output means 35 and 45 have three selectors 36, 37, 38 and 46, 47, 48.

In the generating means 34, the command CMD1, the address ADP1 and the two parity signals CMDP1,
ADRP1 is generated, and the command CM is generated by the generation means 44.
D2, address ADR2 and two parity signals CM
The generation of DP2 and ADRP2 is the same as in the case of the first embodiment.

Selectors 36, 37, 3 in the output means 35
8, the selection is performed according to the identification signal ID1, the command CMD1 is selected from the command CMD1 and the address ADR1, the parity signal CMDP1 is selected from the parity signal CMRP1, the parity signal CMDP1 is selected from the parity signal CMDP1, and the parity signal ADRP1 is selected from the parity signal ADRP1. The signals are selected and become the signal CDAD1, the signal CDADP1, and the signal CDADPX1.

Selectors 46, 47, 4 in the output means 45
8, the selection is performed in accordance with the identification signal ID2, the command CMD2, the address ADR2 to the address ADR2, the parity signal CMDP2 and the parity signal A.
The parity signal ADRP2 is selected from DRP2, the parity signal CMDP2 is selected from the parity signal CMDP2, and the parity signal CMDP2 is selected from the parity signal ADRP2 to become the signal CDAD2, the signal CDADP2, and the signal CDADPX2.

Of these signals, the signal CDAD1, the signal CDADP1, the signal CDAD2 and the signal CDADP2
Is input to the main storage device 2. Also, the signal CDADPX1
Is input to the check means 39, and the signal CDADPX2 is input to the check means 49. On the other hand, the CDADP1 output from the LSI 30 is input to the LSI 40, compared with the signal CDADPX2 by the comparator in the check means 49, and if a mismatch is detected, the error signal ER2 is input to the diagnostic device 6. Further, the signal CDADF2 output from the LSI 40 is input to the LSI 30, compared with the signal CDADPX1 by the comparator 3A in the check means 39, and if a mismatch is detected, the error signal ER1 is input to the diagnostic device 6.

By the above processing, the coincidence check of the signals generated by the generation means 34, 44 is performed inside the LSIs 30, 40.

In each of the above embodiments, the number of LSIs is two, but the number of LSIs may be three or more.

It is also conceivable that the matching check of the signals generated by the generating means is performed outside the chip. In this aspect, while suppressing an increase in the number of cells in the chip,
Enables signal matching check.

[0019]

As described above, according to the present invention, since only the parity signal among the signals output from the chip needs to be output, the number of pins can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

1, 10 Main processing device 2 Main storage device 3, 4, 30, 40 LSI 5, 39, 49 Checking device 6 Diagnostic device 31, 34, 41, 44 Generating device 32, 35, 42, 45 Output device 33, 34, 36, 37, 38, 46, 47, 48
Selector 3A, 4A, 51, 52 Comparator

Claims (3)

[Claims] 1. In a duplication mechanism of an information processing apparatus having a main processing unit composed of a plurality of chips having the same configuration, an input signal common to all chips and an identification signal unique to each chip are used as inputs to each chip. The duplexing mechanism of the information processing device, wherein each chip has a generation unit that generates a signal and an output unit that selects and outputs the generated signal according to the identification signal. 2. A parity signal is added to the signal generated by the generating means, the parity signal is not selected by the output means, is output from all chips, and the parity signals output from all chips are matched. 2. The duplication mechanism for an information processing apparatus according to claim 1, further comprising a check means for checking outside the chip. 3. A chip in which a parity signal is added to the signal generated by the generation means, the parity signal is also selected by the output means, and the parity signal is output only from a specific chip while the parity signal is not output. 2. The duplication mechanism for an information processing apparatus according to claim 1, further comprising check means for inputting the parity signal into the chip and checking whether the parity signals match each other inside the chip.