JPH05324144A - Function setting circuit - Google Patents

Abstract

PURPOSE:To make it possible to instantaneously set up a port function and an output signal after turning on a power supply. CONSTITUTION:Reading signals 51 to 54 are respectively read out from ROM cells 55a to 55d. When the reading signal 51 is in a high level, an output PAD is set up to a CMOS type output PAD, and at the time of a low level, set up to an n-channel open drain type output PAD. The initial output statue of the output PAD is set up by the reading signal 52. When the reading signal 53 is in a low level, a p-channel MOSFET 61 is turned on and an input PAD is pulled up. When the reading signal is in a high level, an n-channel MOSFET 62 is turned on and the input PAD is pulled down. Thus, the port function and the initial output signal are instantaneously set up after turning on the power supply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to selection of a CPU port function and setting of port output data at the time of initial operation, and in particular to a CPU port output format such as CMOS type or N channel open drain type. , Pull-up input type, pull-down input type, and set the port initial output to high level, low level, or unconnected.

[0002]

2. Description of the Related Art Conventionally, the port function of a CPU has been set by the following two methods.

(1) The first method is to set the port function of the CPU during the manufacturing process of the integrated circuit.
That is, a plurality of masks are prepared, a mask pattern is selected according to a desired port function of the CPU, a port is formed, and the CPU has a desired port function.

(2) In the second method, the CPU itself is the ROM
It is a method of setting a port function in accordance with an instruction stored in, for example. In this method, as shown in FIG.
After DD rises and the CPU power supply reset is released, CP is activated by using a normal instruction cycle or a dedicated instruction cycle.
U reads the data for port function setting from ROM,
The function of each port of the CPU is set based on the read data.

[0005]

However, in the method of selecting the CPU port function by the mask, since the manufacturing mask is used to select the function, a large number of masks are required to perform the function selection. Is difficult. In particular, as the number of types of functions increases, so many masks are required, and short-term production becomes more difficult.

Next, in the ROM read method by the instruction cycle, after the reset of the CPU is released, the data is read from the ROM 75 and the port function of the CPU is selected by using a normal instruction cycle or a dedicated instruction cycle. Therefore, as shown in FIG. 4, there is a problem that the function of the port of the CPU and the selection of the output signal cannot be selected after the power is turned on until the execution of the function setting instruction is completed.

That is, as shown in FIG. 4, generally, it takes 10 ms, which is about 3 instruction cycles, from the rise of the power supply voltage VDD to the output of the reset signal RES, and thereafter, the setting is generally completed in about 8 instruction cycles. .. During this time, the output format of the CPU port cannot be switched, and for example, the output format is fixed to the N-channel open drain output format. Therefore, it is 1 after turning on the power.
This scheme could not be used for ICs that needed another output format such as CMOS format during 0ms + 11 instruction cycles. The present invention has been made in view of the above circumstances, and CP
The purpose is to set the port function and output signal of U immediately after the power is turned on.

[0008]

A function setting circuit according to the present invention comprises a read-only memory for outputting function setting data in response to power-on, a power supply voltage supplied to one end of a current path, and a gate electrode having the above-mentioned structure. Function setting data from the read-only memory is supplied, the other end of the current path is connected to the input terminal of the input / output circuit, and a pull-up transistor,
One end of the current path is connected to the other end of the current path of the pull-up transistor and the input terminal, the function setting data from the read-only memory is supplied to the gate electrode, and the other end of the current path is grounded. It is equipped with a pull-down transistor and its function is set immediately after the power is turned on.

[0009]

In response to the power-on, the read-only memory supplies the function setting data to the gate electrode of the pull-up transistor to set the function of the pull-up transistor. The read-only memory supplies the function setting data to the gate electrode of the pull-down transistor to set the function of the pull-down transistor. As a result, the functions of the pull-up transistor and the pull-down transistor are set immediately after the power is turned on.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A CPU having a function setting circuit according to an embodiment of the present invention will be described below with reference to the drawings. First, the CPU shown in FIG. 1 has a plurality of ROM cells 55a to 55d, AND gates A1 and A2, OR gates 66 and P.
Channel MOSFET 63, N-channel MOSFET 6
4, 65, a pull-up transistor 61, and a pull-down transistor 62.

Next, the structure of the function setting circuit will be described. Input PAD (input terminal) is P channel MOSFE
It is connected to the connection point between the other end of the current path of T61 and one end of the current path of the N-channel MOSFET 62. Also, input P
AD is connected to the input terminal of the inverter 67, and the output signal of the inverter 67 is supplied to an internal circuit (not shown) in the CPU. The power supply voltage VDD is supplied to one end of the current path of the P-channel MOSFET 61, and the read signal 53 from the ROM cell 55c is supplied to the gate electrode. The other end of the current path of the N-channel MOSFET 62 is grounded, and the read signal 54 from the ROM cell 55d is supplied to the gate electrode. First of AND gate A1
The port data from the CPU is supplied to the input terminal of, and the reset signal RES is supplied to the inverting input terminal.

A reset signal RES is supplied to the first input terminal of the AND gate A2, and R is supplied to the second input terminal.
The read signal 52 from the OM cell 55b is supplied. The output end of the AND gate A1 and the output end of the AND gate A2 are connected to the input end of the OR gate 66, and the output end of the OR gate 66 is connected to the gate electrodes of the P-channel MOSFET 63 and the N-channel MOSFET 65.

The power supply voltage VDD is supplied to one end of the current path of the P-channel MOSFET 63, and the other end of the current path is connected to one end of the current path of the N-channel MOSFET 64. The other end of the current path of the N-channel MOSFET 64 is connected to one end of the current path of the N-channel MOSFET 65. The connection point between the other end of the current path of the N-channel MOSFET 64 and the one end of the current path of the N-channel MOSFET 65 is connected to the output PAD (output terminal). N
The other end of the current path of the channel MOSFET 65 is grounded. In the gate electrode of the N-channel MOSFET 64,
The read signal 51 from the ROM cell 55a is supplied.

Next, the setting operation of the port function of the CPU shown in FIG. 1 will be described. After the power is turned on, the power supply voltage VDD
2 rises to the operating voltage of the circuit of 4.5 V as shown in FIG. 2A, the ROM cells 55a to 55d read the stored data and output it as read signals 51 to 54.

Read signal 51 from ROM cell 55a
Is high level, the N-channel type MOSFET 64 is turned on and the output PAD is set to the CMOS type output PAD. When the read signal 51 is low level,
The N-channel MOSFET 64 is turned off and the output PAD is N
It is set to a channel open drain type PAD.

The read signal 52 from the ROM 55b will be described. Immediately after the power is turned on, the reset signal RES- is at a low level and its inverted signal RES is at a high level as shown in FIG. 2 (c). Therefore, the output of the AND gate A1 becomes low level regardless of the port data.

On the other hand, the output signal of the AND gate A2 becomes high or low level depending on the level of the read signal 52. Therefore, when the read signal 52 is high level, a high level signal is obtained from the output end of the OR gate 66, and when it is low level, a low level signal is obtained. The output signal of the OR gate 66 is a P-channel MOS
It is supplied to the FET 63 and the gate electrode of the N-channel MOSFET 65.

Therefore, the read signal 51 is at a high level, the N-channel MOSFET 64 is on, and the output PAD is
Is set to the CMOS type output PAD, an output signal of either high level or low level is output from the output PAD according to the read signal 52. On the other hand, the read signal 51 is low level, the N-channel MOSFET 64 is off, and the output PAD is the N-channel open drain type PAD.
When the read signal 52 is at the high level, the output signal from the output PAD is fixed at the low level, and when the read signal 52 is at the low level, the output PAD is opened.

After that, when the reset signal RES_ becomes high level, the AND gate A2 is turned off and the AND gate A1 outputs an output signal according to the signal level of the port data. Therefore, when the read signal 51 is at high level, a signal corresponding to the port data is output from the output PAD. On the other hand, when the read signal 51 is low level, the output signal from the output PAD is low level if the port data is high level, and the output PAD is open state if the port data is low level.

Next, when the read signal 53 is at low level, the P-channel MOSFET 61 is turned on and the input P
AD is pulled up. When the read signal 53 is at high level, the P-channel MOSFET 61 is turned off and the input PAD is not pulled up.

When the read signal 54 is at high level, N
The channel MOSFET 62 is turned on and the input PAD is pulled down. When the read signal 54 is low level, the N-channel MOSFET 62 is turned off and the input PA
D is not pulled down. As a result, as shown in FIG. 2, the switching of the port function of the CPU is completed immediately after the power is turned on in accordance with the data described in the ROM cells 51 to 54.

Next, a specific configuration example of the ROM cells 55a to 55d will be described. The ROM cell shown in FIG. 3A is an example in which an EPROM cell is used.
When the voltage division at the connection point 2 determined by the writing amount of the ROM cell 3 is equal to or lower than the threshold voltage of the inverter 5, the output signal 4 becomes high level, and the voltage division at the connection point 2 becomes equal to the inverter 5.
When the voltage exceeds the threshold voltage of, the output signal 4 becomes low level. The output signal 4 of the inverter 5 becomes the read signals 51 to 54 shown in FIG.

The ROM cell shown in FIG. 3B has a mask R
This is an example using an OM cell. When the mask ROM cell 11 or 12 is implanted with ions and the mask ROM cell 11 is off and the mask ROM cell 12 is on, the output signal 14
Goes low. On the other hand, when the mask ROM cell 12 is off and the mask ROM cell 11 is on, the output signal 14
Goes high. The output signal 14 is the read signal 51.
Through 54.

The ROM cell shown in FIG. 3C has a mask R
This is an example applicable to both the OM cell and the EPROM cell. The mask ROM cell 24 is in the ON state and the capacitor C
Before the charge is stored in 1, the power supply voltage VDD (high level) is supplied to the inverter 21b,
Inverts this high-level signal and outputs the low-level signal 2
3 is output.

After the electric charge is accumulated in the capacitor C1,
A low level signal is supplied to the input terminal of the inverter 21b, and a high level signal is output from the input terminal of the inverter 21b. This high level signal is supplied to the capacitor C2, and the capacitor C2 is charged. Inverter 2
Since the output signal of 1b is high level and the capacitor C2 is charged, the signal 23 becomes high level, and the high level signal 23 is latched by the latch circuits 21a and 21b.

When the mask ROM 24 cell is off,
The electric charge is not accumulated in the capacitor C1, the potential of the input end of the inverter 21b is always held at the high level by the power supply voltage VDD, and the inverter 21b outputs the low-level signal 23. The low-level signal 23 is latched by the latch circuits 21a and 21b.

The ROM cell shown in FIG. 3D is a mask RO.
This is an example applicable to both M and EPROM. When the mask ROM 34 is on and the mask ROM 35 is off, the read signal 33 becomes high level. Further, when the mask ROM 34 is off and the mask ROM 35 is on, the read signal 33 becomes low level. The read signal 33 is held by the latch circuit including the inverters 31a and 31b. The ROM cell 5
Any of the memory cells of FIGS. 3A to 3D may be used as 5a to 55d.

In the above embodiment, since the initial state of the port function of the CPU is determined by the data for each product, the manufacturing process can be reduced and the production period can be shortened. In addition, since the port function of the CPU can be changed by changing the data in the memory, the degree of freedom is increased and it can be used for general purposes. Secondly, since the initial state of the CPU is stable with the selected function, the application field is expanded.

Thirdly, in the above embodiment, since the CPU port function is set regardless of the clock signal, it is possible to eliminate the non-selected state of (reset time + instruction execution time) until the setting of the function is completed. it can.

[0030]

According to the present invention, the port function and the output signal can be set immediately after the power is turned on.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a CPU according to an embodiment of the present invention.

FIG. 2 is a timing chart relating to a port function setting operation of the CPU shown in FIG.

3 is a diagram showing a specific configuration of the ROM cell shown in FIG.

FIG. 4 is a timing chart relating to a port function setting operation of a conventional CPU.

[Explanation of symbols]

55a to 55d ... ROM cells, 51 to 54 ... Read signals, 61, 63 ... P-channel MOSFETs, 62, 6
4, 65 ... N-channel MOSFET.

Claims (4)

[Claims] 1. A read-only memory that outputs function setting data in response to power-on, a power supply voltage is supplied to one end of a current path, and a function setting data from the read-only memory is supplied to a gate electrode. A pull-up transistor in which the other end of the current path is connected to the input terminal of the input / output circuit, and one end of the current path is connected to the other end of the current path of the pull-up transistor and the input terminal, and a gate electrode Is provided with a function setting data from the read-only memory and the other end of the current path is grounded, and the function is set immediately after the power is turned on. circuit. 2. A read-only memory for outputting function setting data in response to power-on, and a function for resetting the function setting data from the read-only memory and the port data from the CPU,
A selection circuit for switching and outputting; a first transistor in which a power supply voltage is supplied to one end of a current path and an output signal of the selection circuit is supplied to a gate electrode; and a current of the first transistor in one end of a current path. The other end of the current path is connected, the gate electrode is supplied with the function setting data from the read-only memory, and the other end of the current path is connected to the output terminal. A third transistor which is connected to the output terminal, the output signal of the selection circuit is supplied to the gate electrode, and the other end of the current path is grounded, and which corresponds to the function setting data from the read-only memory. A function setting circuit in which the function of the output circuit and the initial output are set. 3. The first and third MOS transistors have opposite conductivity types, and when the second transistor is turned on in response to the function setting data, the output circuit is set to CMOS type. 3. The function setting circuit according to claim 2, wherein the output circuit is set to an open drain type when the second transistor is off. 4. The first to third MOS transistors respond to the output of the selection circuit and the function setting data from the read-only memory to change the initial output from the output terminal to low level, high level and The function setting circuit according to claim 2, wherein the function setting circuit is set to one of high impedance.