JPH05323893A - Operation part controller - Google Patents

Abstract

PURPOSE:To prevent an LED, etc., from deteriorating or burning owing to the continuous driving of a device such as the LED due to an open circuit of a data signal line or synchronizing signal line by stopping driving the device in the case where the signal from a main control part does not vary for a previously set time and longer. CONSTITUTION:The operation part controller which drives the device 4a on a dynamic scanning basis according to the signal from the main control part 5 is provided with a detecting circuit 2 which detects the variation state of the signal and a timer 3 which clocks a time. This controller is provided with a control circuit 4 which decides whether or not the data signal, etc., varies in the certain set time, e.g. a time corresponding to a single scan, and stops driving the device 4a when not. Consequently, a large current is prevented from flowing for a long time in a state wherein all devices or the specific device 4a is continuously driven to eliminate the possibility that the device 4a deteriorates or burns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation section control device for driving a device by a dynamic scan system in response to a data signal or a synchronization signal from a main control section.

[0002]

2. Description of the Related Art Heretofore, as a method of controlling the display of an operation section provided in, for example, a copying machine, a dynamic scan method capable of reducing the number of control lines for driving a device is known.

That is, in this dynamic scan type operation section, devices such as LEDs and buzzers are connected between a plurality of digit lines and segment lines arranged in a matrix. Then, based on a data signal from the main control unit that controls the main body of the copying machine or the like, the above digit lines are sequentially activated at a constant cycle, and the activated digit line L
Of the devices such as ED, the segment line to which the required LED is connected is activated, and the L
The ED is lit up.

By the way, in the above dynamic scan method, the LED lights up only during a period in which both the corresponding digit line and segment line are in an active state, and the lighting period is shorter than the extinguishing period. Will be reduced. Therefore, conventionally, the current supplied to the LEDs has been increased to increase the average brightness of the LEDs.

[0005]

However, due to a failure of the data generation circuit of the main control unit or a disconnection of the data signal line or the synchronization signal line between the main control unit and the operation unit, the data is input to the operation unit. When the data signal does not change, the LED remains lit, and a large current flows through the LED and the driver for driving the LED for a long time. As a result, there is a possibility that the LEDs, the driver, and the like may be deteriorated and burned.

The present invention solves the above-mentioned problems, and an operation for preventing deterioration and burnout of an LED or the like due to a device such as an LED being left driven due to a disconnection of a data signal line or a synchronizing signal line. An object of the present invention is to provide a partial control device.

[0007]

In order to achieve the above object, the present invention relates to an operation unit control device for driving a device by a dynamic scan system in response to a signal from a main control unit. It is provided with a detecting means for detecting, a timer for measuring time, and a drive stopping means for stopping driving of the device when the signal has not changed for a preset time or longer.

According to the second aspect of the invention, the detecting means detects the change state of the synchronization signal included in the signal.

Further, in claim 3, the detecting means detects the change state of the data signal included in the signal.

Further, the fourth aspect comprises a changing means for changing the set time.

[0011]

According to the operation part control device having the above structure, the change state of the signal from the main control part is detected, the time is timed, and the drive of the device is stopped when the signal has not changed for the set time or more. By doing so, it is possible to prevent the device from being driven due to disconnection of the data signal line or the synchronization signal line.

According to another aspect of the present invention, the operating portion control device detects the change state of the synchronization signal from the main control portion, and stops the driving of the device when the synchronization signal has not changed for the set time or longer. To be done.

Further, according to the operation unit control device of the present invention, the change of the data signal from the main control unit is detected, and the drive of the device is stopped when the data signal has not changed for the set time or more. It

According to the operating section control device of the fourth aspect, the setting time can be changed so that the setting can be made according to the signal from the main control section.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a dynamic scan type operation unit controller according to the present invention. This operation unit control device includes a data receiving circuit 1, a detection circuit 2, a measurement timer 3, a device control circuit 4 and a device 4a, and an LED, a buzzer, etc., according to a data signal transmitted from the main control unit 5 in real time. Device 4
a is dynamically driven.

The main control section 5 indicates scan data b0 to b15 and scan address data b16 to b1 for instructing the drive of the device 4a as shown in FIG. 8 in order to instruct the dynamic scanning of the device 4a such as an LED.
The data b0 to b18 consisting of 8 are transmitted to the data receiving circuit 1 serially or in parallel. In addition,
When the main control unit 5 transmits data serially,
With the above data b0 to b18, as shown in FIG.
A frame synchronization signal FSYNC as a timing reference signal for dynamic control and a bit synchronization signal SCLK as a timing reference signal for each bit of serial data.
Is to be transmitted.

The data receiving circuit 1 includes a data signal transmitted from the main control section 5 and synchronizing signals FSYNC and SCL.
K is received, and further, the data signal and the like are output to the detection circuit 2 and converted into parallel data and output to the device control circuit 4.

Based on the data signal from the data receiving circuit 1, the device control circuit 4 has a plurality of digit lines D0 to D7 (see FIG. 7) and segment lines S0 to S15 (see FIG. 7) arranged in a matrix. Are sequentially activated to drive the devices 4a such as LEDs and buzzers connected between the digit lines D0 to D7 and the segment lines S0 to S15 by dynamic scanning.

The detection circuit 2 changes the state of the data signal and the synchronization signals FSYNC and SCLK from the data receiving circuit 1, that is, whether the data signal changes from low level to high level or from high level to low level. The detection result is output to the measurement timer 3. The measurement timer 3 counts time. Further, the measurement timer 3 is configured to reset the time counting operation when a signal indicating that the data signal or the like has changed is input from the detection circuit 2. Further, the measurement timer 3 receives the signal from the device 4a when a signal indicating that the data signal has changed is not input by a preset time, for example, a time corresponding to one scan.
A stop signal is output to the device control circuit 4 in order to stop the driving of the device.

That is, normally, all the devices 4a of the operation unit are not driven at the same time (LEDs are turned on), and the data signal and the synchronization signals FSYNC and SCLK instructing the dynamic scan are supplied within one scan period. Change at least once. However, when a disconnection occurs in the data signal line or the synchronization signal line between the main control unit 5 and the operation unit, the data b received by the data receiving circuit 1
0 to b18 become constant, or the synchronization signal FSYN
C and SCLK are not generated, and the signal does not change.
If the device 4a such as an LED is driven in this state, all or a specific device 4a may be left in a driven state and a large current may flow for a long time, which may cause deterioration or burning of the device 4a. Therefore, it is determined whether or not the data signal or the like has changed within the set time, for example, the time corresponding to one scan, and when the data signal or the like has not changed for the set time or more, the device 4a
The drive of is stopped.

When the stop signal from the measurement timer 3 is input, the device control circuit 4 receives the device 4a.
The drive of is stopped forcibly. The drive stopped state is released by, for example, manually operating the system reset switch, and the drive is restarted.

As described above, the devices 4a such as LEDs are sequentially dynamically driven according to the data signal from the main control section 5, and the data signal and the synchronization signal FSYN are set within the set time.
When there is no change in C and SCLK, the device 4a is forcibly stopped because it is determined that a failure such as disconnection has occurred, so that it is possible to prevent the device 4a from being driven due to the disconnection or the like. ..

Next, detailed configurations of the data receiving circuit 1, the detection circuit 2, the measurement timer 3 and the device control circuit 4 will be described. First, the detailed configuration of the data receiving circuit 1 will be described with reference to FIGS. 2 shows a circuit formed when the data signal from the main control unit 5 is parallel, and FIG. 3 shows a circuit formed when the data signal from the main control unit 5 is serial. ..

That is, in FIG. 2, the data receiving circuit 1
Is composed of a data latch circuit 11. The data latch circuit 11 performs waveform shaping processing by latching parallel data from the main control unit 5, and outputs the processed parallel data to the detection circuit 2 and the device control circuit 4.

In FIG. 3, the data receiving circuit 1 is composed of a data latch circuit 12 and a serial-parallel conversion circuit 13. The data latch circuit 12 includes serial data and sync signals FSYNC, S from the main controller 5.
The waveform shaping process is performed by latching CLK, and the serial data and the synchronization signal FSYN after this process are processed.
It outputs C and SCLK to the detection circuit 2 and the serial-parallel conversion circuit 13. The serial-parallel conversion circuit 13 converts the serial data from the data latch circuit 12 into parallel data based on the synchronization signals FSYNC and SCLK and outputs the parallel data to the device control circuit 4.

Next, the detailed structure of the detection circuit 2 will be described with reference to FIG. Note that FIG. 4 shows a circuit configured when the data signal from the main control unit 5 is serial. The cycle of the clock CLK is the cycle of 1 bit of the serial data SIN and the sync signal FS.
It is set to be considerably shorter than the cycle of YNC and SCLK.

The detection circuit 2 includes a data detection section 21 for detecting a change in the serial data SIN and a frame synchronization signal FS.
It is composed of a frame signal detector 22 for detecting a change in YNC, a bit signal detector 23 for detecting a change in the bit synchronization signal SCLK, and a gate circuit 24. In addition,
The frame signal detector 22 and the bit signal detector 23 are
Since it has the same circuit configuration as the data detection unit 21,
Only the data detector 21 will be described, and the frame signal detector 22 will be described.
The description of the bit signal detection unit 23 will be omitted.

The data detecting section 21 includes a flip-flop 2
10, 211, 219, gate circuits 212, 213, 2
14, 216, 217 and inverters 215, 218. The flip-flop 210 stores serial data SIN which is one clock CLK before, and the flip-flop 211 stores two clocks CLK.
The serial data SIN which is the previous minute is stored.

The gate circuits 212, 213, 214 and the inverter 215 compare the serial data SIN that is two clocks CLK earlier and the serial data SIN that is one clock CLK earlier, and if these data do not match, That is, a high signal is output to the gate circuit 24 when the data signal changes, while a low signal is output to the gate circuit 24 when the data signal does not change.

Flip-flop 219 and gate circuit 21
6, 217 and the inverter 218 are the above-mentioned inverter 2
When a high signal is input from 15, the high signal is latched and output to the gate circuit 24. The detectors 22 and 23 output a high signal to the gate circuit 24 when the sync signals FSYNC and SCLK change.

The gate circuit 24 includes detection units 21, 22, 22.
When a high signal is input from each of the flip-flops 219, 229 and 239 of 23, the counter 31 described later
Is output to the measurement timer 3 and the low signal is output to the gate circuits 216, 226, 236 of the detection units 21, 22, 23.
Then, each of the detection units 21, 22, 23 receives the low signal from the gate circuit 24, and flip-flops 219,
The outputs of 229 and 239 are reset to low level.

In this way, when all the signals of the serial data SIN and the synchronizing signals FSYNC and SCLK are changed, and the high signals are output from the flip-flops 219, 229 and 239 of the detection units 21, 22, 23. Only, the low signal is output to the measurement timer 3.

The flip-flops of the detection units 21, 22, 23 are also reset by a clear signal CR input from the outside of the detection circuit 2.

Next, the detailed structure of the measurement timer 3 will be described with reference to FIG. The measurement timer 3 is the counter 31
It is composed of. The counter 31 counts clock signals, and when the count value reaches a preset value n, outputs a low signal as a stop signal from the output terminal Qn to the device control circuit 4. The counter 31 is configured to reset its count operation when a low signal is input from the gate circuit 24. That is, the count operation of the counter 31 is reset when the low signal is input from the gate circuit 24 within the time from when the count value becomes “0” to the set value n, and thus the low signal is input. The low signal as the stop signal is not output to the device control circuit 4 during the period.

Further, FIG. 6 shows a counter 31 and a selection circuit 3.
2 is provided so that the time until the stop signal is output to the device control circuit 4 can be changed. That is, the counter 31 has count values of m, m + 1,
..., n, the corresponding output terminals Qm, Qm + 1,
A low signal is output from Qn. The selection circuit 32 outputs the output terminals Qm, Qm of the counter 31 according to the selection setting by a setting means such as a switch (not shown).
Any one of the outputs from +1, ..., Qn is output to the device control circuit 4. Then, for example, when the output terminal Qm is selected by the selection circuit 32, when the count value of the counter 31 reaches m, a low signal is output from the output terminal Qm. Then, this low signal is output as a stop signal to the device control circuit 4 via the selection circuit 32.

In this way, since the time until the low signal is output can be selected by the selection circuit 32,
The time can be appropriately changed in accordance with the design change of the dynamic control time, etc., and the labor of design can be reduced.

Next, the detailed structure of the device control circuit 4 will be described with reference to FIG. Device control circuit 4
Is composed of a gate unit 41, a driver 42, and a driver 43. The gate unit 41 is turned on while the high signal is being input from the measurement timer 3 to turn on the driver 4
The data signal from the data receiving circuit 1 is output to the terminals 2 and 43, and when a low signal is input from the measurement timer 3, the data signal is turned off and the output of the data signal to the drivers 42 and 43 is stopped. The driver 42 sequentially activates the segment lines S0 to S15 in a constant cycle according to the data signal from the gate unit 41. Driver 4
The numeral 3 sequentially activates the digit lines D0 to D7 in a constant cycle according to the data signal from the gate section 41.

Among the LEDs 4a of the activated digit lines D0 to D7, the LEDs 4a of the activated segment lines S0 to S15 are dynamically driven (lighted). In addition, LED4a
Are stopped when the gate portion 41 is turned off.

In the above embodiment, the data detector 2
1. Frame signal detector 22 and bit signal detector 23
When the high signal is output from the measurement timer 3, the measurement timer 3 is reset, but the gate circuit (NAND circuit) 24 is replaced with N.
An OR circuit may be provided and the measurement timer 3 may be reset when a high signal is output from at least one of the detection units 21, 22, and 23.

When the data signals from the main control section 5 are parallel, the data detection section 21 is provided for each bit, and when all of these data detection sections 21 output a high signal, the measurement timer 3 may be reset, or the measurement timer 3 may be reset when a high signal is output from at least one of the data detection units 21.

Further, the data detecting section 21, or only one of the frame signal detecting section 22 and the bit signal detecting section 23 may be provided.

[0042]

According to the present invention, the driving of the device is stopped when the signal from the main control unit has not changed for a preset time or longer, so that the LED or the like is broken due to the disconnection of the data signal line or the synchronization signal line. It is possible to prevent the device from remaining driven, and it is possible to prevent deterioration and burnout of the device and the driver of the device. In addition, it is possible to prevent malfunction of the device.

Further, since the set time can be changed, even if the design of the dynamic control time of the signal from the main control unit is changed when the operation unit control device is integrated, this IC can be changed. Instead, the set time can be set according to the design change.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic scan type operation unit control device according to the present invention.

FIG. 2 is a detailed configuration diagram of a data receiving circuit when a data signal from a main control unit is parallel.

FIG. 3 is a detailed configuration diagram of a data receiving circuit when the data signal from the main control unit is serial.

FIG. 4 is a circuit diagram showing a detailed configuration of a detection circuit.

FIG. 5 is a detailed configuration diagram of a measurement timer.

FIG. 6 is a detailed configuration diagram showing another embodiment of the measurement timer.

FIG. 7 is a detailed configuration diagram of a device control circuit.

FIG. 8 is an image diagram showing a configuration of data from a main control unit.

FIG. 9 is a timing chart showing serial data and synchronization signals from the main control unit.

[Explanation of symbols]

 1 data receiving circuit 2 detection circuit 3 measurement timer 4 device control circuit 4a device 5 main control unit

Claims (4)

[Claims] 1. An operation unit control device for driving a device by a dynamic scan system in response to a signal from a main control unit, a detection means for detecting a change state of the signal, a timer for measuring time, and the signal An operation unit control device, comprising: drive stopping means for stopping the driving of the device when it has not changed for more than a preset time. 2. The operation unit control device according to claim 1, wherein the detection means detects a change state of a synchronization signal included in the signal. 3. The operation unit control device according to claim 1, wherein the detecting means detects a change state of a data signal included in the signal. 4. The operation unit control device according to claim 1, further comprising a changing unit that changes the set time.