JPH05323055A - Measuring device of time interval - Google Patents

Abstract

PURPOSE:To measure accurately a time interval between two pulses by a method wherein a triangular wave is generated synchronously with the pulses, analog-to-digital conversion is executed at a first clock and a conversion constant is corrected by inputting a known-interval pulse. CONSTITUTION:A known-interval pulse generator 1 generates known-interval pulses of a prescribed interval and these pulses are inputted together with unknown-interval pulses to an OR gate 2 and then to a flip-flop(FF) 3 and FF 5. A triangular wave generating circuit 4 receives an output of the OR gate 2 and generates a triangular wave. A clock pulse generating circuit 6 generates a clock pulse of a prescribed frequency and inputs it to the FF 5 and an AND gate 8. A counter 10 counts the number A of the clock pulses included between first and second pulses. A Q output of the FF 5 gives the timing of conversion to a conversion start signal generating circuit 9, and based on this timing, an analog-digital converter 7 converts an output voltage of the triangular wave generating circuit into a digital value. With values at the time of the first and second pulses denoted by B and C, a pulse interval TPP is computed by an equation TPP=ATCL+(B-C)/m. The known-interval pulse being inputted, the multiplication rate (m) of conversion of the converter 7 is corrected by a known fractional time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for accurately measuring the time interval between two pulses. Here, the pulse interval means from the rising edge of the first pulse to the rising edge of the second pulse, or from the falling edge of the first pulse to the falling edge of the second pulse. The time when the reference timing is given at the time of rising or falling is referred to as pulse input.
The present invention measures the interval at the time of pulse input of the first and second pulses. Either rising or falling may be used, but for simplicity, the measurement from the rising of the first pulse to the rising of the second pulse will be described below as an example.

Usually, a method is used in which a clock pulse having a high frequency is constantly generated, counting clock pulses from the rising edge of the pulse, and stopping counting at the rising edge of the next pulse. The counting of clock pulses may be rising or falling. The timing that rises or falls and serves as a reference for timing is referred to as clock input. Here, for the sake of simplicity, it is assumed that the clock rises when the clock is input. That is, clock pulses are counted at the rising edge.
The invention is of course applicable to the opposite case as well. When the cycle of the clock pulse is T _CL , the pulse interval T _PP is obtained as an integral multiple of this.

T _PP = AT _CL (1) This is usually the best timekeeping method. The circuit is simple and easy to manufacture. If the clock time T _CL is short, the accuracy will be considerable. However, in this method, the fractional time at the rising edge of the two pulses cannot be known, so an error of up to 1 clock time T _CL occurs. Since the clock pulse and the pulse to be measured are not synchronized, there is uncertainty in which part of one clock the rising edges of the first and second pulses fall. Further, the clock can be made faster, but it cannot be made faster than the limit of the operating frequency of the digital logic IC.

[0004]

2. Description of the Related Art More precise time measurement is possible if it is known more in detail how the first pulse is related to the clock pulse and what the second pulse is related to the clock pulse. Is possible. As such, Japanese Patent Application Laid-Open No. 60-225027 proposes a device for measuring the fraction more accurately in order to measure the time interval between the transmitted wave and the received wave of ultrasonic waves. It generates a triangular wave at the moment of pulse rise to measure the fractional time from the pulse rise to the first clock pulse that follows. The triangular wave is a waveform in which the voltage rises or falls in proportion to time. Then, the voltage of this triangular wave is obtained at the first rising of the clock, and this is analog-digital converted by m (1 / s) times to obtain the fraction.

It is assumed that the time from the rise of the pulse to be clocked to the rise of the first clock pulse is a fractional time. The fractional time of the first pulse is T ₁ , and the fractional time of the second pulse is T ₂ . The exact pulse interval is T _PP = AT _CL + T ₁ −T ₂ (2). It suffices if T ₁ and T ₂ are known, but this is obtained by taking T ₁ and T ₂ as triangular wave voltages and performing analog-to-digital conversion at m times. That is, if the digital output at T ₁ is B and the digital output at T ₂ is C, then T ₁ = T
_CL B / m and T ₂ = T _CL C / m. Obtain B and C as digital values,

The pulse interval is more accurately calculated as T _PP = AT _CL + (B−C) T _CL / m (3). 8 and 9
The above-mentioned JP-A-60-225027 will be described below.
FIG. 8 is a circuit diagram. FIG. 9 is a waveform diagram corresponding to this.

The first pulse is from P to flip-flop 81.
Enter S input. The second pulse enters the R input of flip-flop 81 from R. 9A shows the first pulse P ₁ and FIG. 9B shows the second pulse R ₁ . Since this is an SR flip-flop, it rises with a set input and falls with a reset input. The output Q of the flip-flop 81 rises at the rising edge of the first pulse
It falls at the rising edge of the pulse. This is (c) of FIG.
Is the waveform of.

The width of this wide pulse is the pulse interval T _PP between the two pulses. The clock pulse CLK and the wide pulse C enter the AND gate 83. The product of both is calculated. That is, while the wide pulse C is present, the clock pulse CLK passes through it and is input to the up / down counter 84. This counts the number A of clock pulses included in the wide pulse C. The input of the counter 84 is as shown in FIG.
(D) of.

Although it is a fractional number, another flip-flop 82 is provided to measure this. The set input S of the flip-flop 82 is connected to the oaget 86 for calculating the sum of the first and second pulses. That is, it is set at the rising edges of the first and second pulses. The clock CLK is connected to the reset input of the flip-flop 82. That is, the flip-flop 82 is set by the first and second pulses to have the output Q = 1, and is reset by the first clock CLK. The output Q = 1 only for the fractional times T ₁ and T ₂ .

This is the waveform (e) in FIG. This is integrated by the integrating circuit 87. Since Q = 1 is integrated over time, the output is a triangular wave that increases in proportion to time. FIG. 9 (f) shows the waveform. It is a triangular wave that increases with time T ₁ and T ₂ . This is converted into a digital value by the analog-digital converter 88. The conversion ratio at this time is m. It is assumed that the integrated value at T ₁ is B and the integrated value at T ₂ is C. Obviously, B is proportional to T ₁ and C is proportional to T ₂ . The subtractor 85 stores B and inputs C at the end of the wide pulse,
Subtract C from B. Eventually A and (BC) / as output
m is obtained. Substituting this into (3), the pulse interval T
_{Get PP} .

[0011]

The conversion in the analog-digital converter (A / D converter) 88 is a problem. When the fractional time is T _e (e = 1, 2), this is represented by a straight line having an intercept t _b and an inclination 1 / m as shown in FIG. Letting the output of the A / D converter be X, T _e = (X / m) + t _b (4). m must be constant. This is because it is a proportional constant and is also included in the equation (3) that gives the result.

However, this is difficult to keep constant. Intercept t of FIG.
_b and the slope m change with temperature. The integrating circuit is composed of an operational amplifier, a resistor, a capacitor, etc., as shown in FIG.
The value of the resistor varies depending on the element, and the value of the capacitor varies even more drastically. Therefore, m must be set to a predetermined value by measuring the exact value of the resistor and the capacitor in advance and adjusting the conversion ratio of the A / D converter.

Not only that. In the circuit of the previous example, it is also proportional to the output Q = 1 voltage of the flip-flop 82. Although this is a high level voltage of the output, the allowable range is of course determined, but this range is wide. Even in an element with a power supply of 5V, the range of high output has a variation of several hundred mV to 1V.
m must be a predetermined constant value. For this purpose, it is necessary to measure the output high level range for each element and adjust the conversion ratio of the A / D converter so as to match the range. In this way, adjustment is necessary during production. Even if the initial adjustment at the time of manufacture is possible, there are temperature fluctuations. The values of high-level voltage of resistors, capacitors, and flip-flops change with temperature. Then, the conversion ratio m changes.

[0014]

The time interval measuring device of the present invention is a device for measuring the time interval from the rising edge to the rising edge or from the falling edge to the falling edge of the first and second pulses. A clock generator for generating a clock pulse having a constant period T _CL, a counter for counting the number A of clock pulses included from the input of the first pulse to the input of the second pulse, and the first and second pulses. A triangular wave generating circuit that generates a triangular wave at the time of input, an analog-digital converter that performs analog-digital conversion of the output voltage of the triangular wave generating circuit at a certain ratio m, and when the first clock is input after the first and second pulses are input. A conversion start signal generation circuit that instructs the analog-to-digital converter to convert the output voltage of the triangular wave generation circuit into a digital signal, and a fixed interval is known And a distance known pulse generator for generating a pulse, first pulse, the digital converted signal of the triangular wave generated by the second pulse B, Examples C first, the pulse interval T _PP of the second pulse, T _PP = AT _CL +
And it is determined by the (B-C) / m, by entering the spacing known pulse W _k by known fractional time D _k (B-
It is characterized in that the divisor m of C) is corrected.

FIG. 1 is a schematic configuration diagram of the circuit for _{obtaining the} above T _PP . There is a pulse generator 1 of known interval, which can be input to the ogate 2. The pulse to be measured whose interval is unknown is input to the ogate 2 from another terminal. The unknown interval pulse and the interval known pulse are similarly guided to the clock terminal of the first flip-flop 3 by the ogate 2. The triangular wave generator 4 receives the output of the ogate 2 and generates a triangular wave having a voltage proportional to time. The Q output of the first flip-flop 5 is connected to the D input of the second flip-flop 5. The clock pulse generation circuit 6 generates a clock pulse having a constant frequency. This enters the clock terminal of the flip-flop 5 and one terminal of the AND gate 8.

The output of the AND gate 8 is connected to the counter 10. The Q output of the second flip-flop rises with the first pulse and falls with the second pulse. Counter 1
Zero eventually counts the number of clock pulses contained between the first and second pulses. The triangular wave generating circuit 4 is connected to the analog-digital converter 7. The Q output of the flip-flop 5 gives the conversion start signal generation circuit 9 conversion timing. This timing is when the first clock is input to the flip-flop 5 after the first and second pulses are input. In other words, it is T ₁ , T ₂ after the triangular wave starts to be generated.

At this timing, the analog-digital converter 7 converts the output voltage of the triangular wave generating circuit into a digital value. The value at the time of the first pulse is B, and the value at the time of the second pulse is C. As outputs, A, B, and C are obtained. From these, the pulse interval T _PP is calculated by the formula T _PP = AT _CL + (B−C) / m.

Although the triangular wave generating circuit is an integrating circuit after all,
This magnification m is not always a fixed value. In the present invention, this can be corrected. That is, the conversion magnification m of the analog-digital converter is corrected by the input of the pulse having the known interval. This is a feature. There are two means to correct the magnification m. One is to directly correct the proportional constant or the analog-digital converter constant that determines the relationship between the input and output of the triangular wave generation circuit. The other is not, but a method of correcting the divisor when dividing the output of the analog-digital converter.

Any of these may be used. In the former case, the divisor m can be directly corrected by changing the resistance of the integrating circuit, changing the capacitance of the capacitor of the integrating circuit, or changing the control variable of the analog-digital converter. In the latter case, the output of the divisor m should be divided without correcting the integration circuit or analog-digital converter.
To change. This will be described in more detail.

A pulse with a known interval is input to this circuit. This is two test pulses and their spacing W _k is known. This is similar to the spacing unknown pulses to be measured interval T _PP, becomes more and an integer multiple of the components NT _CL clock pulse T _CL, a fractional time D _k. That is, W _k
= NT _CL + D _k . The fractional time is the difference between the fractional time T _1k of the first pulse and the fractional time T _2k of the second pulse (T _1k −
T _2k ).

[0021] However, since the interval known pulse for correction Unlike the unknown pulse, the fractional time instead of _{T 1, T 2, T 1k} , to be written as T _2k. The number of clock pulses is N instead of A. The pulse interval is also W _k instead of T _PP
Is written. k is a number given to a pulse with a known interval. This may be a set of pulses or a plurality of sets of pulses with different pulse intervals. Let B _{k be} the output of the analog-digital converter in the fractional time of the first pulse, and C _k be the output of the analog-digital converter in the fractional time of the second pulse. These can be measured immediately.

The total pulse width W _k is known, and T _CL is also fixed. The outputs B _k , C _k of the analog-to-digital converter in the fractional times T ₁ , T ₂ are also known. Divisor m from these
Can be confirmed. This makes it possible to adjust the value of the divisor m with respect to the output of the analog-digital converter in the measurement of the pulse with unknown interval.

[0023]

With respect to the unknown interval pulse, the number A of clock pulses included in the wide pulse from the input of the first pulse to the input of the second pulse is counted to input the first and second pulses. A triangular wave is generated from time, and the voltage of the triangular wave when the first clock pulse is input is converted into a digital value by an analog-digital converter with a magnification of m, and these are B and C.
Then, the pulse interval T _PP is obtained by AT _CL + (B−C) / m. Since the divisor m varies with temperature depending on the element, the divisor m is adjusted using a set of test pulses with known intervals. This is the feature of the present invention. A method of adjusting m with a set of known test pulses is described.

FIG. 2 shows the test pulse. Let W _k be the known time interval of the test pulse. This is a constant given in advance. The quotient obtained by dividing this by the clock cycle T _CL is n, and the remainder is E _k . Naturally, 0 <E _k <T _CL . W _k with which can be written as _{W k = nT CL + E k} (5). Here, the meaning of n is slightly different from that of N used so far. E _k also has a slightly different meaning than D _k . N is defined by the following equation regardless of the magnitude of T _2k and T _1k .

W _k = NT _CL + (T _1k −T _2k ) (6) This means that the second term on the right side may be positive or negative. Figure 2
Indicates two cases. (A) shows the case where the second term on the right side is positive. That is, the fractional time of the first pulse is longer than the fractional time of the second pulse. Since the second term is positive, N = n and E _k = D _k . _{W k = nT CL + E k} = NT CL + D k = NT CL + (T 1k -T 2k) (7)

(B) shows the case where the second term on the right side is negative. That is, the fractional time of the first pulse is shorter than the fractional time of the second pulse. Since the second term is negative, N-1 = n, D
_k + T _CL = E _k . Since D _k is negative between -T _CL ~0, positively the remainder E _k by adding the T _CL. Instead, one clock T _CL is subtracted from the first term. _{W k = nT CL + E k} = (N-1) T CL + (D k + T CL) (8)

It is important to note that in this equation, n and E _k
Is a fixed constant. As a result of measuring the fractional time, B _k and C _k are obtained. Since the test pulse and the clock pulse are not synchronized, B _k and C _k are not predetermined. That is, B _k and C _k are random variables. However, these differences should be almost fixed in advance. This is because if these differences are divided by the divisor m, D _k should be _obtained .

However, this is not always the case because the divisor m may deviate from the optimum value. When the optimum value is M, a _{(B k -C k) / M} = D k (9). This always holds. If M = m, the expression in which M in (9) is replaced by the current divisor m is also established. But m
If is deviated from the optimum value M, it must be adjusted to return it to M. There are a method of internally adjusting by changing the conversion constant of the integrating circuit and the analog-digital converter, and a method of correctly determining the divisor to be divided by the output of the analog-digital converter. Both will be explained.

[Method] Adjustment of internal variables (1) If B _k > C _k , the constant E _k = D _k . And, the value obtained from the measurement (B _k -C _k) is compared with / m. (A) which if if _{(B k -C k) / m} > E k is the m is too small. Therefore, the constant of the integrating circuit or the analog-digital converter is adjusted to increase the magnification m and bring it closer to the optimum value M. (B) On the contrary, if (B _k −C _k ) / m <E _k , this means that m is too large. The constant m of the integrating circuit or the analog-digital converter is adjusted to reduce the magnification m so that it approaches the optimum value M.

(2) If B _k ≤C _k , the constant E _k = D _k
+ T _CL . This is compared with T _CL + (B _k −C _k ) / m obtained by adding T _CL to the value obtained from the measurement. (A) If T _CL + (B _k −C _k ) / m <E _k , this means that m is too small. Therefore, the constant of the integrating circuit or the analog-digital converter is adjusted to increase the magnification m and bring it closer to the optimum value M. (B) On the contrary, if (B _k −C _k ) / m> E _k , this means that m is too large. The constant m of the integrating circuit or the analog-digital converter is adjusted to reduce the magnification m and bring it closer to the optimum value M.

[Method] Adjustment of external variables (1) If B _k ≧ C _k , the constant E _k = D _k . This has a relationship with the optimum value M of the divisor and the expression (9). From this, the optimum value M can be obtained. M = (B _k −C _k ) / D _k (10). During normal measurement, the difference between the outputs B and C of the analog-digital converter is calculated, and this is divided by the divisor M to calculate the pulse interval, and the above M is used as the constant at this time.
Instead of (3), T _PP = AT _CL + (B−C) T _CL / M (11). m is replaced by the optimum value M found at the input of the test pulse. Do not adjust the constants of the integrator circuit as they are. The divisor for the output of the analog-digital converter is replaced with the optimum value M.

Since the calibration is performed by using the pulse having the known interval, it is not necessary to adjust the intermediate circuit constant. If (10) is rewritten only by the value known by the input of the test pulse and the constant given in advance, then T _PP = AT _CL + (B−C) T _CL D _k / (B _k −C _k ) (12)

(2) If B _k <C _k , the constant E _k = D _k
+ T _CL . By adding T _CL to the equation (9), there is a relation of E _k = D _k + T _CL = (B _k −C _k ) / M + T _CL (13). From this, the optimum value M can be obtained. M is _{= (C k -B k) /} (T CL -E k) (14). This is only different from (10). After the same, the difference between B and C of the output of the analog-digital converter is calculated during normal measurement, and this is divided by the divisor M as shown in (11).
The pulse interval is obtained by dividing by, and M of (14) is used as a constant at this time. In any case, the constant m of the integrating circuit or the like is left unchanged and is not adjusted. Replace the divisor for the output of the analog-to-digital converter with (10) or (14).

Accurate pulse intervals can be obtained by either the method of changing the internal variable or the method of changing the external variable. However, since the temperature changes constantly occur, the above-mentioned adjustment must be frequently performed. Further, the number of pulses with known intervals may be one set or plural. It is possible to calibrate even with one set.
A set of known spaced pulses are input to the apparatus of the present invention at regular intervals or at any time to perform magnification calibration. For example, calibration is performed using known pulses at intervals of 1 hour.

The accuracy of the calibration does not deteriorate just because the number of sets is one. As taught by probability theory, calibration accuracy can be improved by repeatedly calibrating a set of known pulses. If there are one set of pulses with known intervals,
There is only one such as W _k , n, D _k . However, when inputting this and obtaining the fractional time, B _k and C _k are obtained, but these take any number between 0 and T _CL . Since these are different, the accuracy is improved by repeatedly inputting this known interval pulse to the apparatus of the present invention and repeating the calibration.

It is also possible to use multiple sets of known spaced pulses. This is because the suffix k is added to indicate this, and it is also applicable to the case where there are a plurality of sets of known pulse intervals. FIG. 4 shows the fractional time D _k and the outputs B _k and C _k of the analog-digital converter when the interval known pulse W _k (k = 1 to 3) of 3 is used. These are measurements in which a pulse with a known interval is input many times and the measurement is repeated.

The case of k = 1 is represented by a black circle, the case of k = 2 is represented by a white circle, and the case of k = 3 is represented by a triangle. Only two (B _k −C _k ) values are determined for each. Positive and negative values. B _k and C _k themselves take different values each time they are input, but the difference becomes constant. The difference between the positive value and the negative value is T _CL .

There is another point that must be pointed out in this graph. It is the difference of fractional time (B _k −
Stability for C _k ). The proportionality constant is m described above. Six points are shown in this figure. This has 6 measurements
It doesn't mean times. It means that many measurements are almost the same, although they are measured many times.
Moreover, these measurement points are on a straight line, and the inclination is 1 / M. However, at the time of actual calibration, not all measurement points are exactly on one straight line due to errors in the integration circuit and the analog-digital converter. But,
A straight line that minimizes the error may be approximated by using the least squares method from many measurement point data.

[0039]

FIG. 5 shows an example of a circuit according to an embodiment of the present invention. The numbers are attached corresponding to FIG. Ogate 2 is for inputting a pulse with a known interval and a pulse with an unknown interval. The first flip-flop has the inverting output -Q connected to the D input. The output of the above-mentioned gate enters the clock terminal of the flip-flop 3. This flip-flop is such that the value of D appears at the Q output when the clock is applied. Therefore, in the first flip-flop 3, the output Q rises with the first pulse and the output Q falls with the second pulse.
This is for producing a time interval as shown in FIG. 9 (c).

The output Q of this is input to the D input of the second flip-flop 5. The second flip-flop 5 is for producing a clock pulse included between the first and second pulses. The clock of the clock pulse generation circuit 6 is connected to the clock input terminal of this flip-flop.
The output Q of the second flip-flop passes through the AND gate 8 and enters the counter 10. A clock is input to the AND gate 8 via the delay element 21. The delay element 21 gives the propagation delay time of the flip-flop.

The counter 10 eventually counts the number A of clocks included between the first pulse and the second pulse. This corresponds to (d) of FIG. The output Q of the first flip-flop 3 enters the one input terminal of the AND gate 24 through the delay element 22. The inverted output -Q of the flip-flop is input to the other terminal. The inverted output -Q passes through the delay element 23 and enters one input terminal of the AND gate 25. The output Q enters the other input terminal of the AND gate 25.

The delay elements 22, 23, the AND gate 24,
Reference numeral 25, the o'clock gate 26, and the integrating circuit 27 correspond to the triangular wave generating circuit 4. The delay element gives a delay of one clock cycle. The integrator circuit 27 starts integration with the oaget signal and produces an output proportional to time. That is, a triangular wave is generated. This means the triangular wave of FIG. 9 (f). The reason why there are two delay elements and two gates is that the same operation is performed for both positive and negative pulses.

The output of the second flip-flop 5 is similar. One of the output Q and the inverted output -Q is directly input to the AND gates 30 and 31 via the delay element of the other. This is logically ORed with the oaget 32. This measures the timing from the input of the first and second pulses to the input of the clock pulse to the clock terminal of the second flip-flop. When a clock pulse is input, the analog-digital converter 7 is instructed to convert the output of the integration circuit 27 into an analog-digital signal. The digital conversion is set to be m times the main pulse A. Thus for the first pulse the signal B
And the signal C is obtained for the second pulse. This circuit diagram does not include a correction circuit for the divisor m. As described above, m can be corrected after the outputs A, B and C are obtained, or can be directly changed by changing the constant of the integrating circuit.

The pulse with a known interval can be generated by the circuit shown in FIG. 6, for example. A series body of switch 40 and resistor 41 is connected between the power supply _Vcc and the ground. The D input of the flip-flop 42 is connected to this connection point. The clock pulse generation circuit 44 is connected to the clock input of the flip-flop 42. This clock is different from the clock shown in FIG. The pulse widths are different and they are not synchronized. The Q output of the flip-flop 42 and the signal passed through the clock delay element 43 are input to the AND gate 45. The delay element 43 has a delay time corresponding to the propagation delay of the flip-flop. The second flip-flop 46 has the inverting output −Q and the D input connected to each other. The output is inverted every time a signal is applied to the clock input. It is a double frequency divider. The inverting output −Q passes through the delay element 47 and enters the clock input of the flip-flop 48. Its D input is tied to the power supply voltage. The inverted output -Q enters one terminal of the AND gate 49. The output of the AND gate 45 is connected to the other terminal of the AND gate 49. The flip-flops 42, 46 and 48 can be reset all at once.

A waveform diagram of each part of the circuit shown in FIG. 6 is shown in FIG. 10, and the operation will be described. Upon reset, all flip-flops have a Q output of 0 and a -Q output of 1. First, when the switch 40 is closed, the D input of the flip-flop 42 goes up to 1. This is the waveform in FIG. Next, when the clock pulse shown in FIG. 10B enters the clock input, the Q output rises to 1 after the propagation delay time of td. This is the waveform of FIG. 10 (d). The delay element 43 is shown in FIG.
As shown in (c), the clock pulse is delayed by the time td. Since the Q output of the flip-flop 42 and the output of the delay element 43 are input to the AND gate 45, the AND gate output is as shown in FIG. The delay element 43 functions so that the pulse width of the first pulse of the AND gate output does not become narrow. In FIG. 10, the delay of the AND gate is neglected.

The output of the AND gate 45 is input to the flip-flop 46 which is a frequency divider, and its -Q output is as shown in FIG. The delay element 47 gives a delay of about 1/2 cycle of the clock pulse and less than 1 cycle. This is the waveform shown in FIG. Since the D input of flip-flop 48 is fixed at _Vcc , the -Q output drops to 0 at the rising edge of the clock input. This is shown in FIG. Since the inputs of the AND gate 49 are the output of the AND gate 45 (FIG. 10 (e)) and the Q output of the flip-flop 48 (FIG. 10 (h)), their outputs are as shown in FIG. 10 (i). It becomes 2 consecutive pulses. The delay element 47 works so that the second pulse width does not become narrow. The circuit shown here uses the clock as it is as pulses with known intervals. However, the known interval pulse can be generated by various circuits other than this.

The integrating circuit can be formed by the circuit shown in FIG. This is one in which the non-inverting input of the operational amplifier 50 is grounded, the inverting input and the output are connected by a capacitor, and a signal is input to the inverting input via the resistor 51. When the resistance value is R and the capacitor capacity is C, the current between the inverting input and the output is V _in / R, and the output voltage is integrated ∫ (V _in / CR) d
Since it is t, it functions as an integrating circuit.

[0048]

According to the present invention, a triangular wave is generated from the input of the first pulse and the second pulse to the input of the first clock, and this is analog-digital converted to measure the fractional time. According to the present invention, it is possible to accurately measure a time interval less than one clock pulse cycle. The constant interval pulse can be used to correct the constant of the integrating circuit or the scaling factor of the analog-digital converter. Even if there is a change in magnification due to temperature, this can be easily corrected. Also, the adjustment work time for manufacturing and shipping can be shortened. Great practical effect.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing a pulse interval measuring device of the present invention.

FIG. 2 is a waveform chart showing an example of the magnitude of a fractional time when a test pulse is input in the circuit of the present invention. (A) has T ₁ > T ₂ ,
(B) shows the case where T ₁ <T ₂ .

FIG. 3 shows the relationship between the fractional time and the output of the analog-digital converter when the integration circuit is operated and the output of the integration circuit is converted into a digital value by the analog-digital converter in the fractional time from the pulse rising to the first clock. Graph.

FIG. 4 is a graph showing a relationship between a difference between outputs B and C of an analog-digital converter and a fractional time.

FIG. 5 is a circuit diagram of a pulse time interval measuring circuit according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of known interval pulses.

FIG. 7 is a circuit diagram showing an example of an integrating circuit.

FIG. 8 is a circuit diagram of a pulse interval measuring device disclosed in JP-A-60-225027.

FIG. 9 is a waveform diagram showing voltage waveforms at various portions in the circuit of Japanese Patent Laid-Open No. 60-225027.

10 is a waveform diagram showing voltage waveforms at various portions in the circuit of FIG.

[Explanation of symbols]

 1 Interval Known Pulse Generator 2 Ogate 3 Flip Flop 4 Triangular Wave Generation Circuit 5 Flip Flop 6 Clock Pulse Generation Circuit 7 Analog-to-Digital Converter 8 And Gate 9 Conversion Start Signal Generation Circuit 10 Counter

Claims (1)

[Claims] 1. A device for measuring a time interval from a rising edge to a rising edge or a falling edge to a falling edge of a first pulse and a second pulse, the clock generating a clock pulse having a constant period T _CL. A generator, a counter for counting the number A of clock pulses included from the time of inputting the first pulse to the time of inputting the second pulse, and a triangular wave generation circuit for generating a triangular wave at the input of the first and second pulses,
An analog-digital converter for analog-digital converting the output voltage of the triangular wave generating circuit at a certain ratio m, and converting the output voltage of the triangular wave generating circuit into a digital signal when the first clock is input after the first and second pulses are input. A conversion start signal generation circuit for instructing the analog-digital converter to perform the above, and a known interval pulse generator for generating a known interval pulse at a constant interval. The triangular wave generated by the first pulse and the second pulse is digitally converted. Assuming that the signals are B and C, the pulse interval T _PP of the first and second pulses is T _PP = AT
_CL + (B−C) / m is used, and the interval known pulse W _k is input and the known fractional time D _k is _calculated as (B
A time interval measuring device characterized by correcting the divisor m of -C).