JPH05322987A - Inspection method for electronic device - Google Patents

Abstract

PURPOSE:To make transmission and reception of data unnecessary with using a special external terminal part, a switching device for communication buss and the protocol of internal communication buss in an electronic device in inspecting an integrated circuit constituting the electronic device by using a boundary scan method. CONSTITUTION:An inspection device 5 sets a microcomputer COM in boundary scan mode by way of external buss interface 3 and then transmit tests data. The microcomputer COM transmits the test data to an integrated circuit IC1 and receives tests data from an integrated circuit IC2. The microcomputer COM then transmits the test data received from the integrated circuit IC2 to the inspection device and the inspection device 5 inspects the received test data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting a connection state of input / output terminals of a plurality of integrated circuits which constitute an electronic device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 7, an integrated circuit has a data parallel input terminal PI and a data parallel output terminal PO.
And a serial interface SIF for serial communication with a microcomputer or another IC. The serial interface SIF is provided with a data serial input terminal SI, a data serial output terminal SO, a communication clock terminal SCK, and a chip select terminal CS for selecting a communication partner. In an actual integrated circuit, the parallel input terminals PI and the parallel output terminals PO are not always regularly arranged in this way, and some integrated circuits also have terminals that serve as input and output. In addition, some integrated circuits do not have the parallel input terminal PI. However, the above description is given to simplify the explanation.

When connecting a plurality of integrated circuits having such a structure, the parallel output terminal PO of the first integrated circuit ICA is connected to the parallel input terminal PI of the second integrated circuit ICB as shown in FIG. Serial interface S
The serial input terminal SI, serial output terminal SO, and clock terminal SCK of the IF are commonly connected to each integrated circuit ICA and ICB. In addition, each integrated circuit ICA and I
The chip select terminals CS of the CB are separately connected from a control microcomputer (hereinafter referred to as a microcomputer) COM, and the other party to communicate with is the chip select terminal C.
By selecting with S, it is configured to perform time division communication.

By the way, when transmitting and receiving data by connecting this kind of integrated circuit, it is necessary to inspect whether or not the parallel input terminal PI and the parallel output terminal PO of each integrated circuit are surely connected. .. In particular, when a large number of integrated circuits are arranged at a high density on a substrate with a limited area, the wiring process becomes complicated, which makes it more difficult to reliably inspect the connection state of the wiring. there were.

As one method for solving this problem, a so-called boundary scan (Boundary scan) is used.
-Scan: Hereinafter, an inspection method called B / S is considered (IEEE Std 1149.1-).
1990). That is, as shown in FIG. 9, the integrated circuit IC11 of this type has a configuration in which a parallel input terminal PI and a parallel output terminal PO for data and a serial interface SIF for performing serial communication are added to the B / S.
It has a test interface TIF for.

The test interface TIF inputs a test serial input terminal TSI for serially inputting test data from the outside, a test serial output terminal TSO for serially outputting the input test data, and a clock for processing test data. A test clock input terminal TCK and a test mode select terminal TMS for inputting a command to set the integrated circuit IC11 in a test mode.
Have and.

As shown in FIG. 10, the inside of the integrated circuit IC11 corresponds to each of the input terminals PI1 to PI4 of the parallel input terminal PI between the parallel input terminal PI and the function logic FLG for executing predetermined data processing. B / S cells BC1 to BC4 are provided. Also,
B / S cells BC5 to BC8 are provided between the parallel output terminal PO and the function logic FLG that executes predetermined data processing, corresponding to the output terminals PO5 to PO8 of the parallel output terminal PO. The test clock input terminal TCK and the test mode select terminal TM
S is omitted.

FIG. 11 is a block diagram showing an example of the configuration of the B / S cell. FIG. 11A is a block diagram of the B / S cells BC1 to BC of FIG.
4 is an input cell corresponding to 4 and (b) is a B / S cell B in FIG.
It is an output cell corresponding to C5 to BC8. FIG. 11 (a)
In, the data input from the input terminal PIi (i is an integer from 1 to 4 in FIG. 10) is sent to the function logic (FLG) and the first input of the multiplexer MUX. The output data of the preceding stage is input to the second input of the multiplexer MUX (if this B / S cell corresponds to BC1, the input data to the test serial input terminal TSI, BC2
To BC4, the output data of BC1 to BC3) are input. When the multiplexer MUX is set to the test mode, the input terminal PIi
D flip-flop D-FF
To the D flip-flop D-FF when "SHIFT DR" is input.
Output to. Then, in this state, the D flip-flop D
-If the clock signal CLOCK DR is sent to FF,
The output of the D flip-flop D-FF is transferred to the B / S cell of the next stage.

Next, in FIG. 11B, the data input from the function logic (FLG) is input to the first input of the multiplexer MUX. Further, the data input from the B / S cell in the previous stage is input to the second input of the multiplexer MUX via the D flip-flop D-FF. The multiplexer MUX sends the output of the D flip-flop D-FF to the output terminal POj (j is an integer from 5 to 8 in FIG. 10) when set in the test mode, and the function logic (FLG) in the normal mode.
The data input from is output to the output terminal POj. D
The output of the flip-flop D-FF is the next stage (when this B / S cell corresponds to BC8, the test serial output terminal T
B / S cell BC when SO, BC5 to BC7
6 to BC8).

Although not shown, the integrated circuit IC11 shown in FIG. 10 receives a "SHIFT DR" or a circuit for generating a clock signal CLOCK DR and sending it to each B / S cell, and an input from the serial interface SIF in the normal mode. A normal signal processing circuit is provided for processing the processed data and performing mode setting, parameter setting, etc. of the function logic FLG.

The integrated circuit IC11 configured as described above
Performs the following operations in test mode. (1) 4 input from the test serial input terminal TSI
After the bit serial data is temporarily stored in the B / S cells BC1 to BC4, it is transferred to the B / S cells BC5 to BC8 based on the clock signal CLOCK DR and further output from the test serial output terminal TSO. (2) The 4-bit data input in parallel from the input terminals PI1 to PI4 is temporarily stored in the B / S cells BC1 to BC4 and then transferred to the B / S cells BC5 to BC8 based on the clock signal CLOCK DR. , And outputs as serial data via the test serial output terminal TSO. (3) 4 input from the test serial input terminal TSI
The bit serial data is once stored in the B / S cells BC1 to BC4, then transferred to the B / S cells BC5 to BC8 based on the clock signal CLOCK DR, and further output as parallel data from the corresponding output terminals PO5 to PO8. To do.

In this way, the test interface TIF
And integrated circuit IC1 having B / S cells BC1 to BC8
The integrated circuits IC12 to IC14 having the same configuration as the first integrated circuit IC11 are connected as shown in FIG.
The test data TD, which is 4-bit serial data for testing, is input to the test serial input terminal TSI.
This test data TD is B / B provided on the parallel output terminal PO side of the integrated circuit IC11 shown in FIG.
It is stored in the S cells BC5 to BC8, and is further output from the parallel output terminal PO to the input terminal PI of the second integrated circuit IC12 that follows.

The test data TD input to the parallel input terminal PI of the second integrated circuit IC12 is the B / S cell (B in FIG. 10) provided corresponding to the parallel input terminal PI of the second integrated circuit IC12. / S cells BC1 to BC4) and further transferred to the B / S cells (similar to B / S cells BC5 to BC8 in FIG. 10) corresponding to the parallel output terminal PO of the integrated circuit IC12, and the test serial output. It is output from the terminal TSO. Hereinafter, similarly, in the integrated circuits IC13 and IC14, the test serial input terminal TSI and the test serial output terminal T are respectively provided.
Input and output via SO.

In this way, by outputting the test data TD through the parallel signal line between the parallel input terminal PI of the integrated circuit IC11 and the parallel output terminal PO of the integrated circuit IC12, for example, "1111" as the test data TD. Is input, if there is disconnection or connection failure in the parallel signal line between the parallel output terminal PO of the integrated circuit IC11 and the parallel input terminal PI of the integrated circuit IC12, the test serial output terminal TSO of the second integrated circuit IC12. In the serial data output from, only the data corresponding to the defective portion becomes "0".
It is output as data such as "1".

Therefore, the connection states of the first integrated circuit IC11 and the second integrated circuit IC12 can be inspected based on this output data. In an actual integrated circuit, for example, the IC 11 and the IC 13 may be connected, or the output of the IC 12 may be input to the IC 11. However, in order to simplify the description, they are connected regularly. The case is shown.

FIG. 13 is a block diagram showing the configuration of a conventional electronic device inspection system. Here, parts corresponding to those in FIGS. 9 and 10 are denoted by the same reference numerals. Camera integrated V
An electronic device 20 such as a TR has two integrated circuits IC21 and IC22 provided on one substrate.
The parallel output terminal PO of 21 and the parallel input terminal PI of the integrated circuit IC22 are connected to each other, and are configured to send and receive data between the two integrated circuits IC21 and IC22. The serial interface SIF of each of the integrated circuits IC21 and IC22 is the selector 2
3. Connected to the microcomputer COM via the internal communication bus 24, the microcomputer COM and the integrated circuits IC21, IC2
It is configured to perform serial communication between the two.

In the electronic device 20 configured as described above, the external terminal portion 25 is connected to the selector 23, and when the select terminal SEL is controlled to the "H" level, the selector 23 is set as shown in FIG. As shown by the broken line, the microcomputer COM is switched to the external terminal section 25 side. Further, an inspection device 27 is connected to the external terminal portion 25 via a first bidirectional communication bus 26,
The inspection device 27 is configured to transmit various control data to the external terminal portion 25, and directly transmit / receive test data to / from the internal communication bus 24 of the electronic device 20 via the external terminal portion 25. ing.

Further, an external bus interface 28 is connected to the microcomputer COM, and the external bus interface 28 is connected to the external communication bus (second bidirectional communication bus) 2.
An inspection device 27 is connected via 9. The external communication bus 29 is conventionally used for remote control of the electronic device 20, transmission / reception of data used for mode setting, parameter setting, etc. of the integrated circuits IC21 and IC22. Here, the inspection device 27 tests the microcomputer COM. It is used to let you know that you are doing. As the external bus interface 28 and the external communication bus 29, for example, a LANC (Local Applic) proposed by the present applicant is used.
application control bus system (registered trademark). Details of the LANC are described in, for example, Japanese Patent Application Laid-Open No. 61-147687, and will not be described here.

In FIG. 13, when the inspection device 27 controls the select terminal SEL of the external terminal section 25 to the "H" level, the selector 23 switches from the microcomputer COM to the external terminal section 25 side as shown by the broken line. In this state, the test serial output terminal T of the external terminal section 25
SO, a test serial input terminal TSI, and a test clock terminal TCK are serial input terminals SI, serial output terminals SO, and clock input terminals SC of the serial interfaces SIF of the integrated circuits IC21 and IC22, respectively.
Connected to K.

At this time, the chip select terminal CSA of the external terminal section 25 is connected to the chip select terminal CS of the integrated circuit IC21, and the chip select terminal CSB of the external terminal section 25 is connected to the chip select terminal CS of the integrated circuit IC22. Connected. Using these two chip select terminals CSA and CSB, integrated circuits IC21 and IC
By operating the circuits 22 separately, data is not simultaneously output from the serial output terminals SO of the integrated circuits IC21 and IC22 on the internal communication bus 24 connected to the serial interface.

Here, the test mode select terminal TMS of the external terminal section 25 is connected to the test mode select terminals TMS of the integrated circuits IC21 and IC22, and the integrated circuits IC21 and IC22 according to the logic level of the test mode select terminal TMS. Is configured to be in test mode. In this test mode, the test data input to the serial input terminal SI of the integrated circuit IC21 is transferred from the B / S cells BC1 to BC4 (not shown) to the B / S cells BC5 to BC8, and from the parallel output terminal PO. Parallel input terminal PI of integrated circuit IC22
Sent to. The test data input to the parallel input terminal PI of the integrated circuit IC22 is the B / S cell BC.
1 to BC4 to B / S cells BC5 to BC8 (not shown)
And is output from the serial output terminal SO.

In this inspection system, the integrated circuit IC21
And without providing the test interface TIF in the IC 22,
Test data is input from the serial interface SIF. Therefore, the data input from the serial interface SIF in the normal mode is sent to the normal signal processing circuit, and the serial interface SIF is output in the test mode.
Although a switching circuit is required to send the data input from the B / S cell to the B / S cell, the test interface TIF is omitted, so that the structure of the integrated circuit is simplified.

[0023]

However, in the conventional electronic device inspection system described above, the external inspection device directly transmits the test data to the internal communication bus of the electronic device to be inspected by the first bidirectional communication bus. Therefore, a dedicated external terminal unit is required and data must be transmitted and received by the protocol of the internal communication bus. If there are a plurality of electronic devices, an internal communication bus switching device is required.

Further, since the external inspection device needs to notify the microcomputer of the test by the external communication bus to prevent the microcomputer from malfunctioning during the inspection, transmission / reception by the protocol of the external communication bus is also possible. It must be made. The present invention solves the above problems and provides an inspection method for an electronic device that does not require a dedicated external terminal unit and a communication bus switching device, and that does not require data transmission / reception according to an internal communication bus protocol. The purpose is to

[0025]

In order to solve the above problems, the present invention provides a microcomputer, a plurality of integrated circuits for transmitting and receiving data to and from the microcomputer via an internal communication bus, and an external bus interface of the microcomputer. In a method of inspecting a connection state of input / output terminals of a plurality of integrated circuits in an electronic device provided with a B / S method, the inspecting device instructs a microcomputer to set a test mode via an external bus interface. A step of transmitting a command and test data, a step of transmitting test data by a microcomputer to a predetermined integrated circuit, a step of receiving the test data by the microcomputer from an integrated circuit connected to the integrated circuit, Testing the test data received from the circuit.

Further, in the present invention according to the above invention, the test data received from the integrated circuit is further inspected by an inspection device.

[0027]

According to the present invention, since the method for inspecting the electronic device is configured as described above, the external inspecting device can inspect the electronic device through the microcomputer incorporated in the electronic device. Therefore, a dedicated external terminal unit and a communication bus switching device are unnecessary, so that the inspection device can be simplified and the number of parts of the electronic device can be reduced.

Further, since the test data is inspected by the inspection device, even if the integrated circuit is changed, it can be dealt with only by changing the command or B / S data transmitted by the inspection device.

[0029]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an electronic device inspection system according to an embodiment of the present invention.
An electronic device 1 such as a camera-integrated VTR is provided with a plurality of integrated circuits on one substrate.
Only 3 is shown. The parallel output terminal PO of the integrated circuit IC1 and the parallel input terminal PI of the integrated circuit IC2 are connected, and the parallel output terminal PO of the integrated circuit IC2 and the parallel input terminal PI of the integrated circuit IC3 are connected,
It is configured to transmit and receive data between these IC1 to IC3. The serial interface SIF of each of the integrated circuits IC1 to IC3 is the internal communication bus 2
Is connected to the microcomputer COM via the
It is configured to perform serial communication between the OM and the integrated circuits IC1 to IC3.

In the electronic device 1 configured as described above, the microcomputer COM is connected to the inspection device 5 via the external bus interface 3 and the external communication bus 4. The external bus interface 3 and the external communication bus 4 are used for remote control of the electronic device 1, mode setting of the integrated circuits IC1 to IC3, parameter setting, etc., such as LANC described in the conventional example. Here, the inspection device 5 is used. Sends and receives test data and commands to and from the microcomputer COM.

FIG. 2 is a block diagram of data sent to the microcomputer COM by the inspection device in the embodiment of the present invention.
It is composed of an IC designating command for designating an integrated circuit for writing S data, a data length of B / S data to be written in a B / S cell of the integrated circuit, a B / S data and a B / S mode setting command. FIG. 3 is a block diagram of the RAM of the microcomputer according to the embodiment of the present invention, in which a command area CA for storing the B / S mode setting command, the B / S data length and the IC designation command shown in FIG. It has an output data area DA1 for storing B / S data output to the integrated circuit and an input data area DA2 for storing B / S data input from the integrated circuit.

FIG. 4 is a flow chart of the inspection procedure in the embodiment of the present invention, and FIGS. 5 and 6 are explanatory views showing the state of the integrated circuit in each step of FIG. Here, the arrangement of the B / S cells of the integrated circuits IC1 to IC3 of FIG. 4 is the same as that of FIG. Hereinafter, with reference to FIGS. 1 to 6, an integrated circuit IC
A procedure for sequentially inspecting the connection state of the parallel output terminal PO of 1 and the parallel input terminal PI of the integrated circuit IC2 and the connection state of the parallel output terminal PO of the integrated circuit IC2 and the parallel input terminal PI of the integrated circuit IC3 will be described.

First, the inspection device 5 connects the microcomputer COM to the B / B via the external communication bus 4 and the external bus interface 3.
Set to S mode. When the microcomputer COM enters the B / S mode, it stops normal operation. Further, the test mode select terminal TMS is set to "H" to set the integrated circuits IC1 to IC3 in the test mode. Then, the B / S mode setting command standby state is set.

Next, the inspection device 5 is connected to the microcomputer COM as shown in FIG.
Send the data shown in. Upon receiving the data, the microcomputer COM receives the IC designation command, the B / S data length and the B
/ S mode setting command in RAM command area CA
And the B / S data is stored in the output data area DA1 (step S1 in FIG. 4). Here, the B / S data is data P1 = “11” for setting the test data “1111” at the parallel output terminal PO of the integrated circuit IC1.
110000 ”, and the IC designation command is the integrated circuit I.
The B / S mode setting command is a command for designating C1, and sends the B / S data stored in the output data area DA1 to the integrated circuit and stores the data read from the integrated circuit in the input data area DA2. Is a command to instruct. At this time, the data stored in the normal mode remains in the integrated circuits IC1 to IC3 (marked with * in FIG. 5A).

Next, the microcomputer COM is in the command area C.
The integrated circuit IC1 is selected by reading the IC designation command stored in A and setting the chip select terminal CSA to the “H” level. Then, the data "11110000" is read from the output data area DA1 of the RAM and sent to the serial input terminal SI of the integrated circuit IC1. At this time, the data "*********" is read from the serial output terminal SO of the integrated circuit IC1 and stored in the input data area DA2 of the microcomputer COM (step S in FIG. 4).
2). The input data “11110000” is shown in FIG.
As shown in (b), the test data “1111” that is the first 4 bits B is connected to the parallel output terminal PO.
Since the data is stored in the / S cells BC8 to BC5, the test data "1111" appears at the parallel output terminal PO. Since the latter half 4-bit data “0000” is not used for the test, any pattern other than this may be used. When the output to the serial input terminal SI is completed, the chip select terminal CS
Set A to "L" level. The integrated circuit IC1 is controlled in the hold mode by setting the chip select terminal CSA to the "L" level. In this mode the integrated circuit IC1
Does not change, and the data of the parallel output terminal PO holds the test data “1111”.

Next, the inspection device 5 is connected to the microcomputer COM as shown in FIG.
Send the data shown in. Upon receiving the data, the microcomputer COM stores each data in the command area CA or the output data area DA1 as in step S1 (step S3 in FIG. 4). Here, the B / S data is data P2 = “1111” for setting the test data “1111” in the parallel output terminal PO of the integrated circuit IC2.
0000 "and the IC designation command is the integrated circuit IC2.
Is a command that specifies. At this time, test data P2
May be overwritten on the test data P1 stored in the output data area DA1 in step S1 or may be stored in another address of the output data area DA1. In this embodiment, the data is overwritten to save the RAM.

Next, the microcomputer COM reads the IC designation command and sets the chip select terminal CSB to the "H" level to select the integrated circuit IC2. Then, at the parallel input terminal PI of the integrated circuit IC2, the test data “111” of the parallel output terminal PO of the integrated circuit IC1 is output.
1 ”is captured (step S4 in FIG. 4, FIG. 5C).

Then, the data "11110000" is input to the serial input terminal SI of the integrated circuit IC2. At this time, the data "*** 1111" is read from the serial output terminal SO of the integrated circuit IC2 and stored in the input data area DA2 of the microcomputer COM (step S of FIG. 4).
5, FIG. 6 (a). That is, in this step, the data P1 for inspecting the connection state of the parallel output terminal PO of the integrated circuit IC1 and the parallel input terminal PI of the integrated circuit IC2, the parallel output terminal PO of the integrated circuit IC2, and the parallel input terminal PI of the integrated circuit IC3 are read. Writing of the data P2 for inspecting the connection state of is simultaneously performed. Next, the integrated circuit IC2 is placed in the hold mode by setting the chip select terminal CSB to the "L" level.

Input data area DA2 of the microcomputer COM
By comparing the latter 4 bits of the data "*** 1111" stored in the first half of the data "1110000" stored in the data area in step S1 with the parallel output terminal PO of the integrated circuit IC1. The connection state of the parallel input terminal PI of the integrated circuit IC2 is inspected (step S6 in FIG. 4). This comparison is a microcomputer COM
May be performed by the inspection device 5, but the microcomputer CO
When the configuration is performed by M, the program of the microcomputer COM must be changed when the configuration of the integrated circuit is changed, whereas when the comparison is performed by the inspection device 5, the content of the input data area DA is changed to the external bus interface. Since it is read into the inspection device 5 through 3, it can be dealt with only by changing the program of the inspection device 5.

Next, the inspection device 5 is connected to the microcomputer COM as shown in FIG.
Send the data shown in. Upon receiving the data, the microcomputer COM stores each data in the command area CA and the output data area DA1 (step S7 in FIG. 4).
Here, the B / S data is data P3 = "111111" for setting the test data "1111" in the parallel output terminal PO of the integrated circuit IC3, and the IC designation command is a command that designates the integrated circuit IC3.

Next, the microcomputer COM reads the IC designation command and sets the chip select terminal CSC to the "H" level to select the integrated circuit IC3. Then, at the parallel input terminal PI of the integrated circuit IC3, the test data “111” of the parallel output terminal PO of the integrated circuit IC2 is output.
1 ”is captured (step S8 in FIG. 4, FIG. 6B).

Then, the data P3 = "1110000" is input to the serial input terminal SI of the integrated circuit IC3. At this time, the data "*** 1111" is read from the serial output terminal SO of the integrated circuit IC3, and the microcomputer C
The data is stored in the input data area DA2 of the OM (step S9 in FIG. 4, FIG. 5C). That is, here as well as in step S5, reading of the data P2 for inspecting the connection state of the parallel output terminal PO of the integrated circuit IC2 and the parallel input terminal PI of the integrated circuit IC3, the parallel output terminal PO of the integrated circuit IC2 and the integrated circuit IC4, for example. Data P3 for inspecting the connection state of the parallel input terminal PI (not shown)
Are written simultaneously.

Input data area DA2 of the microcomputer COM
By comparing the last 4 bits of the data "*** 1111" stored in the first half with the first 4 bits of the data "1110000" stored in the data area in step S3, the parallel output terminal PO of the integrated circuit IC2 The connection state of the parallel input terminal PI of the integrated circuit IC3 is inspected (step S10 in FIG. 4).

Thereafter, the tests are performed in the same manner as IC4, IC5, ... Then, the test data “1111”
When the test using the
The above-mentioned test mode is repeated with "0". As a result,
First, the test data “1111” and “0000” input to the integrated circuits IC1 to IC3 and the like and the integrated circuits IC1 to
A comparison result with the data output from the serial output terminal SO of the IC3 or the like can be obtained, and if there is a difference in the comparison result, it can be understood that there is an abnormality such as a connection failure in the signal line corresponding to the difference data.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention. For example, the B / S mode in which the inspection device instructs the microcomputer not to store the data unnecessary for the test (such as "*********" read from the integrated circuit in step S2) in the data area. A setting command may be sent. Also, the output data area and the input data area may be shared.

[0046]

As described above in detail, according to the present invention, the following effects can be obtained. (1) Since the dedicated external terminal unit and the switching device for the internal communication bus are not required, the inspection device can be simplified and the number of parts of the electronic device can be reduced. (2) When the electronic device is viewed from the inspection device, data is exchanged in the data area (RAM) in the virtual space of the microcomputer.
Therefore, it is not necessary to be aware of the internal structure of the electronic device. (3) The inspection device need only support the protocol of the external communication bus. (4) Since the inspection device is configured to inspect the test data, even if the integrated circuit is changed, it can be dealt with by only changing the command or B / S data transmitted by the inspection device. Therefore, it is not necessary to change the program of the microcomputer of the electronic device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an electronic device inspection system according to an embodiment of the present invention.

FIG. 2 is an embodiment of the present invention, the inspection device is a microcomputer C
It is a block diagram of the data transmitted to OM.

FIG. 3 is a configuration diagram of a RAM of a microcomputer according to an embodiment of the present invention.

FIG. 4 is a flow chart of an inspection procedure in the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a state of the integrated circuit in each step of FIG.

FIG. 6 is an explanatory diagram showing a state of the integrated circuit in each step of FIG.

FIG. 7 is an explanatory diagram showing a configuration of an integrated circuit.

FIG. 8 is a connection diagram showing a connection state of a plurality of integrated circuits and a microcomputer.

FIG. 9 is an explanatory diagram showing a configuration of a conventional B / S integrated circuit.

FIG. 10 is an explanatory diagram showing an internal configuration of a conventional B / S integrated circuit.

FIG. 11 is a block diagram showing a configuration of a conventional B / S cell.

FIG. 12 is an explanatory diagram when performing B / S on a plurality of integrated circuits.

FIG. 13 is a block diagram showing a configuration of a conventional electronic device inspection system.

[Explanation of symbols]

 1 Electronic Device 2 Internal Communication Bus 3 External Bus Interface 4 External Communication Bus 5 Inspection Device COM Microcomputer IC1 to IC3 Integrated Circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shinji Takada 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (2)

[Claims] 1. A plurality of integrated circuits in an electronic device comprising a microcomputer, a plurality of integrated circuits for transmitting and receiving data to and from the microcomputer via an internal communication bus, and an external bus interface of the microcomputer. In a method of inspecting a connection state of an input / output terminal by using a boundary scan method, (a) an inspection device transmits a command and a test data for instructing the microcomputer to set a test mode via the external bus interface. And (b) the microcomputer transmits the test data to a predetermined integrated circuit, and (c) the microcomputer outputs the test data from the integrated circuit connected to the integrated circuit. Receiving (d) said collection And a step of inspecting the test data received from the product circuit. 2. The inspection method for an electronic device according to claim 1, wherein the inspection device inspects the test data received from the integrated circuit.