JPH05322933A - Waveform sampling apparatus - Google Patents

Abstract

PURPOSE:To generate a plurality of sampling pulses by one triggering and to perform a plurality of samplings by constituting a sampling-pulse generating circuit of a synchronous oscillator, which is oscillated in synchronization with a trigger and a counter for counting the oscillated signals. CONSTITUTION:A trigger circuit 1 outputs a trigger signal based on a trigger input (a). A synchronous oscillator 2 is oscillated in synchronization with the trigger signal and outputs a time-measuring clock signal. A starting-point counter 3 uses the data from an adder 5 as the initial value, counts the clock signal from the oscillator 2 so as to determine the time for sampling the first point with respect to the trigger signal and outputs the signal as the carry signal. A periodic-point counter A counts the clock signal from the oscillator 2 based on the carry signal from the counter 3 and outputs the carry signal at every preset value. The carry signals from the counters 3 and A are added in an AND circuit 12. The result is used as the sampling pulses, and the measured inputs are sampled and held in an S/H circuit 13. A/D conversion is performed with an ADC 14, and the result is stored in a memory 15 at the timing of the signal from a delay circuit 21. Thus, a plurality of samplings are performed by one triggering.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform sampling device, and more particularly to improvement of a time axis circuit when an input frequency is high.

[0002]

2. Description of the Related Art Sampling methods when the input frequency is faster than the sampling pulse in the waveform sampling circuit include sequential sampling and random sampling. Comparing the two, random sampling is superior in terms of measurement speed, but sequential sampling is superior in terms of repetitive waveform measurement accuracy. The present invention intends to speed up the measurement by a simpler method while maintaining the superiority of the accuracy of the sequential sampling. Therefore, the conventional sequential sampling method and its problems will be described below. Due to the processing time, circuit configuration, etc., it is impossible to perform a sufficient number of samplings to form a waveform from a single trigger signal due to the processing time or circuit configuration. There are cases where In such a case, for a high-frequency signal, the waveform is formed by sequentially sampling from the trigger point using the periodicity of the waveform and replacing it with the equivalent time, that is, a minute time from the trigger point. Sequential sampling is used which forms a waveform while shifting. In conventional sequential sampling, it is difficult to perform multiple sampling for one trigger due to the configuration of the time axis correction circuit that outputs sampling pulses while shifting a minute time from the trigger, and thus only one point is sampled for one trigger. It is often the case. Further, as an example of implementing a time axis circuit capable of performing a plurality of samplings for one trigger, there is a time axis circuit configured to sequentially skew a sampling clock synchronized with a trigger input.

[0003]

Therefore, since one sample is used for one trigger, the same number of samples as the number of samples are required to obtain a sufficient number of samples to form a waveform. It takes longer to complete minute sampling. For example, in the case of an oscilloscope or the like, there is a drawback that the waveform update becomes slow. Also,
In the conventional configuration of the time axis circuit capable of performing a plurality of samplings for one trigger, there is a problem that the circuit configuration becomes complicated because the method of sequentially skewing the sampling clocks is used. It is an object of the present invention to solve such a problem and to realize a waveform sampling device having a simple configuration and capable of sampling a plurality of data with one trigger signal in a sequential sampling method.

[0004]

According to the present invention, a trigger circuit which receives a trigger input and outputs a trigger signal in synchronism with the trigger input when in a trigger waiting state, and in synchronism with the input from the trigger circuit are provided. A synchronous oscillator that starts oscillation and outputs a time measurement clock signal, a control circuit that controls data transfer and a trigger wait state or the whole, and a first point for the trigger signal set by the control circuit. Is added to the initial value of the sampling time and the output from the integrator to be described later, and the data from the adder is used as the initial value, and the time measurement clock signal from the synchronous oscillator is counted. Determine the time to sample the first point for the trigger signal,
A start point counter that outputs as a carry signal and a carry signal of the start point counter are input as an operation prohibition release signal, the time measurement clock signal from the synchronous oscillator is counted, and the value set by the control circuit is set. A cycle point counter that outputs a carry signal for each time, a number counter that counts the carry signal from the cycle point counter and outputs a carry signal for each value set by the control circuit, and a control circuit by the control circuit. The set value is used as the incrementing number, the carry signal from the number counter is added each time it is input, and an integrator that outputs to the adder, the carry signal from the start point counter, and the periodic point are added. An AND circuit that ORs the carry signals from the counter and the value set from the control circuit And the number of the increment,
Each time a carry signal from the start point counter is input, it is added and output, a cycle counter for counting carry signals from the number counter, and an integrated value from the start number integrator A second adder for adding the count value from the cycle counter, a delay circuit for outputting a signal obtained by delaying the output signal from the AND circuit by a time required for sample hold or analog / digital conversion, and A sample hold circuit for sampling and holding the measurement input signal using the output signal from the AND circuit as a sampling pulse, an analog / digital converter for converting the analog output from the sample hold circuit into a digital signal, and the second adder The output is used as an address, and the analog signal is output at the timing of the signal from the delay circuit. A memory is provided for storing a digital signal which is output from the digital converter, a waveform sampling device and performing sequential sampling capable of capturing a plurality of data in a single trigger signal.

[0005]

Since a plurality of sampling pulses are generated for one trigger by using a sampling pulse generating circuit composed of a startable oscillator that oscillates in synchronization with the trigger and a counter that counts it, one trigger is generated. On the other hand, it becomes possible to perform a plurality of samplings.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a basic configuration diagram of the present invention. In the figure, reference numeral 1 denotes a trigger circuit, which receives a trigger input and outputs a trigger signal synchronized with the trigger input when in a trigger waiting state. The synchronous oscillator 2 starts oscillation in synchronization with the input from the trigger circuit and outputs a time measurement clock signal. 3 is a start point counter, which uses the data from the adder 5 as an initial value, counts the time measurement clock signal from the synchronous oscillator 2 and determines the time at which the first point is sampled with respect to the trigger signal. Output as rising signal. The adder 5 adds the initial value of the time at which the first point is sampled to the trigger signal set by the control circuit 18 and the output from the integrator described later and outputs the result. An AND circuit 12 takes the logical sum of the carry signal from the start point counter and the carry signal from the periodic point counter. Reference numeral 13 denotes a sample hold circuit (hereinafter referred to as S / H circuit), which uses the output signal of the AND circuit 12 as a sampling pulse to sample and hold the measurement input signal. 14
Is an analog / digital converter (hereinafter referred to as ADC)
The analog output from the S / H circuit 13 is converted into a digital signal. Reference numeral 15 is a memory, which uses the output from the adder 23 as an address and at the timing of the signal from the delay circuit 21,
It stores the digital signal that is the output from the ADC. The delay circuit 21 outputs a signal obtained by delaying the output signal from the AND circuit 12 by the time required for sample hold or analog / digital conversion. Reference numeral 16 denotes a memory address generation circuit, which inputs a carry signal from the start point counter 3, a control signal from the control circuit 18, and a carry signal from the frequency counter B, generates a signal as an address in the memory 15, and outputs it. To do. The memory address generating circuit 16 is composed of a start number accumulator 20, an adder 23, and a cycle counter C. Reference numeral 18 denotes a control circuit which controls data transfer and a trigger waiting state or the whole. The start number integrator 20 sets the value set by the control circuit as the increment number, and adds the carry signal from the start point counter each time it is input, and outputs it. Cycle counter C
Counts the carry signal from the frequency counter.
The adder 23 adds the integrated value from the start number integrator 20 and the count value from the cycle counter C to the memory 1
A signal which becomes an address at 5 is generated and output. A is a periodic point counter, which inputs the carry signal of the start point counter 3 as an operation prohibition release signal, counts the time measurement clock signal from the synchronous oscillator 2, and
A carry signal is output for each value set from 8. B is a counter, which counts the carry signal from the periodic point counter A and outputs a carry signal for each value set by the control circuit 18. I is an integrator, which sets the value set by the control circuit 18 as the incrementing number, adds the carry signal from the frequency counter B every time it is input, and outputs the sum to the adder 5.

In the conventional sequential sampling, only a counter (corresponding to the starting point counter 3 in FIG. 1) for determining how late the sampling should be performed with respect to the trigger input is provided. ,
In this configuration, a counter (corresponding to the periodic point counter A in FIG. 1) is provided for effecting how often the sampling is performed for one trigger input. Therefore, with respect to the trigger input, the first sampling pulse is output from the start point counter 3, and the second and subsequent sampling pulses are output from the periodic point counter A, so that sampling is performed a plurality of times with one trigger input. ..

FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, the same parts as those in FIG.
Reference numeral 4 is a register for storing the initial value of the delay from the control circuit 18 for the start point counter 3. The output of the register 4 and the output of the integrator I are added by the adder 5. 6, 8 are counters, 7, 9, 11 are registers, 1
0 is an incrementer. A periodic point counter A is composed of the counter 6 and the register 7. The counter 8 and the register 9 constitute a frequency counter B. The incrementer 10 and the register 11 constitute an integrator I.

FIG. 3 shows a specific configuration of the memory address generation circuit 16, in which 19 is a register and 20 is an incrementer. The value stored in the register 19 is integrated in synchronization with the sampling timing, and the adder 2
Since the data indicating how many times the trigger has occurred is added in 3, it is possible to generate an address corresponding to the time at each sampling point.

A description will be given of such an embodiment. Basically, it is similar to FIG. 1, and FIG. 2 is a diagram in which a register for storing a value such as an initial value in counting is added to FIG.
The trigger circuit 1 outputs in synchronization with a trigger input in a trigger waiting state. This signal causes the synchronous oscillator 2 (so-called startable oscillator) to start oscillating. At this time, the control circuit 18 stores the initial value of the delay in the register 4, the initial value of the periodic point counter A for counting the sampling interval in the register 7, and the register 9 performs the sampling several times with one trigger. The initial value of the number of times counter B that counts whether it has been performed is stored, the register 11 stores the number of increments to be accumulated by the incrementer 10, and the register 19 stores the value stored in the register 7 in the register 11. Stored is the value divided by the specified value. The start point counter 3 (so-called delay counter) counts the number of clocks of the output signal of the synchronous oscillator 2 to determine the time to sample the first point with respect to the trigger. The sampling pulse is output to the counter 6 and the AND circuit 12 at the determined time. Counter 6
The (counter that is the basis of the periodic point counter A) starts counting the clocks from the synchronous oscillator 2 by the sampling pulse from the start point counter 3 and carries a carry signal (so-called carry signal) every predetermined number of times. )
Is output. The counter 8 (the counter that is the basis of the frequency counter B) counts the carry signal output from the counter 6. This makes it possible to know how many times sampling is currently performed for one trigger input. Further, when the count for the value defined by the register 9 is completed, a carry signal (so-called carry signal) is output to the incrementer 10. The incrementer 10 integrates the current number of triggers, and outputs a value corresponding to the number of triggers to the adder 5. Therefore, sequential sampling is executed by slightly shifting the generation time of the sampling pulse with respect to the trigger input.

The operation in such a configuration will be described in detail with reference to the time chart shown in FIG. In the figure a
2 to f show temporal changes in the operation of each point shown in FIG. It should be noted that the upper parts a to f in FIG. 4 show the changes to the first trigger input, and the lower parts a to f show the changes to the second trigger input. Reference numeral a is a trigger ready (TRIG READY) signal output from the control circuit 18 which determines whether the trigger circuit 1 is in the trigger waiting state. b is a trigger signal output from the trigger circuit 1, and the trigger circuit 1 is in a trigger waiting state (the trigger ready signal a is at H level)
And when there is an external trigger input, H
It will be a level. c is a clock signal output from the synchronous oscillator 2. d is a sampling pulse output from the start point counter 3. e is a sampling pulse output from the periodic point counter A. f is a signal output from the frequency counter B, which is a sampling end signal indicating that all samplings for one trigger input have been completed. Also S11, S1
2 to S16 are data sampled by the first trigger input, and S21 and S22 to S26 are data sampled by the second trigger input.

As a preparation before starting the measurement, each register (4, 7, 9, 11, 19) of the control circuit 18
Store the data in. The trigger ready (TRIG READY) signal is kept at the L level until this sequence is completed. The value input to each register will be described.
Register 4 has a trigger point (rising edge of trigger signal a)
From this, the data at which position to start sampling is stored. For example, the sampling pulse d in the upper part of FIG. 4 is output at the third rising edge of the clock signal c. As understood from this, the initial value of the delay amount stored in the register 4 is 2. Register 7
Stores a value that defines the interval of the sampling pulse e. For example, the sampling pulse e in the upper part of FIG. 4 is output at every fourth rising edge of the clock signal c after the sampling pulse d is generated. As can be understood from this, the value of the period stored in this register 7 is 3. The register 9 stores how many times sampling is performed for one trigger input. This stored value is the number of pulses generated for one trigger input in the sampling pulse e. The register 11 stores the deviation of the delay amount for each trigger input. Figure 4
A comparison between the upper sampling pulse d and the lower sampling pulse d shows that the rising edge of the clock signal c is deviated by one pulse. In order to shift by one pulse, 1 is stored in the register 11. Register 1
As described above, 9 stores a value obtained by dividing the period value 3 stored in the register 7 by 1 stored in the register 11, that is, 3.

The operation will be specifically described. When the trigger ready (TRIG READY) signal becomes H level, the trigger circuit 1 enters the trigger waiting state, and when there is a trigger input, the trigger signal a rises. When the trigger signal a becomes H level, the synchronous oscillator 2 starts oscillating, and the clock signal c
Is output. The start point counter 3 outputs a carry signal when counting the initial value 2 of the delay amount stored in the register 4. This corresponds to the sampling pulse d. At the rising edge of the sampling pulse d, the counter 6 starts counting the clock signal c.
Therefore, the sampling pulse e is output every three cycles of the clock signal c. The counter 8 (counter within the number counter B) counts the sampling pulse e,
When a pulse corresponding to the value stored in the register 9 arrives, a carry signal is output. This signal is shown in FIG. 4 as the sampling end signal f.

In the incrementer 10, the value stored in the register 11 for one minute is integrated for each sampling end signal f. The sampling end signal f is output to the control circuit 18 as an end signal. further,
Load to the start point counter 3 via the OR circuit 17 (LOA
D) Input as a signal. At the same time, the integrated value 1 is output from the incrementer 10 and added to the value 2 stored in the register 4 by the adder 5. Therefore, in the state where the next trigger signal a shown in the lower part of FIG. The sampling pulse d is generated at the fourth rise of the clock signal c from the rise of the trigger signal. By performing such sampling, a large number of samplings can be performed with a small number of trigger inputs, and the efficiency of measurement is improved. Because it is sequential sampling,
Order of time difference from the time of trigger input (S1 shown in FIG. 4
1, S21. ． S12, S22. ． ), It is necessary to store the sampling data digitized by the ADC 14 in the memory 15. The circuit for this purpose is the configuration of the address generation circuit 16 shown in FIG.

A time chart showing the operation of the address generation circuit 16 will be described with reference to FIG. 5, which shows an address generation method for storing sampling data in the memory 15 in order of time difference from the time when a trigger is input. First, in the incrementer 20 shown in FIG. 3, a write signal g for writing data to the memory 15 for each sampling is used as a clock input, a sampling end signal f is used as a reset input, and the integrated value is the value of the register 19. Is.
Therefore, as shown in FIG. 5, the output DI of the incrementer 20 is integrated for each sampling pulse d and sampling pulse e. Since 0 is added in the adder 23 in the first trigger, the address AD becomes equal to DI, and S11, S12. ． The sampling data shown in is stored. Since the counter 22 uses the sampling end signal f as a clock input, the address DA output from the integrator 23 is incremented by 1 in the adder 23 at the second trigger, and S21 and S22 are added to the address AD in the memory 15. ． ． The sampling data shown in is stored. By the above operation, the sampling data is stored in the memory 15 in order of the time difference from the time when the trigger is input.

[0016]

As described in detail above, the present invention can realize a waveform sampling apparatus capable of performing high-speed sequential sampling.

[Brief description of drawings]

FIG. 1 is a configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a partial configuration diagram of an embodiment of the present invention.

FIG. 4 is an explanatory diagram of the operation of the present invention.

FIG. 5 is an explanatory diagram of the operation of the present invention.

[Explanation of symbols]

 1 Trigger Circuit 2 Synchronous Oscillator Circuit 3 Start Point Counter 12 AND Circuit 13 Sample-Hold Circuit 14 Analog / Digital Converter 15 Memory 16 Memory Address Generation Circuit 18 Control Circuit 20 Start Count Integrator 21 Delay Circuit 23 Second Adder A Cycle point counter B Number of times counter C Cycle counter

Claims (1)

[Claims] 1. A trigger circuit that receives a trigger input and outputs a trigger signal synchronized with the trigger input when the trigger is in a waiting state; and a time measurement clock that starts oscillation in synchronization with the input from the trigger circuit. A synchronous oscillator that outputs a signal, a control circuit that controls the data transfer and the trigger wait state or the whole, and an initial value of the time when the first point is sampled for the trigger signal set by the control circuit. An adder for adding and outputting outputs from an integrator to be described later, and data from the adder as an initial value, counting the time measurement clock signal from the synchronous oscillator and counting the first point with respect to the trigger signal. A start point counter that determines the time at which the eyes are sampled and outputs as a carry signal, and the carry signal of the start point counter A period point counter that inputs a signal, counts the time measurement clock signal from the synchronous oscillator, and outputs a carry signal for each value set from the control circuit; and a carry signal from the period point counter. Count,
A counter that outputs a carry signal for each value set by the control circuit, and a value that is set by the control circuit as an increment number, and is added each time a carry signal is input from the counter. In addition, an integrator that outputs to the adder, an AND circuit that performs a logical sum of the carry signal from the start point counter and the carry signal from the periodic point counter, and the value set by the control circuit The number of carry signals from the start-point counter, and the number-of-starts integrator that outputs the carry signal each time the counter is input; a cycle counter that counts carry signals from the number-of-times counter; A second adder for adding the integrated value from the counter and the count value from the cycle counter; A delay circuit that outputs a signal delayed by a time required for sample-holding or analog / digital conversion of the output signal of, and a sample-hold circuit that samples and holds the measurement input signal by using the output signal from the AND circuit as a sampling pulse An analog / digital converter for converting an analog output from the sample hold circuit into a digital signal, and an output from the second adder as an address, and the analog / digital converter at a timing of a signal from the delay circuit. And a memory for storing a digital signal which is an output from the device, and performing sequential sampling capable of capturing a plurality of data with one trigger signal.