JPH0531828B2 - - Google Patents

Info

Publication number
JPH0531828B2
JPH0531828B2 JP61240006A JP24000686A JPH0531828B2 JP H0531828 B2 JPH0531828 B2 JP H0531828B2 JP 61240006 A JP61240006 A JP 61240006A JP 24000686 A JP24000686 A JP 24000686A JP H0531828 B2 JPH0531828 B2 JP H0531828B2
Authority
JP
Japan
Prior art keywords
anisotropic conductive
conductive film
film
semiconductor chips
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61240006A
Other languages
Japanese (ja)
Other versions
JPS6394661A (en
Inventor
Akiteru Rai
Takashi Nukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP61240006A priority Critical patent/JPS6394661A/en
Publication of JPS6394661A publication Critical patent/JPS6394661A/en
Publication of JPH0531828B2 publication Critical patent/JPH0531828B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PURPOSE:To obtain a new hybrid type three-dimensional IC which realizes high density electrical connection by a method wherein semiconductor chips are provide on both surfaces of an anisotropic conductive film and the semiconductor chips are connected to each other through stripe wirings in the anisotropic conductive film. CONSTITUTION:In an anisotropic conductive film 2, stripe wirings 3 are formed vertically to the surface of the film 2 and independently from each other. Semiconductor chips 4a and 4b have required number of connection electrodes 5a and 5b at the respective corresponding positions. The semiconductor chips 4a and 4b are aligned while the connection electrodes 5a and 5b are facing the anisotropic conductive film 2 and are laminated on both the surfaces of the anisotropic conductive film 2 by thermocompression bonding or mechanical pressure. With this constitution, the respective corresponding connection electrodes 5a and 5b are connected to each other through the stripe wirings 3. Therefore, significant improvement of mounting density, improvement of operation speed owing to the reduction of wiring lengths and improvement of functional performance owing to combination of the chips whose functions, materials, manufacturing processes and so forth are different can be realized.

Description

【発明の詳細な説明】 <産業上の利用分野> この発明は、半導体チツプを積層した構造の半
導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a semiconductor device having a structure in which semiconductor chips are stacked.

<従来の技術> 集積回路(以下ICという)の集積度は急速度
で向上しており、今後も一層の高集積化が求めら
れるのは必然の動きである。しかし、微細加工技
術にも限界があるため、IC設計の基準寸法を変
えることなくICの高集積化と高性能化を可能と
するものとして、三次元ICが出現した。この三
次元ICは、一般にモノリシツクタイプとハイブ
リツドタイプに分けられる。前者は同一基板上に
SOI技術により半導体層を繰り返し形成するもの
であるが、まだ解決を要する課題が数多く残され
ている。
<Conventional Technology> The degree of integration of integrated circuits (hereinafter referred to as ICs) is increasing rapidly, and it is inevitable that even higher levels of integration will continue to be required. However, because microfabrication technology has its limits, three-dimensional ICs have emerged as a means of achieving higher integration and performance without changing the standard dimensions of IC design. These three-dimensional ICs are generally divided into monolithic types and hybrid types. The former is on the same board
Although SOI technology is used to repeatedly form semiconductor layers, there are still many issues that need to be resolved.

一方、後者は二次元ICを積み重ねるもので、
技術上の問題が少ないため実用化が比較的容易で
あり、2個のデバイスをフリツプチツプ方式で貼
り合わせたものが実用化されている。しかし、一
般のフリツプチツプ方式では、電極の接続ピツチ
は最小でも200μm程度が限界であり、素子レベ
ルの高密度な電極の接続は困難であつた。
On the other hand, the latter stacks two-dimensional ICs,
Since there are few technical problems, it is relatively easy to put it into practical use, and a device in which two devices are bonded together using a flip-chip method has been put into practical use. However, in the general flip-chip method, the electrode connection pitch is limited to a minimum of about 200 μm, making it difficult to connect electrodes at a high density at the element level.

<発明が解決しようとする問題点> この発明はこのような問題点に着目し、高密度
な電気的接続の可能な新しいハイブリツドタイプ
の三次元ICを提供することを目的としてなされ
たものである。
<Problems to be Solved by the Invention> This invention has been made with attention to these problems and the purpose of providing a new hybrid type three-dimensional IC capable of high-density electrical connection. .

<問題点を解決するための手段> 上述の目的を達成するために、この発明では、
絶縁性フイルム上に微細ピツチのストライプ配線
を形成し、このフイルムを複数層重ねて相互に接
着した後、ストライプ配線の方向に対して直角に
フイルム状に切断することによつて製造した異方
性導電フイルムの両面に、半導体チツプをその接
続用電極が異方性導電フイルムの面に向くように
位置合わせしてそれぞれ積層し、異方性導電フイ
ルムのストライプ配線を介して両面の半導体チツ
プ間を電気的に接続するようにしている。
<Means for solving the problems> In order to achieve the above-mentioned object, the present invention has the following steps:
Anisotropic film produced by forming striped wiring with fine pitch on an insulating film, stacking multiple layers of this film and adhering them to each other, and then cutting into films at right angles to the direction of the striped wiring. Semiconductor chips are stacked on both sides of the conductive film with their connection electrodes facing the surface of the anisotropic conductive film, and the semiconductor chips on both sides are connected via striped wiring of the anisotropic conductive film. I am trying to connect electrically.

<作用> 異方性導電フイルムの両面に積層された半導体
チツプは、その接続用電極の間が異方性導電フイ
ルムのストライプ配線を介して接続される。そし
てストライプ配線を微細なピツチで形成すること
は比較的容易であるので、接続用電極のピツチを
小さくすることが可能となり、半導体装置の高密
度化が実現される。
<Function> Semiconductor chips stacked on both sides of the anisotropic conductive film are connected between connecting electrodes via striped wiring of the anisotropic conductive film. Since it is relatively easy to form striped interconnections with fine pitches, it is possible to reduce the pitch of connection electrodes, and higher density semiconductor devices can be realized.

<実施例> 次に図示の実施例について説明する。<Example> Next, the illustrated embodiment will be described.

第1図にこの発明によるハイブリツドタイプの
三次元IC1の一実施例の断面図を示す。2は異
方性導電フイルム、3はこの異方性導電フイルム
2の内部にその面に直角な方向に互いに独立して
形成されている無数のストライプ配線、4a,4
bはそれぞれ対応する位置に所定の数だけの接続
用電極5a,5bを有する半導体チツプであり、
半導体チツプ4a,4bはその接続用電極5a,
5bを異方性導電フイルム2の面に向けて位置合
わせし、熱圧着や機械的な圧力を加えることによ
つて異方性導電フイルム2の両面にそれぞれ積層
されている。これにより、互いに対応する各接続
用電極5a,5bはストライプ配線3を介して相
互に接続されることになる。第2図は半導体チツ
プ4a,4bを積層する前の異方性導電フイルム
2の断面を示している。
FIG. 1 shows a sectional view of an embodiment of a hybrid type three-dimensional IC 1 according to the present invention. 2 is an anisotropic conductive film; 3 is an innumerable number of striped wirings formed independently from each other in a direction perpendicular to the surface of the anisotropic conductive film 2; 4a, 4;
b is a semiconductor chip having a predetermined number of connection electrodes 5a, 5b at corresponding positions,
The semiconductor chips 4a, 4b have connection electrodes 5a,
5b are aligned toward the surface of the anisotropic conductive film 2, and are laminated on both sides of the anisotropic conductive film 2 by thermocompression bonding or applying mechanical pressure. As a result, the corresponding connection electrodes 5a and 5b are connected to each other via the stripe wiring 3. FIG. 2 shows a cross section of the anisotropic conductive film 2 before the semiconductor chips 4a, 4b are laminated thereon.

第3図は別の実施例による三次元IC11の断
面図を示す。この実施例では、異方性導電フイル
ム2の表面の所定個所に配線6を形成し、これを
外部への導出用電極としたものであり、他の部分
は第1図のものと同様である。第4図は半導体チ
ツプ4a,4bを積層する前の異方性導電フイル
ム2の断面を示している。
FIG. 3 shows a cross-sectional view of a three-dimensional IC 11 according to another embodiment. In this embodiment, a wiring 6 is formed at a predetermined location on the surface of an anisotropic conductive film 2, and this is used as an electrode for leading to the outside, and other parts are the same as those in FIG. . FIG. 4 shows a cross section of the anisotropic conductive film 2 before the semiconductor chips 4a, 4b are laminated thereon.

上述のような構造において、異方性導電フイル
ム2の材料が熱可望性樹脂の場合には、熱圧着に
よつて両チツプ4a,4bは異方性導電フイルム
2の面に密着し、異方性導電フイルム2がチツプ
4a,4bに対する環境保護膜としても機能し、
信頼性の向上に大きく貢献する。また異方性導電
フイルム2が熱可塑性樹脂でない場合でも、機械
的な圧力を加え、あるいは必要に応じて接着剤を
併用することにより、チツプ4a,4bと異方性
導電フイルム2とは完全に接着される。
In the structure described above, when the material of the anisotropic conductive film 2 is a thermoplastic resin, both chips 4a and 4b are tightly attached to the surface of the anisotropic conductive film 2 by thermocompression bonding, and the anisotropic conductive film 2 is made of a thermoplastic resin. The directional conductive film 2 also functions as an environmental protection film for the chips 4a and 4b,
This greatly contributes to improving reliability. Even if the anisotropic conductive film 2 is not made of thermoplastic resin, the chips 4a, 4b and the anisotropic conductive film 2 can be completely separated by applying mechanical pressure or using an adhesive as necessary. Glued.

次に、三次元IC1あるいは11の形成に用い
られる異方性導電フイルム2について述べる。
Next, the anisotropic conductive film 2 used for forming the three-dimensional IC 1 or 11 will be described.

この異方性導電フイルム2に対応する従来技術
としては、第7図のaに示すシリコーンゴム21
中に金属細線22を埋め込んだ構造のもの、ある
いは、第7図のbに示す絶縁性ゴム23と導電性
ゴム24を層状に積み重ねた構造のもの等のエラ
ステイツクコネクタや、第7図cに示すような絶
縁性ゴム25に金属粒子26を分散させたホツト
プレスタイプの異方性導電フイルム等が開発され
ている。
As a conventional technique corresponding to this anisotropic conductive film 2, a silicone rubber 21 shown in FIG.
Elastic connectors have a structure in which thin metal wires 22 are embedded, or structures in which insulating rubber 23 and conductive rubber 24 are stacked in layers as shown in FIG. 7b, or as shown in FIG. 7c. A hot press type anisotropic conductive film, etc., in which metal particles 26 are dispersed in an insulating rubber 25 as shown, has been developed.

しかし、前者のエラステイツクコネクタの場合
は、接続ピツチは200μm程度が限界であり、後
者の異方性導電フイルムの場合でも、150μm程
度が限界であつて、いずれもより微細なピツチに
よる接続は困難である。また接続抵抗に関して
も、前者は接圧に大きく依存し、後者の場合もカ
ーボン繊維間の接触状態によつて大きく変化し
て、非常に不安定である。
However, in the case of the former elastic connector, the connection pitch is limited to about 200 μm, and even in the case of the latter anisotropic conductive film, the limit is about 150 μm, making it difficult to connect with a finer pitch. It is. Also, regarding the connection resistance, the former largely depends on the contact pressure, and the latter also varies greatly depending on the contact state between the carbon fibers and is extremely unstable.

これに対して、この発明における異方性導電フ
イルムは、熱可塑性あるいは熱硬化性の絶縁性フ
イルム上に十数μmから数十μmの微細ピツチの
ストライプ配線を形成し、このフイルムを複数層
重ねて相互に接着した後、ストライプ配線の方向
に対して直角にフイルム状に切断することによつ
て得られるのであり、高密度且つ安定した接続が
可能なものである。ここで絶縁性フイルムとして
熱可塑性樹脂を用いた場合には、形成された異方
性導電フイルムはホツトプレスタイプのコネクタ
となる。また熱可塑性樹脂の絶縁性フイルムを用
いた場合でも、フイルムを重ねる際に接着層を介
して熱圧着することにより、異方性導電フイルム
を製作することができる。また使用する配線材料
としては、Al、Au、Ti、Cu等の、フイルムとの
密着性がよいものなら特に限定されない。
On the other hand, the anisotropic conductive film of the present invention is produced by forming striped wiring with a fine pitch of tens of micrometers to several tens of micrometers on a thermoplastic or thermosetting insulating film, and stacking multiple layers of this film. After bonding them together, they are cut into a film at right angles to the direction of the striped wiring, allowing for high-density and stable connections. When thermoplastic resin is used as the insulating film, the anisotropic conductive film formed becomes a hot press type connector. Furthermore, even when an insulating film made of thermoplastic resin is used, an anisotropic conductive film can be produced by thermocompression bonding via an adhesive layer when overlapping the films. Further, the wiring material to be used is not particularly limited as long as it has good adhesion to the film, such as Al, Au, Ti, Cu, etc.

このような異方性導電フイルムの製造工程の一
例を第5図に示す。
An example of the manufacturing process of such an anisotropic conductive film is shown in FIG.

先ず、ガラス板14上にポリイミドをコーテイ
ングして半硬化状態とし、あるいは熱可塑性樹脂
をコーテイングして、厚さ数μm〜20μmの絶縁
性フイルム15を形成する[第5図a]。次いで、
2μm程度にAl膜を蒸着によつて形成し、フオト
リソ技術を使つて10μmピツチ程度のストライプ
配線16を形成する[第5図b]。次に、絶縁性
フイルム15をガラス板14から剥がし、第5図
cのようにストライプ配線16の方向を揃えて複
数層重ねて熱圧着する。そして、第5図dに示す
ようにストライプ配線16に直角な方向に厚さ
10μm〜数十μmのフイルム状に切断する。こう
して無数のストライプ配線16がフイルムの面に
直角な方向に規制正しく並んだ異方性導電フイル
ム2が得られるのである。尚、第5図dのストラ
イプ配線16は、第1図乃至第4図のストライプ
配線3に相当するものである。
First, polyimide is coated on the glass plate 14 to bring it into a semi-cured state, or thermoplastic resin is coated on the glass plate 14 to form an insulating film 15 having a thickness of several μm to 20 μm [FIG. 5a]. Then,
An Al film with a thickness of about 2 μm is formed by vapor deposition, and stripe wiring 16 with a pitch of about 10 μm is formed using photolithography [FIG. 5b]. Next, the insulating film 15 is peeled off from the glass plate 14, and as shown in FIG. 5c, a plurality of layers are stacked and thermocompressed with the striped wiring 16 aligned in the same direction. Then, as shown in FIG. 5d, the thickness is
Cut into films of 10 μm to several tens of μm. In this way, an anisotropic conductive film 2 in which countless striped wirings 16 are regularly arranged in a direction perpendicular to the surface of the film is obtained. Note that the stripe wiring 16 in FIG. 5d corresponds to the stripe wiring 3 in FIGS. 1 to 4.

第6図は絶縁性フイルムが熱硬化性の場合の例
であり、第5図aにおいて、ガラス板14上にコ
ーテイングしたポリイミドを硬化させて絶縁性フ
イルム15とし、これに2μm程度のAl膜を蒸着
によつて形成し、フオトリソ技術を使つて10μm
ピツチ程度のストライプ配線16を形成する[第
5図b]。これをガラス板14から剥がして第6
図aのようにストライプ配線16の方向を揃え、
接着層17と交互に複数層重ねて熱圧着する。そ
して、第6図bに示すようにストライプ配線16
に直角な方向に厚さ10μm〜数十μmのフイルム
状に切断する。これにより、無数のストライプ配
線16(すなわち3)がフイルムの面に直角な方
向に規則正しく並んだ異方性導電フイルム2が得
られるのである。
FIG. 6 shows an example in which the insulating film is thermosetting. In FIG. 5a, the polyimide coated on the glass plate 14 is cured to form the insulating film 15, and an Al film of about 2 μm is coated on this. Formed by vapor deposition and 10μm using photolithography technology
Stripe wiring 16 having a pitch of about 100 psi is formed [FIG. 5b]. Peel this off from the glass plate 14 and
Align the direction of the stripe wiring 16 as shown in figure a,
A plurality of layers are stacked alternately with adhesive layer 17 and bonded by thermocompression. Then, as shown in FIG. 6b, the stripe wiring 16
Cut the film into a film with a thickness of 10 μm to several tens of μm in a direction perpendicular to . As a result, an anisotropic conductive film 2 in which a countless number of striped wirings 16 (ie, 3) are regularly arranged in a direction perpendicular to the surface of the film is obtained.

尚、これらの実施例で用いられているガラス板
14は、絶縁性フイルム作成時の支持台の役割を
果たすものであり、必要がなければ用いなくても
よい。
Note that the glass plate 14 used in these Examples serves as a support during the production of the insulating film, and may not be used if unnecessary.

又、第1図及び第3図の実施例では、半導体チ
ツプ4a,4bは同一サイズとして説明している
が、この発明によれば、異なつたサイズのチツプ
を貼り合わせてハイブリツドタイプの三次元IC
を構成することももちろん可能である。
Furthermore, in the embodiments shown in FIGS. 1 and 3, the semiconductor chips 4a and 4b are described as having the same size, but according to the present invention, chips of different sizes are pasted together to form a hybrid type three-dimensional IC.
Of course, it is also possible to configure

<発明の効果> 上述の実施例から明らかなように、この発明
は、絶縁性フイルム上に微細ピツチのストライプ
配線を形成し、このフイルムを複数層重ねて相互
に接着した後、ストライプ配線の方向に対して直
角にフイルム状に切断することによつて製造した
異方性導電フイルムを用い、この異方性導電フイ
ルムの両面に半導体チツプを積層し、異方性導電
フイルムのストライプ配線を介して両面の半導体
チツプ間を電気的に接続するようにしたものであ
り、異方性導電フイルム内のストライプ配線を微
細なピツチで形成することが比較的容易であるの
で、接続用電極のピツチを小さくすることが可能
となり、半導体装置の高密度化が実現される。
<Effects of the Invention> As is clear from the above-described embodiments, the present invention involves forming striped wiring with fine pitches on an insulating film, stacking a plurality of layers of the film and adhering them to each other, and then changing the direction of the striped wiring. Using an anisotropic conductive film manufactured by cutting the anisotropic conductive film into a film shape at right angles to the It is designed to electrically connect semiconductor chips on both sides, and it is relatively easy to form striped wiring within the anisotropic conductive film at a fine pitch, so the pitch of the connecting electrodes can be made small. This makes it possible to achieve high density semiconductor devices.

従つて、この発明によれば、実装密度の飛躍的
な向上、配線長の短縮による動作速度の向上、機
能、材質、製造プロセス等の異なるチツプを組み
合わせることによる機能性の向上等、多くの効果
が期待されるのである。
Therefore, according to the present invention, many effects can be achieved, such as a dramatic improvement in packaging density, an improvement in operating speed by shortening the wiring length, and an improvement in functionality by combining chips with different functions, materials, manufacturing processes, etc. is expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例の断面図、第2
図は、同実施例に用いる異方性導電フイルムの断
面図、第3図は、他の実施例の断面図、第4図
は、同上実施例に用いる異方性導電フイルムの断
面図、第5図a乃至第5図dは、それぞれ異方性
導電フイルムの製造工程の一例を示す図、第6図
a及び第6図bは、それぞれ異方性導電フイルム
の製造工程の他の一例を示す図、第7図a乃至第
7図cは、それぞれこの発明の異方性導電フイル
ムに対応する従来例の断面図である。 1,11……三次元IC(半導体装置)、2……
異方性導電フイルム、3,16……ストライプ配
線、4a,4b……半導体チツプ、5a,5b…
…接続用電極、6……配線(導出用電極)、15
……絶縁性フイルム、17……接着層。
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG.
The figure is a sectional view of an anisotropic conductive film used in the same example, FIG. 3 is a sectional view of another example, and FIG. 4 is a sectional view of an anisotropic conductive film used in the same example. 5a to 5d each show an example of the manufacturing process of an anisotropic conductive film, and FIGS. 6a and 6b each show another example of the manufacturing process of an anisotropic conductive film. The figures shown in FIGS. 7a to 7c are sectional views of conventional examples corresponding to the anisotropic conductive film of the present invention, respectively. 1, 11... Three-dimensional IC (semiconductor device), 2...
Anisotropic conductive film, 3, 16...stripe wiring, 4a, 4b...semiconductor chip, 5a, 5b...
...Connection electrode, 6...Wiring (lead electrode), 15
...Insulating film, 17...Adhesive layer.

Claims (1)

【特許請求の範囲】 1 絶縁性フイルム上に微細ピツチのストライプ
配線を形成し、このフイルムを複数層重ねて相互
に接着した後、ストライプ配線の方向に対して直
角にフイルム状に切断することによつて製造した
異方性導電フイルムの両面に、半導体チツプをそ
の接続用電極が異方性導電フイルムの面に向くよ
うに位置合わせしてそれぞれ積層し、異方性導電
フイルムのストライプ配線を介して両面の半導体
チツプ間を電気的に接続したことを特徴とする半
導体装置。 2 異方性導電フイルムの表面に配線を形成し、
この配線を外部への導出用電極とした特許請求の
範囲第1項記載の半導体装置。 3 異方性導電フイルムが、絶縁性フイルムの熱
可塑性を利用して相互に熱圧着した後フイルム状
に切断して得られたものである特許請求の範囲第
1項または第2項記載の半導体装置。 4 異方性導電フイルムが、熱可塑性でない絶縁
性フイルムを接着層を介して相互に接着した後フ
イルム状に切断して得られたものである特許請求
の範囲第1項または第2項記載の半導体装置。
[Claims] 1. Stripe wiring with fine pitches is formed on an insulating film, multiple layers of this film are stacked and bonded to each other, and then the film is cut at right angles to the direction of the stripe wiring. Semiconductor chips are laminated on both sides of the anisotropic conductive film produced in this way, with their connection electrodes facing the surface of the anisotropic conductive film, and then the semiconductor chips are laminated on both sides of the anisotropic conductive film, and the semiconductor chips are laminated on both sides of the anisotropic conductive film. A semiconductor device characterized in that semiconductor chips on both sides are electrically connected. 2 Form wiring on the surface of the anisotropic conductive film,
2. The semiconductor device according to claim 1, wherein the wiring is an electrode for leading to the outside. 3. The semiconductor according to claim 1 or 2, wherein the anisotropic conductive film is obtained by thermocompression-bonding the insulating film to each other using thermoplasticity and then cutting it into a film shape. Device. 4. The anisotropic conductive film according to claim 1 or 2, wherein the anisotropic conductive film is obtained by adhering non-thermoplastic insulating films to each other via an adhesive layer and then cutting them into film shapes. Semiconductor equipment.
JP61240006A 1986-10-08 1986-10-08 Semiconductor device Granted JPS6394661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61240006A JPS6394661A (en) 1986-10-08 1986-10-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61240006A JPS6394661A (en) 1986-10-08 1986-10-08 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6394661A JPS6394661A (en) 1988-04-25
JPH0531828B2 true JPH0531828B2 (en) 1993-05-13

Family

ID=17053061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61240006A Granted JPS6394661A (en) 1986-10-08 1986-10-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6394661A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033217A1 (en) * 1997-01-24 1998-07-30 Rohm Co., Ltd. Semiconductor device and method for manufacturing thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998033217A1 (en) * 1997-01-24 1998-07-30 Rohm Co., Ltd. Semiconductor device and method for manufacturing thereof

Also Published As

Publication number Publication date
JPS6394661A (en) 1988-04-25

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