JPH05315577A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a logic circuit which is adequate in load drive capacity and minimal in power consumption by a method wherein a transient current, which is made to flow to discharge electric charge stored in a load capacitor at a fall time of output signal, is varied in intensity corresponding to the capacity of the load capacitor. CONSTITUTION:A differential logic circuit is composed of transistors T1 and T2 whose collectors are connected to a high power supply terminal 1 through the intermediary of a resistor R1 and a transistor T3 whose collector is connected to a high power supply terminal 1 through the intermediary of a resistor R2 and emitter is connected to a low power supply terminal 2 through the intermediary of a constant current source I. An emitter follower output circuit is composed of a transistor T4 whose base is connected to the collector of the transistor T2 and a transistor T5 whose base is connected to the collector of the transistor T3. The resistor R2 is formed variable in resistance and varied in resistance value corresponding to the size of a load capacitor located at an output terminal 6, whereby an electric power can be prevented from being wasted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a master slice type semiconductor integrated circuit device composed of an emitter coupled logic circuit.

[0002]

2. Description of the Related Art A master slice type semiconductor integrated circuit device composed of a conventional emitter coupled logic circuit is shown in FIG.
Will be explained. In the circuit shown in FIG. 4, the bases are connected to the input terminals 3 and 4, respectively, and the collector is the resistor R1.
Transistor T connected to the high-potential side power supply terminal 1 via
1 and T2, the base is connected to the reference power supply terminal 5, the collector is connected to the higher power supply terminal 1 through the resistor R2, the emitters are commonly connected to the emitters of the transistors T1 and T2, and the constant current source I is connected. A transistor T3 connected to the lower power supply terminal 2 through a base, a base connected to the collector of the transistor T2, a collector connected to the higher power supply terminal 1, and an emitter connected to the output terminal 6; Is output terminal 6
Connected to the collector of the transistor T3 via the capacitor C and the emitter connected to the low-side power supply terminal 2
And a transistor T6 having a base and a collector connected via a resistor R4, a collector connected to the high-potential power supply terminal 1 via a resistor R3, and an emitter connected to a low-potential power supply terminal 2. Configured, resistors R1 and R2, transistors T1, T
2 and T3 and the constant current source I constitute a differential logic circuit section, and the transistors T4 and T5 constitute an emitter follower output circuit section. The resistors R3, R4 and R5 and the transistor T6 provide a constant voltage to the base of the transistor T5.
And a circuit in which a steady current is passed through T5. When the input terminals 3 and 4 are at a low level lower than the potential of the reference power source terminal 5, the constant current I flows through the transistor T3 and the resistor R2, so that the collector potential of the transistor T2 becomes the high potential side power source potential and the output terminal 6 is at a high level. Becomes

When one of the output terminals 3 and 4 is at a high level higher than the potential of the reference power supply terminal 5, the constant current I flows through the transistor T1 or T2 and the resistor R1 so that the collector level of the transistor T2 is constant current I. And, the output terminal 6 becomes low level because the potential drop due to the resistor R1 becomes a constant potential from the high-potential side power supply potential. Therefore, the circuit diagram of FIG. 4 constitutes a 2-input NOR circuit. In the above-described semiconductor integrated circuit device, the output terminal 6 has a parasitic capacitance CL due to a connection wiring to the next-stage logic circuit,
When the output level rises and falls, this parasitic capacitance CL is charged and discharged. When the output level rises, the driving capacity of the transistor T4 charges the parasitic capacitance CL, so that a steep rising is obtained. However, when the output level falls, the parasitic capacitance CL is discharged by the current flowing through the transistor T5, so that a steep falling occurs. In order to obtain, it is necessary to increase the current flowing through the transistor T5. Therefore, in the circuit shown in FIG. 4, the inverted logic signal of the output signal is obtained from the collector of the transistor T3 by the capacitor C,
It is applied to the base of the transistor T5, and the current flowing in the transistor T5 is increased only during the transition period of the fall of the output level of the output terminal 6 to rapidly discharge the parasitic capacitance CL. That is, at the fall of the output level, the current path of the constant current I switches from the resistor R2 to the resistor R1, so that the collector potential of the transistor T3 rises. At this time,
Since the base of the transistor T5 is coupled to the collector of the transistor T3 by the capacitor C, the base potential of the transistor T5 rises transiently. Since the current flowing through the collector of the transistor is given by the following equation (1), the current flowing through the transistor T5 transiently increases.

I = Is · exp ((qV) / (kT)) (1) where Is is a saturation current value, q is a charge amount, k is a Boltzmann constant, and T is an absolute temperature.

Then, the base potential of the transistor T5 normally returns to the level determined by the resistors R3, R4 and R5 and the transistor T6, and the current flowing through the transistor T5 returns to the steady value.

[0006]

In the above-described conventional semiconductor integrated circuit device, the transient current flowing through the transistor T5 is transiently constant at the fall of the output level, without depending on the size of the load capacitance CL. Therefore, the load capacity C
Unnecessary increase in power consumption due to excessive flow of transient current despite L being small, or delay time due to inability to flow transient current required for discharging despite large load capacitance CL There was a problem such as the increase of. Also, according to the size of the load capacitance CL, the capacitor C
There is also a method of switching the transient current value by changing the value of, but in the master slice type semiconductor integrated circuit device that forms a desired logic form by selecting the wiring connection form, in the element formation stage on the common substrate. A plurality of capacitors C must be formed, and the capacitors C are used only in the output circuit section and cannot be used as other circuit elements.
Since the required area is larger than the resistance and the like, forming a plurality of capacitors C on the common substrate in advance has a problem that the area of the semiconductor integrated circuit chip is increased.

[0007]

In order to solve the above problems, in a semiconductor integrated circuit device of the present invention, the respective emitters are connected in common, and the collectors are connected to a lower power supply terminal via a constant current source. Is the input of the output logic signal from the connection point of the collector and the resistor of the first transistor, which constitutes the differential logic circuit composed of the differential transistor pair connected to the high-potential side power supply terminal via the resistor, to the base and A logic circuit for outputting through an output circuit composed of an emitter follower transistor used as an output terminal,
The emitter is detected by detecting a collector potential of a second transistor which is paired with a first transistor having a collector for taking out the output logic signal and whose collector is connected to a high potential side power supply terminal through a second resistor. In the logic circuit which transiently controls the circuit current of the follower transistor output circuit, the second resistor has a desired resistance value corresponding to the load capacitance value existing at the output terminal.

[0008]

The present invention will be described below with reference to the drawings. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. The circuit shown in FIG. 1 has a transistor T1 whose bases are connected to the input terminals 3 and 4, respectively, and whose collector is connected to the high-side power supply terminal 1 via the resistor R1.
And T2, the base is connected to the reference power supply terminal 5, the collector is connected to the high potential side power supply terminal 1 via the resistor R2, the emitter is commonly connected to the emitters of the transistors T1 and T2, and the low potential is connected via the constant current source I. Side power terminal 2
Connected to the collector of the transistor T2, the collector connected to the high-potential side power supply terminal 1, the emitter connected to the output terminal 6, and the collector connected to the output terminal 6. A transistor T5 whose base is connected to the collector of the transistor T3 via a capacitor C and whose emitter is connected to the low-potential side power supply terminal 2; and base and collector are connected via a resistor R4, and the collector is high side via a resistor R3. The transistor T6 is connected to the power supply terminal 1 and the emitter is connected to the lower power supply terminal 2, and the resistance value of the resistor 2 is changed according to the magnitude of the load capacitance existing at the output terminal 6. The basic operation of each circuit portion is the same as that of the conventional example described with reference to FIG. Now, output terminal 6
If the load capacitance CL existing in the load capacitance CL is small and the current for discharging the charge stored in the load capacitance CL at the fall of the output level is small, the resistance value of the resistor 2 is set to be small and the output terminal 6 The change in the collector potential of the transistor T3 due to the change in the logic state is reduced. As a result, the amount of transient change in the base potential of the transistor T5 is reduced, and unnecessary transient current flowing in the transistor T5 can be suppressed. On the contrary, when the load capacitance CL existing at the output terminal 6 is large and a large amount of current is required to discharge the electric charge stored in the load capacitance CL when the output level falls, the resistance value of the resistor 2 is increased. Is set to a large value to increase the change in the collector potential of the transistor T3 due to the change in the logic state of the output terminal 6. This allows
The transient change amount of the base potential of the transistor T5 becomes large, and a large amount of current can be transiently passed through the transistor T5 to rapidly discharge the electric charge charged in the load capacitance CL. In the master slice type semiconductor integrated circuit device, the resistors R1, R2, etc. are usually formed by using a plurality of basic resistors formed in advance on a common substrate.
For example, basic resistances are connected in parallel to set the resistance value of R2 small, and basic resistances are connected in series to set the resistance value of R2 large.
Furthermore, since this basic resistance is formed in advance on a common substrate in order to form various circuits,
It is not necessary to newly prepare an extra element on the common substrate to configure the circuit of the present invention, and there is no increase in the chip area. FIG. 5 shows a collector potential waveform of the transistor T3, a transient current waveform flowing in the transistor T5, and an output signal waveform of the output terminal 6 depending on the resistance value of the resistor R2.
Further, FIG. 6 shows the load capacitance dependency of the circuit delay time due to the difference in the resistance value of the resistor R2. Here, the resistance value of the resistor R2 is 2 KΩ and 1 KΩ, the resistance value of the resistor R1 is 2 KΩ, the value of the capacitor C is 50 fF, and the current value of the constant current source I is 0.3.
mA, high side potential is 0V, low side power source potential is -3.4V
Is.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention. In this embodiment, the point at which the capacitor C is connected is divided into the resistor R2a and the resistor R2b and set as the connection node between the resistors R2a and 2b, and the resistor R2 is placed on the resistor R2 of the capacitor C according to the size of the load capacitance CL. By changing the connection point of, the change in the base potential of the transistor T5 due to the change in the logic state of the output terminal 6, that is, the transient current value flowing in the transistor T5 is changed. Specifically, it is realized by changing the position of the electrode provided on the polysilicon forming the resistor. In this embodiment, the resistance value of the resistor R2 itself is constant regardless of the connection position of the capacitor C on the resistor R2. Therefore, since the change in the collector potential of the transistor T3 is constant regardless of the connection position of the capacitor C, it is suitable for application to a circuit that performs another logical operation using the collector potential of the transistor T3.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit device according to a third embodiment of the present invention.

The circuit diagram shown in FIG. 3 is the collector of the transistor T3 when the load capacitance CL is large and the resistance value of the resistor R2 is set to be large in the semiconductor integrated circuit device of the first embodiment shown in FIG. A clamp transistor T7 is inserted between the high-potential power supply terminal 1 and the collector of the transistor T3 in order to prevent the potential of the transistor T3 from being saturated too much.

[0012]

As described above, according to the present invention, the transient current value flowing for discharging the electric charge charged in the load capacitance at the time of the fall of the output signal level is changed according to the size of the load capacitance. Therefore, there is an effect that it becomes possible to configure a logic circuit having an appropriate load driving capability without wasting power consumption. Further, when the output signal level rises, the load capacitance CL is charged by the driving ability of the transistor T4, so that a steep rise signal is obtained regardless of the resistance value of the resistor R2.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit device.

FIG. 5 is a diagram showing an in-circuit potential and a current of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a load capacitance dependency of a delay time of the semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

1 High-side power supply terminal 2 Low-side power supply terminal 3 First input terminal 4 Second input terminal 5 Reference power supply terminal 6 Output terminal R1, R2, R3, R4, R5 Resistance R2a, R2b, R2c, R2d R2 dividing resistance T1, T2, T3, T4, T5, T6, T7 Transistor I Constant current source C Capacitor CL Load capacity

Claims (1)

[Claims] 1. A differential comprising a pair of differential transistors in which respective emitters are connected in common and are connected to a lower power supply terminal via a constant current source, and collectors are connected to a higher power supply terminal via a resistor. A logic circuit that outputs the output logic signal from the connection point between the collector and the resistor of the first transistor that constitutes the logic circuit to the base and outputs it through the output circuit composed of the emitter follower transistor whose emitter is the output terminal By detecting the collector potential of the second transistor which is paired with the first transistor having a collector for taking out the output logic signal and whose collector is connected to the high-potential side power supply terminal through the second resistor. In a logic circuit that transiently controls the circuit current of the emitter follower transistor output circuit, a negative current present at the output terminal A semiconductor integrated circuit device, wherein the second resistor has a desired resistance value corresponding to a load capacitance value.