JPH05314798A - Ic memory test device - Google Patents

Abstract

PURPOSE:To increase throughput by storing test results of plural bits output from a memory to be tested in a memory, counting numbers of failure by a row and column line fail counter, and processing them in parallel. CONSTITUTION:A memory 51 to be tested which outputs 4 bits and the like is accessed and tested via an address generator 3 and a reading control section 2, and normal/defective of test results is stored in a fail memory 1. And, numbers of failure are counted by a row line fail counter 4a and a column line fail counter 4b of a relief processing section 41. In the same way as the above concerning memories 52-5n to be tested, the counter 4a and 4b, etc., can count numbers of failure as one piece every memories 51-5n independently of numbers of output bits of each memory. Therefore, throughput can be increased by processing memories 51-5n in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an IC having a redundant spare line.
The present invention relates to a defective cell repair process in a memory testing device.

[0002]

2. Description of the Related Art Generally, a large-capacity memory is provided with a redundant spare line in order to improve its yield, and when a defective cell is found, it is replaced with the redundant spare line. Also, the memory has an array structure of matrix,
Redundant spare lines are provided in each of the rows and columns. However, as the capacity of the memory increases, the test time increases, and it is essential to shorten the test time including the above-mentioned repair processing time in order to improve the throughput.

At present, in the memory test, as shown in FIG. 3, the test result of the memory under test is stored in the fail memory 1 in real time, and after the test is finished, the test result is read from the fail memory 1 and the rescue process is performed by the CPU or It is done by dedicated hardware. Therefore, in order to complete the test and proceed to the next test, it is necessary to read the defect information of the memory under test from the fail memory and perform a relief process on all the test results, such as counting the number of defects on the row and column lines. Is.

Conventionally, a relief process has been performed by a technique represented by Japanese Patent Laid-Open No. 62-204500, which will be described below with reference to FIG. Here, a case will be described in which N tested memories of 4-bit output are simultaneously tested. FIG. 5 shows a fail memory 1 for storing a test result of a memory under test and a failure information stored in the fail memory 1 after the test and reading the number of failures on a line by row and column directions while reading out the failure information for each output. The row line fail counter 7a for counting and the column line fail counter 7b are constituted by hardware capable of simultaneously processing N sets. In the prior art, the memory under test is stored for each output in parallel in the fail memory 1 at the time of testing, and the fail memory 1 is row and column line fail counters 7a, 7b for each output after the test is completed.
The number of defective lines is counted, and the line having a large number of defects is relieved. In general, in the mass production test of a memory, a large number of memories under test are tested at the same time in order to improve throughput. Therefore, also in the relief processing, it is important to perform the line fail count of a large number of rows and columns at the same time in order to improve the throughput. Here, when 16 4-bit output memory under test are tested at the same time, in the prior art, in order to collectively process the line fail counts of these test results, 64 sets of row and column line fail counters are arranged in parallel. It is necessary to have it, and there is a problem that a huge amount of hardware is required to correspond to the number of output bits of the memory under test, which is difficult to realize.

[0005]

SUMMARY OF THE INVENTION In the present invention, the above problems are solved, and the relief processing after the end of the test of the memory under test having a plurality of bit outputs tested simultaneously at a large number is efficiently performed to increase the throughput. It is an object of the present invention to provide an IC memory test device capable of achieving this.

[0006]

The above object is to provide a fail storing means for storing a test result of a memory under test having a plurality of bit outputs tested at the same time for each output of the memory under test, and the fail storing means. Read control means for sequentially reading the test results for each of a plurality of bits of the memory under test stored in the memory, and the read results for each of a plurality of outputs.
A line fail count means for counting the number of defects on a set of row and column lines, a first address for reading the fail storage means, and a failure of each output of the memory under test read from the fail storage means. Address generating means for generating a second address for identifying information and a third address for identifying which output row and column the number of defects is being counted by the line fail counting means. Can be achieved by providing.

[0007]

The output of the memory under test having a plurality of bits of output can be realized by one set of line fail counting means without requiring line and row line fail counting means for each minute. Downsizing,
The number of line fail count means does not depend on the number of output bits of the memory under test. Further, when testing N memories under test at the same time, N line fail counts can be easily realized in parallel by having N means in parallel, and high throughput can be achieved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a fail memory 1 for storing the results of simultaneous testing of 5n memory cells 5 to 5n having four outputs, and X, Y, and X for reading defect information from the fail memory 1 after the test. An address generator 3 capable of generating a Z three-dimensional address, and a read controller 2 for controlling the read of the defect information stored in the fail memory 1.
The read defect information is composed of a row line fail counter 4a and a column line fail counter 4b which count the number of defects on the row and column lines by the address of the address generator. Z of the address generator 3 is an address for identifying each output of the memory under test, Y is a column, and X is an address for identifying a row.

FIG. 2 shows the memory under test 51 of FIG.
This is an actual example when line fail count is performed for rows and columns, and its operation will be described below. First, from the fail memory 1 to the outputs 1 to 4 of the memory under test 51 from the fail memory 1 according to the (Y + X) address of the address generator 3.
The test results up to are read out at the same time, and the Z address of the address generator 2 causes the read control section 2 to output 1 to 4
Select one to read. The read test result is held in the addresses (Z + Y) and (Z + X) by the row and column line fail counters 4a and 4b. Here, when the Z address is 0, the test result of the output 1 of the memory under test 51 is read, and when it is "1", the result of the output 2 is read. It will be. Further, in the line fail counter 4a that performs these read information,
Count to the row line address given the (Z + Y) address. That is, since the Z address for identifying each output is given to the address for storing the count result, there is no malfunction such as confusing the number of defects on the same address line of each output. Row line fail counter 4b
Similarly, the number of defects on the row and column lines is counted by the (Z + X) address. Therefore, the number of defects on the row and column lines of the memory under test having a 4-bit output can be counted by one set of row and column line fail counters.

In the above-described embodiment, the N simultaneous processing of the memory under test having a plurality of outputs can be easily realized by providing the N-type row and column line fail counters as shown in FIG. can do.

In this embodiment, the memory under test having an output bit number of 4 bits has been described. However, the present invention is not limited to this, and the read control unit 2 and the address generator 3 in FIG. 1 have various bit widths. It can be used as a test memory.
Further, the relief processing means is described by the line fail count of the row and the column, but the invention is not limited to this, and when the number of defects on one line address exceeds a predetermined value, a means for storing the line address is provided. Alternatively, a means for converting into address information indicating only the position of the defect information read from the fail memory 1 may be provided.

[0013]

According to the present invention, since it is configured as described above, the following effects can be obtained.

(1) A test result stored in a memory under test having a plurality of bit outputs for each output bit can be realized by a row and column line fail counter that counts the number of defects on a set of row and column lines, and Even when N memory under test is simultaneously tested, parallel processing can be easily realized by providing line fail counters for N sets of rows and columns, and high throughput can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an operation example of the first exemplary embodiment of the present invention.

FIG. 3 is a supplementary explanatory diagram of the present invention.

FIG. 4 is a diagram showing a principle of a conventional technique.

[Explanation of symbols]

1 ... Fail memory, 2 ... Read control unit, 3 ... Address generator row, 4 ... Relief processing unit, 42 ... Relief processing unit, 4n
... Relief processing unit, 4a ... Row line fail counter, 4b
... column line fail counter, 51 ... memory under test, 5
2 ... Memory under test, 5n ... Memory under test, 6 ... Address generator, 71 ... Relief processing section, 72 ... Relief processing section.

Claims (1)

[Claims] 1. A defect information storage means composed of a plurality of blocks for storing test results of a memory under test having a redundant bit line and having a plurality of bit outputs for each output bit, and the defect information storage means. Read control means for sequentially reading the test result for each output bit of the memory under test, and counting the number of defects on the row and column lines of the read result for each output bit by row and column direction Means and
An address for reading the defect information from the defect information storage means, an output bit identification address for sequentially reading the read defect information for each output bit by the read control means, and read through the read control means. An IC memory test apparatus comprising: an address generating unit that generates an address for storing the result of counting the defect information by the defect counting unit.