JPH05314791A - Performance test method for semiconductor device with redundant circuit and semiconductor device with redundant circuit - Google Patents

Abstract

PURPOSE:To realize a performance test method for which twice performance tests are not required even when a detective part found by the performance test is substituted with a redundant circuit in the performance test method for a semiconductor device with the redundant circuit and a semiconductor device with the redundant circuit. CONSTITUTION:This method is a performance test method by which a semiconductor device having a normal circuit 1 and a redundant circuit 2 is operated in trial, and constituted so that operation in the trial is performed for the redundant circuit 2, as well in the performance test method of the semiconductor device by which substitute process substituting a defective part with the redundant circuit 2 is performed after the performance test.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation test method for smoothing a semiconductor device having a redundant circuit for replacing a defective portion of a normal circuit under a predetermined condition, and more particularly to a defective portion of the normal circuit after the operation test. The present invention relates to an operation test method when a replacement step of replacing with a redundant circuit is performed, and a semiconductor device having a structure suitable for such an operation test.

[0002]

2. Description of the Related Art Semiconductor devices such as memory devices and logic circuit devices have been increasing in size in recent years, and there is a demand for further improvement in yield and reliability in the manufacturing process.
As a method of improving yield, a method is provided in which a redundant circuit is provided in advance in a semiconductor device, and when a defective portion is found in a normal circuit, the defective portion is replaced with a portion having a similar function to the redundant circuit. There is. By doing so, the discarded circuit can be made into a good product when there is a defect in even one place in the normal circuit, so that the yield can be greatly improved.

FIG. 5 is a diagram showing a basic circuit configuration example for replacing a defective portion of a normal circuit with a redundant circuit. In FIG. 5, reference numeral 51 is a normal circuit, and 52 is a redundant circuit. In order to replace a defective portion of the normal circuit 51 with a portion having the same function as the redundant circuit 52, it is necessary to switch the input / output signal of the normal circuit 51 to the redundant circuit 52, and the input switching circuit 56 and the output switching circuit 57 are for that purpose. It is a switching circuit. Reference numeral 58 denotes a switching setting circuit, which designates a portion of the normal circuit 51 and the redundant circuit 52 which are switched by the input switching circuit 56 and the output switching circuit 57. Since the replacement is performed after the defective portion of the normal circuit 51 is found, the switching setting circuit 58 is made of a fuse ROM, and the replacement portion is designated by writing predetermined information in the switching setting circuit 58. Also, the replacement may be performed by cutting the wiring pattern with laser light or the like.

In FIG. 5, the input switching circuit 56 is used as a switching circuit.
Although the output switching circuit 57 and the output switching circuit 57 are shown, only one of them may be present. For example, in the memory device shown below, the bit lines, which are normally output parts, are commonly connected, and only the signals of the input parts are switched. In order to replace a defective part with a redundant circuit, it is necessary to prepare a redundant circuit necessary for finding and replacing the defective part. Therefore, it is not easy to apply this method to a logic circuit element such as a microprocessor, and the surface usage efficiency is significantly reduced. Therefore, this method is most effective when applied to a memory device in which the same memory cells are arranged. Therefore, the following description will be made with reference to the memory device as an example.

FIG. 6 is a diagram showing a configuration example of a memory element having a redundant circuit. In FIG. 6, 61 is a memory cell array in which memory cells are arranged in an array, and 62 is a redundant memory cell array for a redundant circuit. Reference numeral 681 denotes a row decoder which decodes a row address signal to bring only one corresponding word line of the memory cell array 61 into an operating state. Reference numeral 682 denotes a column decoder 682 which decodes the column address signal and activates one of the column selection switches 683. In the column selection switch 683, the selected switch connects a bit line or a bit line pair (hereinafter collectively referred to as a bit line) to the sense amplifier 684. Reference numeral 685 denotes a bit line control circuit, which changes the voltage level applied to each bit line depending on whether the operation is a write operation or a read operation. The memory operation is performed on the memory cells connected to one word line and one bit line designated by the row decoder 681 and the column decoder 682.

The above is the configuration and operation of a normal memory device. However, when the redundancy circuit 62 is provided, the redundancy setting circuit 6
31, a selection circuit 633, and a selection prohibition circuit 634. The defective portion of the memory cell array 61 is replaced on a word line basis, and the memory cells of one row attached to the word line of the memory cell 61 are replaced by the memory cells of the first row of the redundancy circuit 62. When the row decoder 681 selects a word line to be replaced, the selection prohibition circuit 634 prohibits the word line of the memory cell array 61 from operating and the selection circuit 633 operates the word line at the uppermost position of the redundant memory cell array 62 to operate. To The redundant memory cell array 62 has a plurality of word lines, and can be replaced by the number of word lines. Which word line is to be replaced is determined by storing information in the redundancy setting circuit 631.

[0007] Generally, the finding of a defective portion and the replacement of the defective portion by a redundant circuit are performed at the stage when a chip-shaped semiconductor device is completed on a semiconductor wafer.
The defective portion is found by using an IC tester attached to the probing device. Replacement with a redundant circuit
As described above, it is performed by cutting the wiring pattern by laser light, cutting by applying a voltage to the fuse ROM, or the like. The semiconductor device that has undergone the replacement process with the redundant circuit is inspected again for normal operation without any defective portion.

After the above processing is completed, the semiconductor device is completed by the steps of cutting out chips, assembling, operation test and the like. Conventionally, when a new defect occurs in these processes, it is discarded as a defective product. It had been. However, if the integrated circuit of the semiconductor device becomes large in scale and the defect rate after the replacement process by the redundant circuit becomes so large that it cannot be ignored, the cost will increase if the defective product is discarded as it is. Therefore, for example, in addition to the first replacement process of first replacing the defect found in the test immediately after the completion of the wafer with the redundant circuit as in the conventional method, the defective part in the subsequent process is found in the final test, and Replacing defective points with redundant circuits It has become necessary to replace with multiple levels of redundant circuits.

A process called burn-in is a process performed after the inspection immediately after the completion of the wafer and the process of replacing the defective portion. This is an operation test method in which a signal is actually applied to the semiconductor device for a certain period of time under severe temperature conditions in order to find an initial operation failure that cannot be found by a single inspection. It has a great effect.

[0010]

The operation test by burn-in is performed by applying a signal to the input portion of the semiconductor device to perform a normal operation. Therefore, the operation test is performed only on the portion that operates by applying a signal. That is, the operation test is performed only on the normal circuit excluding the defective portion and on the redundant circuit in the first replacement step, and the defective circuit is replaced by the burn-in operation. No tests will be conducted. This will be described with reference to FIG. 7 using a memory element as an example.

FIG. 7 shows a redundant memory cell array 7 because some of the memory cells connected to the third word line of the memory cell array 71 in the memory device of FIG. 6 are defective.
It is replaced with the row of memory cells connected to the first word line of No. 2, and such switching information is written in the redundancy setting circuit 731. When the memory element shown in FIG. 7 is subjected to the burn-in operation test, only the row tangent to the word line indicated by a on the right side of each memory cell array is tested. Except for the first row of the redundant memory cell array 72, the other unused rows indicated by Y in the figure are not tested for operation.

If a defective portion is found in the burn-in operation test as described above, it is possible to replace the word line connected to the defective portion again with an unused row of the redundant memory cell 72 so that a good product is obtained. If so, the yield is improved accordingly. However, in the burn-in operation test as described above, the unused portion of the redundant memory cell array is not tested, so if the unused portion is to be replaced, the burn-in operation test is performed again after the replacement. I need to do it. If this operation test is not performed, there arises a problem that sufficient reliability cannot be guaranteed for the newly replaced portion.

However, it is problematic to perform the burn-in operation test again on the semiconductor device which has been once subjected to the burn-in operation test, in order to improve the process efficiency. The present invention has been made in view of the above problems, and reliability is maintained without performing an operation test by burn-in again even when a defective portion generated after an operation test by burn-in is replaced with a redundant circuit. It is an object of the present invention to realize an operation test method by burn-in of a semiconductor device that does not cause a decrease in efficiency of the semiconductor device and a semiconductor device suitable for such an operation test.

[0014]

SUMMARY OF THE INVENTION A semiconductor device operation test method according to the present invention comprises a normalization operation of a semiconductor device having a normal circuit and a redundant circuit used to replace a defective portion of the normal circuit under predetermined conditions. This is a method of performing a replacement step of replacing a defective portion with a redundant circuit when a defective portion is found in the normal circuit after the operation test. Further, in order to achieve the above object, it is characterized in that the break-in operation is also performed on the redundant circuit.

Another aspect of the present invention is a semiconductor device for applying the above-described operation test, and its basic configuration is shown in FIG. In FIG. 1, 1 is a normal circuit, 2 is a redundant circuit used to replace this normal circuit, and 3
Is a switching means for replacing a defective portion of the normal circuit 1 with the redundant circuit 2. Although the switching means 3 is shown to be composed of the input switching means 6 and the output switching means 7 in the figure, the invention is not limited to this, and the defective portion may be replaced by the redundant circuit 2. The semiconductor device of the present invention includes the normal circuit 1, the redundant circuit 2, and the switching means 3 described above. In order to achieve the above object, the redundant circuit is subjected to an operation test in which the semiconductor device is smoothed and operated under predetermined conditions. It is characterized by comprising an operation test signal applying means 4 for applying a signal for leveling and operating the device 2.

[0016]

Since the break-in operation during the operation test is performed on the unused redundant circuit, it is necessary to perform the operation test again when the defective portion found by the operation test is replaced with the unused redundant circuit. There is no. Further, since the semiconductor device of the present invention is provided with the operation test applying means 4, a signal for the leveling operation is applied to the redundant circuit 2 via the operation test applying means 4 during the operation test, which is similar to the normal circuit 1. The smoothing operation is performed.

[0017]

2 is a diagram showing the configuration of an embodiment in which the present invention is applied to a memory device having a redundant circuit. As described above, each memory cell of the memory device is arranged in an array, and each memory cell can be accessed by specifying a row and a column. A row is designated by activating one of the word lines, and a column is designated by activating one of the switch columns connecting the set of bit lines to the output. When a defective portion is found in the normal circuit, the redundant circuit is replaced row by row, that is, in word line units.

In FIG. 2, reference numeral 21 denotes a memory cell array of a normal circuit, which has a structure of, for example, 1024 rows × 1024 columns. Reference numeral 281 denotes a row decoder, which decodes an input row address and activates one word line of the memory cell array 21. Reference numeral 282 denotes a column decoder which decodes an input column address and puts one of the column selection signal lines into an operating state. Reference numeral 283 denotes a column selection switch, which is a column of a set of switches connecting a set of bit lines connected to each column of the memory cell array 21 to the sense amplifier 284 of the output section, and each set of switches has the above column selection signal. Controlled by the corresponding line of lines. That is, the set of bit lines in the column designated by the column decoder 282 is connected to the sense amplifier 284. Reference numeral 285 is a bit line control unit which controls a set of bit lines in accordance with whether to read or write. A normal memory device is composed of the above parts.

In this embodiment, the defective portion found before the operation test is replaced with the redundant circuit before the operation test. The redundant circuit and the word line switching section for this purpose are provided in the memory cell array 21 and the row decoder 281. The redundant circuit included and described below is for replacement after the operation test. In FIG. 2, reference numeral 22 denotes a redundant memory cell array for a redundant circuit, which has memory cells for several rows to more than ten rows, for example, 16 rows of the memory cell array 21 of the normal circuit. That is, here, the redundant memory cell array 22 is a memory cell array of 16 rows × 1024 columns. 231
Is a redundancy setting ROM, which stores the row number of the replacement memory cell array 21 and the position of the redundancy memory cell array 22. Reference numeral 232 is a column of connection switches for connecting the word line from the row decoder 281 and the memory cell array 21, and switches the word line switch to be replaced based on the data of the redundancy setting ROM 231 in a non-connection state. Reference numeral 233 denotes a redundant connection switch, which sequentially connects word lines to be replaced among the word lines from the row decoder 281 to the rows of the redundant memory cell array.

A redundant decoder 241 decodes a row address signal applied to the redundant memory cell array 22 during an operation test. Since the number of rows of the redundant memory cell array 22 is 16 in this embodiment, the redundant decoder is a 4-bit decoder. Reference numeral 242 denotes a changeover switch array for changing over the connection of the word lines of the redundant memory cell 22, and a word line access signal for changing over to the redundant decoder 241 side is applied to the redundant memory cell array 22 during the operation test. In the non-operation test, it is connected to the redundant connection switch 233 side. 243 is a control terminal at the time of the operation test. Reference numeral 25 is a disconnection switch row for disconnecting the bit line connected to the memory cell array 21 from the redundant memory cell array 22 during an operation test. And 24
Reference numeral 4 is a bit line control unit when the redundant memory cell array 22 is separated.

A procedure for testing the operation of the memory device shown in FIG. 2 and replacing the defective portion with the redundant memory cell array 22 will be described. First, when the operation test is started, nothing is written in the redundancy setting ROM 231, all the connection switch rows 232 are in the connected state, and all the redundant connection switch rows 233 are in the non-connected state. Then, for the operation test, the address signal input terminal is connected to the address counter and the control terminal 243 is set to the operation test state. As a result, the changeover switch array 242 is connected to the redundant decoder 241 side, the disconnection switch array 25 is disconnected, and the redundant bit line control unit 244 is activated. In this state, the address signal is sequentially changed, and the bit line control unit 285 controls writing and reading, whereby the leveling operation to the memory cell array 21 is performed.

The address signals are simultaneously sent to the redundant decoder 24.
1 is also input, and the word lines of the redundant memory cell array 22 are sequentially operated. The redundant bit line control unit 2
By controlling the bit line by 44, the break-in operation is performed on the redundant memory cell array 22. At this time, the output of the redundant memory cell array 22 is the memory cell array 2
Since it is separated from 1, the signals do not collide, but the output cannot be read. If the output of the redundant memory cell array 22 is detected due to the necessity of the operation test, it is necessary to provide a column selection switch and a sense amplifier connected to the redundant memory cell array 22 only during the operation test.

The smoothing operation is performed as described above. After the smoothing operation, the memory cell array 21 is sequentially accessed to perform a write / read test of a predetermined value. If a defective portion is found in this inspection, the row address of the defective portion of the memory cell array 21 and the data of which row of the redundant memory cell array 22 the row address is to be replaced with are stored in the redundancy setting ROM 231. Here, replacement of 16 rows is possible, and when there are more defective portions, redundancy is impossible and the memory element is discarded.

Based on the data set in the redundancy setting ROM 231, the connection switch row 232 brings the word line to be replaced into the non-connection state. And the redundant connection switch 23
3 sequentially connects the word lines to be replaced among the word lines from the row decoder 281 to the word lines of the redundant memory cell array 22. When the memory element subjected to the redundancy processing as described above is used, the control terminal 243 is set to the non-operation test state, so the changeover switch 242 is connected to the redundant connection switch 233 side and the disconnection switch row 25.
Becomes a connected state, and the redundant bit line control unit 244 becomes inactive. Then, when the memory cell of the non-replaced row of the memory cell array 21 is accessed, the corresponding memory cell of the memory cell array 21 is directly accessed, but when the memory cell of the replaced row is accessed, the memory cell array 21 is accessed by the connection switch 232.
No access is made because the connection to the word line is disconnected, and the row of the redundant memory cell array connected by the redundant connection switch 233 is accessed. At this time, the bit line control unit 285 controls the bit line set for writing and reading operations to and from the redundant memory cell array 22 because the bit lines are commonly connected to the memory cell array 21, and the output is also column select. This is performed from the sense amplifier 284 via the switches connected by the switch 283.

In this embodiment, the 4-bit redundant decoder 241 is used to access the word line of the redundant memory cell array 22 during the operation test. Here, instead of the redundant decoder 241, the 16 outputs from the row decoder 281 can be used as they are. By doing so, in the operation test, the redundant memory cell array 22 is accessed at the same frequency as the memory cell array 21, and the leveling operation is performed.

However, in this embodiment, the redundant decoder 241 is used.
A 4-bit decoder was used as the input, and the lower 4 bits of the row address signal were input. The number of addresses is shown in the explanatory diagram of FIG. As shown in FIG. 3, 31 is 10
It is a memory cell array for 24 word lines, and a 10-bit decoder 38 is required to decode its row address signal.
1 is required. 32 is a redundant memory cell array for 16 word lines, and an address signal is decoded by a 4-bit decoder 341. The break-in operation is performed by sequentially accessing each memory cell, and the row address signal also sequentially changes. Therefore, the ratio of accessing each word line of the memory cell array 31 for 1024 word lines is 1/10.
24. Compared with this, the ratio of accessing each word line of the redundant memory cell array 32 for 16 word lines is 1
/ 16. Therefore, the redundant memory cell array 32 is accessed 64 times as many times as the memory cell array 31.

Since the severity of the operation test is proportional to the number of break-in operations, it means that the redundant memory cell array 32 has been subjected to the severe test. Therefore, higher reliability is realized. The configuration of the embodiment shown in FIG. 2 is shown by a block diagram of each part, and a concretely shown embodiment thereof is shown in FIG. In this embodiment, the present invention is applied to an EPROM, and a normal circuit is 4
There is a memory cell array for word lines, and there is a memory cell array for two word lines as a redundant circuit.
It is performed in word line units.

In FIG. 4, W1 to W4 are word lines, and J1 and J2 are redundant word lines. Reference numeral 41 is a memory cell array of a normal circuit, and 42 is a redundancy memory cell array. Reference numeral 45 is a switch line for disconnecting the bit line. Reference numeral 431 is a ROM for setting whether or not to perform redundancy replacement and which of the W1 and W2 pair and the W3 and W4 pair is to be replaced. An AND gate column 432 corresponds to a connection switch column that selectively disconnects the connection between the output from the row decoder 481 and the word line. 433
The gate circuit of is a circuit that generates a word address signal to the redundant memory cell array 42 during the operation test and during normal use. An operation test setting unit 443 is set to the “H” level during the operation test. Reference numeral 444 is a redundant bit line control unit for connecting the redundant memory cell array 42 to a power supply during an operation test. Reference numeral 481 is a row decoder of the memory cell array 41 of the normal circuit. Here, a part for controlling the bit line pair, a column decoder, etc. are omitted.

At the time of the operation test, the operation test setting section 443 is set to the "H" state. This may be externally provided with a terminal provided externally, or may be produced internally. When it is at "H" level, all word lines are accessible and any one of the word lines is selected according to the values of S1 inputs A0 and A1. Redundant memory cell array 42
Are alternately selected according to A0.

A binary down signal is repeatedly input to A0 and A1 during an operation test, and word lines are selected in the order of W1, W2, W3 and W4 accordingly. Since J1 and J2 are selected twice during that time, the redundant memory cell array 42 is stressed twice as much as the memory cell array 41. As described above, during the operation test, the memory cell array 41 and the redundant memory cell array 42 are simultaneously accessed. However, the bit line disconnection switch row 45 causes the bit line of the memory cell array 41 and the redundant memory cell array 42 to be connected to each other. Are separated so that the output signals do not collide. That is, the transistor of the redundant bit line control unit 444 is turned on, and the transistor of the bit line disconnection switch array 45 is turned off. As a result, the bit lines are separated but each memory cell is sequentially accessed. As described above, all the transistors are actually operated and burn-in is performed.

Next, when the burn-in as described above is completed and the operation of the memory cell array 42 is measured, the bit line B1 and the word line W2 (B1, W1) of the memory cell array 41 are measured.
It is assumed that the transistor of 2) (the part marked with X in the figure) becomes defective. Redundant ROM consisting of 2 bits at this time
Of 431, the redundant / non-redundant setting bits are programmed to output "H". Then, the redundant data storage bit is further programmed to output "L". Then, the two word lines W1 and W2 are masked by the AND gate of the connection switch string 432, and instead, when an address signal for selecting the word lines W1 and W2 is input from A0 and A1, J1 and J2 are selected. Will be done. The same applies when a defect occurs in another bit, and when there is a defect in the word line W1 or W2, the redundant data is set to "L".
When there is a defect on the word line W3 or W4, the level may be set to "H" level. If there is no need for redundancy, the word line W1 can be set by setting the redundancy setting bit to "L" level.
To W4 are selected.

If the redundancy setting ROM 431 itself is provided with a redundancy function by adopting a parallel system or the like, the yield is further improved. In the above second embodiment, an example of an EPROM is shown, but the same applies to static RAM and dynamic RAM.

[0033]

According to the present invention, the reliability of a semiconductor device in which a defective portion found after an operation test by burn-in is replaced with a redundant circuit to further improve the yield in manufacturing does not require a second operation test. As a result, the efficiency of the manufacturing process can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of a semiconductor device of the present invention having a redundant circuit.

FIG. 2 is a diagram showing a configuration of an embodiment in which the present invention is applied to a memory element.

FIG. 3 is an explanatory diagram showing that the number of run-in operation circuits added to a redundant circuit in the embodiment of FIG. 2 is increased as compared with a normal circuit.

FIG. 4 is a diagram showing a configuration of a second embodiment in which the present invention is applied to an EPROM having four word lines and a redundant circuit for two word lines.

FIG. 5 is a diagram showing a circuit configuration example for replacing a defective portion with a redundant circuit.

FIG. 6 is a diagram showing a configuration of a memory element having a redundant circuit for replacing a defective portion.

FIG. 7 is an explanatory diagram of an operating state at the time of burn-in of the conventional memory device having the redundant circuit of FIG.

[Explanation of symbols]

 1 ... Normal circuit 2 ... Redundant circuit 3 ... Switching means 4 ... Operation test signal applying means

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Claims (5)

[Claims] 1. An operation test method for operating a semiconductor device having a normal circuit (1) and a redundant circuit (2) used to replace a defective portion of the normal circuit (1) under a predetermined condition. In the operation test method for a semiconductor device, in which after the operation test, a replacement step of replacing a defective portion of the normal circuit (1) with the redundant circuit (2) is performed, the leveling operation is performed in the redundant circuit (2). An operation test method for a semiconductor device having a redundant circuit, which is also performed. 2. The frequency of the leveling operation applied to the redundant circuit (2) is higher than the frequency of the leveling operation applied to the normal circuit (1). Method for testing operation of semiconductor device having redundant circuit. 3. A normal circuit (1), a redundant circuit (2) used for replacing a defective portion of the normal circuit (1), and a defective portion of the normal circuit (1) in the redundant circuit (2). In a semiconductor device provided with a switching means (3) for replacement, an operation of applying a signal for normalizing the redundant circuit (2) during an operation test for normalizing the semiconductor device under a predetermined condition. A semiconductor device having a redundant circuit, comprising a test signal applying means (4). 4. The operation test signal applying means (4) applies a leveling operation having a frequency higher than that of the leveling operation applied to the normal circuit (1) during the operation test to the redundant circuit (2). The semiconductor device having the redundant circuit according to claim 3, wherein the semiconductor device is applied to the semiconductor device. 5. The normal circuit (1) and the redundant circuit (2) are memory array circuits having common bit lines,
4. The semiconductor device having a redundant circuit according to claim 3, further comprising bit line separating means for separating each bit line of the normal circuit (1) and the redundant circuit (2) during the operation test.