JPH05313933A - Data processor - Google Patents

Abstract

PURPOSE:To realize a data processor provided with a back-up circuit for a microcomputer system high in reliability at a low cost. CONSTITUTION:The pumping signal FIN which cyclically becomes active is generated by a microcomputer system 1. Meanwhile, a WDT 6 of a data processor repetitively activates the initial signal INIT to reset the system 1 when the signal FIN is stopped. In such a constitution, a back-up circuit 2 is added to perform the substitute processing of the system 1 having a fault together with a back-up control part 10 which outputs a control signal SS to actuate the circuit 2 when the signal FIN is stopped and also the signal INIT is repetitively activated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a backup circuit (backup system) for a microcomputer system.
The present invention relates to a data processing device including.

[0002] A microcomputer system is a necessary system for performing data processing, and at the same time, it is a necessary system for social life as the use of data processing devices becomes social.

Therefore, it has a great influence on the failure of the microcomputer system. Therefore, the data processing device which may have a serious influence due to this, is provided with a backup circuit of the microcomputer system. Further, it is necessary to smoothly switch from the microcomputer system to the backup circuit in order to perform data processing smoothly.

On the other hand, as the use of the data processing device becomes popular, it is necessary to provide the data processing device at low cost so that the switching can be performed with a simple structure.

[0005]

[Prior Art]

(1) Data Processing Device Including Backup Circuit FIG. 4 is a block diagram illustrating a configuration example of a data processing device including a backup circuit. That is, this is a configuration example of a data processing device including a microcomputer system 1 and a backup circuit (backup system) 2, and controlling the controlled device 4 via the switching unit 3.

On the other hand, the switching section 3 is controlled by the select signal S _S output from the backup control section 5, and when the microcomputer system 1 is operating normally, it is controlled to the a contact side in the figure. However, if the microcomputer system 1 fails, the backup circuit 2 is operated by controlling the contact b side in the figure.

In addition, a runaway of the microcomputer system 1 is monitored by a WDT (Watch Dog Timer) 6, and the microcomputer system 1 is reset when the runaway occurs. That is, the microcomputer system 1
In this configuration, the pumping signal FIN that is repeatedly activated is output, and when the pumping signal FIN stops, the initial signal INIT is activated and the microcomputer system 1 is reset.

Then, the backup control unit 5 monitors the pumping signal FIN and detects the pumping signal FI.
When N is stopped for a predetermined time, a select signal S _S is activated and the switching unit 3 is controlled.

(2) WDT FIG. 5 is an excerpt of a circuit diagram for explaining a circuit example of the WDT. 6 is a waveform diagram for explaining the operation of the WDT circuit shown in FIG. 5, (a) is a waveform diagram showing a pumping signal,
(b) is a waveform diagram of the input voltage of the comparator, and (c) is a waveform diagram of the initial signal. The time axes of (a), (b) and (c) are the same.

That is, after the level of the pumping signal FIN is sensed by the comparators CMP ₃ and CMP ₄ , the OR gate G ₁
Combined and shaped with the transistor Tr via the AND gate G _2.
6 is driven and the pumping signal FIN is active (“H”)
Level C), the transistor Tr ₆ is turned on to charge the capacitor C ₃ .

Further, the capacitor C ₃ is the current of the constant current source CC ₂ .
While discharging with I _CB , the current I of the other constant current source CC ₃
It is configured to charge with _CA.

Accordingly, the pumping signal FIN is stopped comparator CMP ₅ of - (minus) input terminal of the potential
V _C rises, the threshold voltage V _TH1 turns the output of comparator CMP _{5 to} the “L” level, transistor Tr ₇ driven via inverter INV turns ON, and the capacitor
Charging of C ₃ begins. By the way, usually I _CA > I _CB .

Then, the potential V _C of the minus side input terminal of the comparator CMP ₅ decreases, and the output of the comparator CMP ₅ becomes "H" level at the threshold voltage V _TH2.
Tr ₇ turns off and discharge of capacitor C ₃ begins. That is, the potential V _C starts to rise.

[0014] As a result, the collector of the transistor Tr ₈ of the output fed through an inverter INV of the comparator CMP _5, pumping signal FIN is stopped (to time t ₆ in FIG. 6)
Then, initial signal INIT of row active is repeatedly outputted (to time t ₇ in FIG. 6).

(3) Backup controller FIG. 7 is a diagram for explaining the configuration and operation of the backup controller. (A) is a block diagram showing an example of the configuration, and (b) and (c) show that the pumping signal has stopped. In the waveform diagram showing the operation in the case, (b)
Is a waveform diagram showing the pumping signal, (c) is a waveform diagram showing the select signal, (d) and (e) are waveform diagrams showing the operation when the pumping signal becomes available, and (d) is the pumping signal. FIG. 4E is a waveform diagram showing a signal, and FIG. 6E is a waveform diagram showing a select signal. The time axes of FIGS. 7 (b) and 7 (c) are the same,
The time axes of (d) and (e) are the same.

The backup control unit uses the pumping signal FI
After N is stopped, the select signal S _S is made active (“H” level) when a predetermined time T _d1 has elapsed. After that, the pumping signal FI
When N is obtained, the select signal S _S is made non-active (“L” level) after a predetermined time T _d2 .

That is, an internal clock that serves as a time reference
The counter unit 7 counts CLK, the count value S _C of the counter unit 7, that is, the time value is determined by the determination unit 8, and the select signal S _S is output.

On the other hand, the pumping signal FIN is frequency-divided by the timer unit 9 composed of a frequency division counter to obtain the judgment control signal S _pd . Then, the count value S _C of the counter unit 7 is cleared (reset) by the judgment control signal S _pd .

Therefore, if the pumping signal FIN is normally input, the counter section 7 is periodically cleared to limit the increase of the count value S _C. However, if the pumping signal FIN stops, the counter section 7 is not cleared and the count value S _C continues to increase.

Therefore, if the judgment unit 8 monitors the count value S _C of the counter unit 7, the select signal S is detected after a predetermined time T _d1 after the pumping signal FIN is stopped.
_S can be made active (“H” level).

On the contrary, if the pumping signal starts to be input,
The counter unit 7 is cleared after a predetermined time T _d2 determined by the frequency division ratio of the timer unit 9, and as a result, the select signal S _S output from the determination unit 8 can be made non-active (“L” level).

[0022]

However, the configuration of the conventional backup control unit is complicated, and the IC (Integrated Ci
Even if it is made into a rcuit), the component cost corresponding to it is necessary. Therefore, the cost of the entire data processing device is also increased.

A technical object of the present invention is to realize an inexpensive and highly reliable data processing device by realizing a backup control unit for switching between a microcomputer system and a backup circuit with a simple structure. ..

[0024]

FIG. 1 is a diagram for explaining the basic principle of the present invention, in which (a) is a block diagram for explaining the configuration of a data processing device, (b) is a waveform diagram of a pumping signal, c)
FIG. 3A is a waveform diagram of an initial signal, and FIG. 3D is a waveform diagram of a select signal. The time axes of (b), (c), and (d) are the same.

The present invention is characterized in that it has a logic configuration so as to obtain a control signal S _S for operating the backup circuit 2 by referring to both the pumping signal FIN and the initial signal INIT.

That is, the pumping signal FIN which becomes periodically active is generated in the microcomputer system 1, while the initial signal INIT which resets the microcomputer system 1 when the pumping signal FIN stops is repeatedly activated. WDT 6
The data processing apparatus having the above is configured as follows.

That is, when the microcomputer system 1 fails, a backup circuit 2 is provided for performing a substitute process of the microcomputer system 1, the pumping signal FIN is stopped, and the initial signal INIT is repeatedly activated. The data processing device is provided with a backup control unit 10 that outputs a control signal S _S (select signal S _S ) for operating the backup circuit 2 when it becomes negative.

[0028]

When the microcomputer system 1 runs out of control or fails, the WDT 6 that cannot obtain the pumping signal FIN repeatedly activates the initial signal INIT.

The delay time T _d3 from when the pumping signal FIN cannot be obtained until the initial signal INIT becomes active (“H” level) is a unique value determined by WDT 6. Also, the delay time T _d4 from when the pumping signal FIN is obtained until the initial signal INIT becomes non-active (“L” level) is also WDT 6
It is a unique value determined by.

Therefore, it is possible to obtain a stable control signal S _S from the backup control unit 10 along with the operation of WDT 6, and the switching between the microcomputer system 1 and the backup circuit 2 is performed in accordance with the operation of WDT 6. It can be done smoothly. Also, the delay time T _d3 , T _d4
Since it is not necessary for the backup control unit 10 to manage the above, the backup control unit 10 can be configured with a simple logic.

[0031]

EXAMPLES Next, examples of how the data processing apparatus according to the present invention can embody a backup control unit will be described.

(1) First Embodiment FIG. 2 is a circuit diagram for explaining the configuration of the first embodiment.

1) Configuration That is, the low active initial signal INIT is ANDed
Gate G₁₁Input to one input terminal of the AND gate G
₁₁Buffer output signal of BF₂Through the other input end
To enter. Also, pull up the input to "H" level.
Buffer BF ₁The output signal of the AND gate G₁₁
Input to the other input terminal of. In addition, AND gate G₁₁Out of
Force signal is select signal S_SIs.

Then, the buffers BF ₁ and BF _{2 are}
The through control is performed by the pumping signal FIN. The through control of the buffer BF ₂ is low active. 2) Operation In the first embodiment, the select signal S _S is at “H” level when the microcomputer system is operating normally, and is at “L” level when the microcomputer system is operating abnormally. Become.

When the microcomputer system is operating normally, that is, in this case, a low active initial signal
Since INIT is at “H” level, when the pumping signal FIN becomes “H” level, the buffer BF ₁ is activated and both inputs of the AND gate G ₁₁ become “H” level, and its output signal, that is, the select signal S _S It becomes "H" level.

After that, the pumping signal FIN is set to "L" level.
When it comes to the buffer, the buffer BF₂Is activated and AND gate G₁₁
Output signal S_SWill return. Therefore, the AND gate
G₁₁ Both inputs continue to be at "H" level.

When the microcomputer system is out of order, that is, in this case, the low-active initial signal
INIT goes to "L" level. Therefore, the pumping signal FI
Even if N becomes "H" level and the buffer BF ₁ operates,
Since the initial signal input to the AND gate G ₁₁ is at “L” level, its output signal, that is, the select signal S
_S also becomes "L" level.

After that, when the pumping signal FIN becomes "L" level and the buffer BF ₂ operates, the AND gate G
Output signal S _{S 11} is fed back to the input of the AND gate G _11. Therefore, both inputs of the AND gate G ₁₁ are at “L” level, and the output signal thereof, that is, the select signal S _S is still at “L” level.

(2) Example-2 FIG. 3 is a diagram for explaining Example-2, (a) is a circuit diagram for explaining the configuration, (b) is a truth table for explaining the operation, and (c) is a circuit diagram. Is a waveform diagram showing an initial signal, (d) is a waveform diagram showing a pumping signal, (e) is a waveform diagram of a Q output signal of a latch, and (f) is a waveform diagram of a negative logic Q output signal. In addition, (c) (d) (e) (f)
The time axes of are the same.

1) Structure This embodiment-2 is a general logic IC "74" (for example,
This is an example in which SN7474 manufactured by TI Co., Ltd. is used as the latch 11, and a low active initial signal INIT is input to the negative logic preset input terminal PR, and a pumping signal FIN is input to the clock input terminal CK.

The negative logic clear input terminal CLR is pulled up to "H" level and the delay input terminal D is pulled down to "L" level. The control signal (select signal) for operating the backup circuit is obtained from the Q output terminal or the negative logic Q output terminal.

2) Operation In the circuit of the second embodiment, as can be seen from the truth table of FIG. 3B, the latch 11 preset by the initial signal INIT is inverted to the D input by the pumping signal FIN. Works.

That is, as illustrated in FIGS. 3C to 3F, when the pumping signal FIN stops and the initial signal INIT becomes the “L” level, that is, active at time t ₂₀₁ , the Q output of the latch becomes “L”. H "level. Further, the negative logic Q output becomes "L" level.

While the pumping signal FIN is stopped, the WDT (not shown) works to initialize the initial signal IN.
IT becomes active repeatedly. However, the Q output once preset holds the "H" level.

[0045] On the other hand, the so pumping signal FIN is obtained at time t _202, Q output of the latch is set to the "L" level. Further, the negative logic Q output becomes "H" level.
Note that after time t _202, exhibits an initial signal INIT is at the "H" level or inactive state, the Q output and a negative logic output Q of the latch will not be reversed.

That is, the control signal for operating the backup circuit can be activated only when the microcomputer system fails.

[0047]

As described above, according to the data processing apparatus of the present invention, the backup controller for switching between the microcomputer system and the backup circuit can be realized with a simple structure. Moreover, since the switching timing is regulated by the operation of the WDT, the switching can be performed at the optimum timing. As a result, an inexpensive and highly reliable data processing device can be realized.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the basic principle of the present invention, in which (a) is a block diagram for explaining the configuration of a data processing device, (b) is a waveform diagram of a pumping signal, and (c) is a waveform diagram of an initial signal.
(d) is a waveform diagram of the select signal.

FIG. 2 is a circuit diagram illustrating a configuration of a first embodiment.

3A and 3B are diagrams illustrating the second embodiment, in which (a) is a circuit diagram illustrating the configuration, (b) is a truth table illustrating the operation, (c) is a waveform diagram showing an initial signal, and (d) ) Is a waveform diagram showing the pumping signal, (e) is a waveform diagram of the Q output signal of the latch, and (f) is a waveform diagram of the negative logic Q output signal.

FIG. 4 is a block diagram illustrating a configuration example of a data processing device including a backup circuit.

FIG. 5 is an excerpt of a circuit diagram illustrating an example of a WDT circuit.

6A and 6B are waveform diagrams for explaining the operation of the WDT circuit shown in FIG. 5, in which (a) is a waveform diagram showing a pumping signal, (b) is a waveform diagram of input voltage of a comparator, and (c) is a waveform diagram of initial signal. ,.

FIG. 7 is a diagram for explaining the configuration and operation of the backup control unit, (a) is a block diagram showing an example of the configuration, (b) and (c) are waveform diagrams showing the operation when the pumping signal is stopped, (b)
Is a waveform diagram showing the pumping signal, (c) is a waveform diagram showing the select signal, (d) and (e) are waveform diagrams showing the operation when the pumping signal becomes available, and (d) is the pumping signal. FIG. 4E is a waveform diagram showing a signal, and FIG. 6E is a waveform diagram showing a select signal.

[Explanation of symbols]

1 Microcomputer system 2 Backup circuit (backup system) 3,3a Switching unit 4 Controlled device 5,10 Backup control unit 6 WDT (Watch Dog Timer) 7 Counter unit 8 Judgment unit 9 Timer unit (division counter) 11 Latch FIN pumping signal INIT initial signal S _S select signal CLK internal clock S _C count signal (count value) of the counter S _pd determination control signal R ₁ to R ₇ resistor C ₁ -C ₃ capacitor Tr ₁ to Tr ₈ transistors CMP ₁ ~ CMP ₆ Comparator CC _{1 to} CC ₃ Constant current source G ₁ OR gate G ₂ , G ₁₁ AND gate INV inverter BF ₁ , BF ₂ buffer

Claims (1)

[Claims] 1. A cyclically active pumping signal (FIN) is generated in a microcomputer system (1), while the microcomputer system (1) is reset when the pumping signal (FIN) stops. WDT that repeatedly activates the initial signal (INIT)
In a data processing device including a (Watch Dog Timer) (6), when the microcomputer system (1) fails, a backup circuit (2) that performs replacement processing of the microcomputer system (1) is provided, and The pumping signal (FIN) stops and the initial signal (INI
A data processing device comprising a backup control unit (10) which outputs a control signal (S _S ) for operating the backup circuit (2) when T) is repeatedly activated.