JPH05312914A - Ic tester - Google Patents

Abstract

PURPOSE:To obtain an IC tester, which can maintain the state of a certain test waveform for a certain pin of a DUT. CONSTITUTION:A control signal, which indicates the presence or absence of the holding of a generated waveform, is added to one of the pattern data of a pattern generator 12. The control signal is received with a timing-pulse generating circuit 22, and the first pulse signal and the second pulse signal are stopped. Therefore, a waveform generating circuit can maintain the present waveform generating state. As a result, various waveform states can be simply set in response to the respective pin. This state can be maintained. Or under the intact state, wherein the present waveform is maintained, the next test can be continued. Various functional tests can be also performed, and the memory capacity of the pattern generator 12 need not be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester,
More specifically, the present invention relates to an IC tester that can set a test waveform to a specific waveform state and maintain the state.

[0002]

2. Description of the Related Art In an IC inspection system, a test waveform pattern of a plurality of bits required for performing IC performance and function tests is automatically generated in accordance with a test pattern program or the like. Conventionally, in such a test waveform pattern generating device, a pattern generator of a microprogram type algorithmic pattern generating type is generally used. Then, the pattern data is shaped by the waveform formatter corresponding to the IC pin by the pattern data generated on the side of the pattern generator and the clock pulse generated by the timing clock generator, and sent to the drive circuit. On the drive circuit side, the output received from the waveform formatter is level-converted, level-shaped, and sent to a predetermined IC pin.

On the other hand, the applicant of the present invention is
Instead of using the pattern generator to generate a pattern, the waveform formatter is provided with a waveform generation memory and part of the data from the pattern generator is used as address data in the waveform generation memory. A clock selection type waveform generator that accesses the generation memory to generate waveform generation data, selects the clock of the timing clock generator by the waveform generation data, and generates test waveforms by flip-flops according to this selection. Japanese Patent Application No. 62-327755 (JP-A 1-1676)
No. 83) has been filed.

[0004]

By the way, in an MPU, various gate arrays, etc., a memory and a logic circuit are mixed. When testing this type of LSI, the test is often performed in a state in which no waveform is applied to other built-in logic circuits during the memory test. Further, when trying to generate a very long test pattern, the program of the test pattern cannot be loaded into the pattern generator at one time, and the test program must be divided and loaded. Sometimes it is necessary to test the first loaded test pattern and then load and test the program again for the remaining test patterns.

When the former memory and the logic circuit are mixed, it is necessary to maintain the applied waveform of a certain pin in a specific state and give the required waveform to another pin. The test state of 1 is independent from the next test state, and the test state does not continue. Therefore, in the former case, processing such as setting a specific waveform corresponding to the pin or switching the mode to a specific waveform mode (for example, fixed waveform mode) is performed. In the latter case, it is more practical to carry out a more reliable test by maintaining the waveform in the state tested immediately before and executing the subsequent test. In order to meet these demands, simply, a large storage capacity of the program in the pattern generator may be adopted so that a large number of patterns can be continuously generated for various tests.

However, the increase in the memory capacity for storing the test program of the pattern generator complicates the internal circuit, hinders high-speed processing, and enlarges the device. Further, there is a problem that the test program itself becomes large and the load time thereof increases to lower the test efficiency. The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide an IC tester capable of maintaining the state of a certain test waveform for a pin having a DUT and performing the next test.

[0007]

The features of the IC tester of the present invention that achieves such an object are that a plurality of patterns having different phases from a pattern generator for generating a control signal for holding or not generating a waveform together with test pattern data. Corresponds to the timing clock generator that generates each clock pulse in a predetermined cycle, and the multiple bits corresponding to the rising edge of the generated waveform and the falling edge of the generated waveform that are assigned to each phase of the multiple clock pulses. A waveform generation memory that stores data having a plurality of bits to be accessed and that is accessed by at least a part of the pattern data;
Each of a plurality of bits of data is received as a gate signal from the waveform generation memory and a specific clock pulse is obtained from the clock pulse of each phase corresponding to each of the rising edge and the falling edge of the generated waveform. A timing pulse generation circuit for respectively generating a first pulse signal and a second pulse signal, receiving a control signal, and stopping the generation of the first pulse signal and the second pulse signal when this is in a state of holding the generated waveform. And a waveform generating circuit that raises or lowers the generated waveform according to the first pulse signal and lowers or raises the generated waveform according to the second pulse signal and outputs the generated waveform.

[0008]

As described above, the control signal indicating whether the generated waveform is held or not is added to one of the pattern information of the pattern generator, and the control signal is received by the timing pulse generation circuit to generate the first pulse signal and the second pulse signal. If the pulse signal is stopped, the waveform generation circuit maintains the current waveform generation state. Therefore, various waveform states can be easily set for each pin and maintained, or the next test can be continued while maintaining the current waveform. As a result, various functional tests can be performed and the memory capacity of the pattern generator does not need to be increased only by adding a signal indicating the presence or absence of the waveform hold to a part of the generated pattern data.

[0009]

1 is a block diagram of an embodiment of an IC tester of the present invention, FIG. 2 is a timing chart for explaining its waveform generating operation, and FIG. 3 is a timing for generating waveform hold control. It is a chart. In FIG. 1, reference numeral 10 denotes a CPU, which sets a program required for pattern generation in the pattern generator 12 through the interface 11 and sets timing generation data required in the timing clock generator 13. The data from the pattern generator 12 and the timing clock generator 13 are sent to the respective waveform formatters of the waveform generator 17, the output of the waveform formatter is input to the driver circuit of the pin electronics 18, and the test is performed via this drive circuit. Waveforms etc. are output corresponding to the pins of the DUT 19.

The number of bits of the pattern data signal input from the pattern generator 12 to each waveform formatter is assumed to be k + 2 bits here. The k + 1 bits of A _{0 to} A _k are used as address data for accessing the waveform generation memory 21 (described later) provided in each waveform formatter, and another 1 bit as a control signal for controlling each circuit, D _i is a waveform. It is added to the hold signal register 24 (described later), and this becomes the generated waveform hold control signal.

Reference numerals 17a, 17b, 17c, ... Are waveform formatters of the waveform generator 17, and 6a, 6
Reference numerals b, 6c, ... Are drive circuits for receiving the waveform patterns output from the respective waveform formatters. Here, since the waveform formatters have almost the same configuration, the waveform formatter 1 is representative of them.
7a shows a specific internal configuration thereof, and hereinafter, the configuration and operation will be described with the waveform formatter 17a as a representative, and the other components will be omitted. A test voltage setting circuit 20 generates data such as a bias voltage of the DUT 19 and data for setting the level of a test pattern according to the data from the CPU 10,
It is supplied to the pin electronics 18, etc., respectively.

The pattern data generated from the pattern generator 12 and the clock pulse of each phase of the timing clock generator 13 are respectively supplied to the waveform formatters 17a and 17a.
17b, 17c, ..., respectively. Then, some of the pattern data is input to the waveform formatter 17a, k + 1 bit of the signal is applied as an address signal of the address input terminals A ₀ to A _K of the waveform generation memory 21 of the waveform formatter 17a.

Here, the address signal applied to the waveform generation memory 21 is k + 1 bits (k is an integer of 1 or more), but in reality, it is, for example, several bits of the pattern data. A few bits access a specific address of the waveform generation memory 21, and the data read from the address is sent to the timing pulse generation circuit 22.

The timing pulse generating circuit 22 receives the data from the waveform generating memory 21 and the clock pulses sent from the timing clock generator 13 and having different phases, and logically ANDs these data with the clock pulse. Under the condition, a rising pulse signal and a falling pulse signal are generated and sent to the set terminal S and the reset terminal R of the flip-flop 23, respectively.

The timing pulse generating circuit 22 has three-input AND gates 22a and 22a for generating a rising pulse which receive the clock pulses of the respective phases obtained from the timing clock generator 13 at their second inputs.
b, 22c, ... And three-input AND gates 22n, 22m, 22l, ... For generating falling pulses that receive clock pulses of respective phases at their second inputs.
It consists of and. And the first of each AND gate
Of the AND gate corresponding to the phase to which each of the bit signals of the data read from the waveform generation memory 21 is assigned.
Has been entered in the input. Note that the Q input of the waveform hold signal register 24 (Q inverted output side, hereinafter Q bar) is input to the third input.

As a result, the waveform hold signal register 24
When the Q bar output of is at "1" or HIGH level (hereinafter "H") (in normal test state)
In this case, it has a 2-input logic. That is, when both the clock pulse of a certain phase and each bit of the digit corresponding to that phase of the waveform generation memory 21 become "1" corresponding to the rising and falling of the generated waveform, the phase A clock pulse is selected for the corresponding A
A rising pulse signal (TR) or a falling pulse signal (TF) is generated as the output of the ND gate.

The rising pulse signal (TR) and the falling pulse signal (TF) are generated in response to the clock pulse selected by each data bit, and are applied to the set terminal and the reset terminal of the flip-flop 23. The Q output of each flip-flop 23, which is sent out, is made to rise or fall in accordance with the pulse signal on the input side. Then, the Q output is output to the drive circuit 6a as a test waveform pattern, and is output to the DUT 19 via the drive circuit 6a.

The waveform hold signal register 24 is composed of a flip-flop, and the timing clock generator 13 is provided.
The test rate signal RP obtained from the pattern generator 1 is received at its clock terminal CK, and the 1-bit data D _i of the pattern data from the pattern generator 12 is received at its data terminal D.
Take in data D _i from 2. Then, the Q-bar output is supplied to the AND gates 22a, 22b, 22c, ... And the AND gates 22n, 22m, 22l ,. This makes it possible to select the mask control for each test rate. In the normal test state, the D _i bit of the pattern data is set to "0". Therefore, the waveform hold signal register 24 is set to "0" and the Q bar output is "1". Therefore, each AND gate becomes a 2-input gate whose output is irrelevant in a normal test state. However, when the D _i bit of the pattern data becomes “1”, “1” is set in the waveform hold signal register 24. As a result, the Q-bar output becomes "0" (= LOW level, hereinafter "L"), each AND gate is closed, and the Q output of the flip-flop 23 maintains the current waveform state.

The data stored in the waveform generating memory 21 is data for determining the rising or falling timing of the waveform to be generated. The structure of one data includes a bit data group allocated to each phase of the timing clock generator 13 corresponding to the rising edge of the generated waveform and a bit data group similarly allocated to each phase corresponding to the falling edge. It consists of a group of bit data. Such data is preset from the CPU 10 via the interface 11 before or at the start of the test, and the rising and / or falling of the generated waveform depends on the contents of the set data. It can be set freely.

Therefore, data corresponding to the waveform mode required for the test is set in advance in the waveform generation memory 21 from the CPU 10, and the waveform generation memory 21 is accessed in accordance with the pattern data generation timing of the pattern generator 12. A wide variety of waveforms can be generated from the flip-flop 23 in real time.

Now, assume that the number of clock pulses having different phases generated from the timing clock generator 13 is three, and the unit of data read from the waveform generation memory 21 is 6 bits (corresponding to the clock pulse of each phase). 3 bits on the rising side and 3 bits on the falling side). FIG. 2 shows the relationship between the generated pattern waveform and the generated waveform mode in the flip-flop 23 under these conditions.
A description will be given according to (a) and (b).

FIG. 2A shows the case where the generated waveform pattern is converted into RZ, and the original data pattern to be generated is shown in FIG. The three clock pulses generated from the timing clock generator 13 are ACLK, BCLK and CCLK of (b), (c) and (d).
And the RZ waveform for the data pattern (a) is shown in (e). Shown in (f) is the 6-bit data stored in the address accessed by the signal from the pattern generator of the waveform generation memory 21. Then, the signal of the seventh digit shown in (g) corresponds to the signal of the previous data D _i and is added to the waveform hold signal register 24. This is currently "0" (=
"L"). Waveform hold signal register 24
Can be set to "0" or "1" for each test cycle by the data D _i from the pattern generator 12. When this is set to "0", the Q bar output is "1" (= "H"). ). Therefore, as described above, each AND gate has two irrelevant outputs.
It is an input gate.

As is clear from this timing chart, when the pattern data of (a) is "1", in order to generate the RZ pulse signal corresponding to this, BCLK is set as the rising timing and CCLK is set as the falling timing. It can be seen that a waveform can be generated as. Further, when the pattern data is "0", it is only necessary to select three clock pulses. This is shown in (f) (100
It becomes 6-bit data of (010) and (000000).

At (100010), the output of the lower-order second bit Q ₁ and the output of the most-significant bit Q ₅ are "1", whereby each of the above clocks is selected. .. In other words, here, of the 6-bit data stored in the waveform generation memory 21, 2
Bits at each digit position of ⁰ , 2 ¹ , 2 ² are ACLK,
It is assigned to the rising timing bits of BCLK and CCLK, and when the corresponding bits are set to "1", the rising pulse signal (TR) is generated from the timing pulse generating circuit 22, and the corresponding bit is set to "0". When "", the rising pulse signal is not generated. Similarly, of 6-bit data, 2 ³ , 2
The bits at each digit position of ⁴ and ²⁵ are ACLK and BCLK, respectively.
, CCLK falling timing bits. Then, when the bit corresponding to these is set to "1", the falling pulse signal (TF) is generated from the timing pulse generating circuit 22, and when the corresponding bit is "0", the falling pulse signal is generated. Will not occur.

When each bit position of the data is assigned in correspondence with the clock pulse in this way, FIG.
If the data (100010) shown in (f) is stored at a specific address of the waveform generation memory 21, the RZ of the RZ shown in (e) of the figure corresponding to the pattern data “1” is accessed by accessing that address. Waveforms can be generated. If the data (000000) is stored in another specific address of the waveform generation memory 21, the RZ waveform corresponding to the pattern data “0” shown in FIG. Can be generated.

FIG. 2B shows a case where a so-called RTWC (real-time waveform control) waveform is generated in the real-time mode, and the data pattern is as shown in (A) in the same manner as described above. , Three clock pulses generated from the timing clock generator 13 are ACLK, BCLK, and C of (b), (c), and (d).
CLK, and (e) shows the RTWC waveform for the data pattern (a). Then, (f) is the 6-bit data of the waveform generation memory 21. Note that “N” in (a) means “0” data pattern in the specific measurement state, and “P” means “1” data pattern in the specific measurement state. Waveforms of different forms can be subsequently generated in real time according to the data patterns "0" and "1". The data D _i of (g) is
It is “0” (= “L”).

In the example shown in FIG. 2C, for example, the data D _i shown in (G) for the waveform of a certain pin is "1" (= "H") corresponding to the fourth data in (b). ) Is an example of the case. At this time, "1" is set in the waveform hold signal register 24 and the Q bar output is "0" (=
"L") and each AND gate is closed at its output. After that, unless the data from the pattern generator 12 becomes "0", in other words, the waveform hold is not released, the AND gate remains closed.
The data D _i can be set to “1” by accessing a specific address inside the pattern generator 12.

As a result, the waveform of (e) in FIG. 2 (b) maintains the same waveform as the third waveform generation data at this pin regardless of the generation pattern as shown in FIG. 2 (c). Continue. Next, the data D from the pattern generator 12
_{When i} becomes “0” and “0” is set in the waveform hold signal register 24, in other words, when the waveform hold is released, the AND gate is opened again, and the rising pulse signal ( TR
), A waveform corresponding to the falling pulse signal (TF) is generated from the flip-flop 23.

In this way, when necessary, it is possible to shift to the next test cycle while maintaining the waveform state of the previous test cycle. Another test program can be loaded to take over from the immediately preceding waveform application state and perform the next test. Further, it becomes possible to test one input pin by applying various waveforms to another input pin while maintaining a specific waveform state.

Here, for example, as shown in FIG.
The data (f) of (b) and (c) are stored in different address areas of the memory, and the address information of the upper digit when accessing the waveform generation memory 21 in the pattern data is "1" or "0". The desired waveform can be generated by switching to or.

As described above, in the embodiment, the signal is handled by the positive logic, but the signal may be handled by the negative logic, and the timing pulse generating circuit has a logic in which the data and the clock pulse are valid. If the product condition is positive or negative, these may be mixed. Therefore, the logic circuit can take various forms. Further, in the embodiment, the rising pulse signal of the timing pulse generating circuit is input to the set terminal of the flip-flop and the falling pulse signal is input to the reset terminal of the flip-flop, but this may be input in reverse. It is possible to generate an inverted waveform. The flip-flop is not limited to this, and a general waveform generation circuit can be used. Further, it goes without saying that the waveform generation memory includes a memory composed of registers.

In the embodiment, the description has been centered on the application pattern for the DUT, but it goes without saying that this can be similarly applied to the case of generating an expected value. Also,
The pattern data generated by the pattern generator includes various data such as various address data generated by the address generator provided inside the data generator, data related to the output waveform of the data generator, data related to pin connection restrictions, and address scramble data. Of course, it is included.

[0033]

As can be understood from the above description, in the present invention, a control signal indicating whether or not the generated waveform is held is added to one of the pattern information of the pattern generator, and this control signal is used as the timing pulse. First received by the generation circuit
Since the pulse signal and the second pulse signal are stopped, the waveform generation circuit can maintain the current waveform generation state. As a result, various waveform states can be easily set for each pin and maintained, or the next test can be continued while maintaining the current waveform. In addition, various functional tests are possible, and it is not necessary to increase the memory capacity of the pattern generator.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an IC tester of the present invention.

FIG. 2 is a timing chart for explaining the waveform generating operation.

FIG. 3 is a timing chart of generated waveform hold control.

[Explanation of symbols]

12 ... Pattern generator, 6, 6a, 6b, 6c ... Drive circuit, 10 ... CPU, 11 ... Interface, 13 ...
Timing clock generator, 17 ... Waveform generator, 17
a, 17b, 17c ... Waveform formatter, 18 ... Pin electronics, 19 ... Device under test (DUT), 2
0 ... Test voltage generation circuit, 21 ... Waveform generation memory, 22
... Timing pulse generation circuit, 24 ... Waveform hold signal register.

Claims (1)

[Claims] 1. A pattern generator for generating a control signal for holding or not generating a waveform together with test pattern data, a timing clock generator for generating a plurality of clock pulses having different phases in a predetermined cycle, and the plurality of clocks. Data having a plurality of bits corresponding to the rising edge of the generated waveform and a plurality of bits corresponding to the falling edge of the generated waveform, which are respectively assigned corresponding to respective phases of the pulses, is stored, and at least a part of the pattern data is stored. A waveform generation memory to be accessed and a plurality of bits of the data are received as gate signals from the waveform generation memory, and a specific clock pulse is generated from the clock pulse of each phase at each of rising and falling edges of the waveform. Correspondingly obtained and correspondingly to the first pulse signal and the second A timing pulse generating circuit for respectively generating pulse signals, receiving the control signal, and stopping the generation of the first pulse signal and the second pulse signal when the waveform signal is held, and a first pulse signal An IC tester comprising: a waveform generation circuit which raises or lowers a generated waveform in response to the second pulse signal, and lowers or raises the generated waveform in response to a second pulse signal.