JPH05312835A - Trigger device of digital oscilloscope - Google Patents

Abstract

PURPOSE:To provide a trigger device which detects difference in time between trigger points with high precision in a digital oscilloscope. CONSTITUTION:When an analog signal is input, trigger is detected in a first trigger circuit 5 from trigger pick-off output of a preamplifier 2. Jitter of a trigger signal and sample clock which is generated in a clock control section 6 is detected in a first jitter detection circuit 12. When a certain delay is obtained in a delay circuit 9, trigger is detected in a second trigger circuit 6 from trigger pick-off output of the preamplifier 2. Jitter of the trigger signal and sample clock is detected in a second jitter detection circuit 13. The sequence of first and second trigger circuits 5, 6 is controlled in a trigger control circuit 7. The detection of jitter of both triggers is done independently, and difference in time between both points on which trigger is applied by both of jitter values and delay time of the delay circuit 9 is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a cycle of an analog signal,
The present invention relates to a trigger device of a digital oscilloscope used for measuring rise time and the like.

[0002]

2. Description of the Related Art A digital oscilloscope detects a trigger of an analog signal after a certain period of time, triggers the analog signal, and stores A / D converted data in a memory.
It is supposed to be displayed.

FIG. 3 shows the configuration of a conventional trigger device for a digital oscilloscope. In FIG. 3, 1 is an attenuator that attenuates an analog signal, 2 is a preamplifier that amplifies the attenuated analog signal, 3 is an A / D converter that converts the amplified analog signal into a digital signal, and 4 is The data memories 5 and 6 for storing the converted data perform the trigger detection by the trigger pick-off output from the preamplifier 2 and output the trigger signal, and the first and second trigger circuits, and 7 indicate the first and the second triggers. A trigger control circuit that controls the circuits 5 and 6, 8 is a clock control unit that generates a sample clock, 9 is a delay circuit that is activated by the control of the trigger control circuit 7, and outputs a delay signal to the trigger control circuit 7.
Reference numeral 10 is a jitter detection circuit that detects jitter from the trigger signal output from the first trigger circuit 5 or the second trigger circuit 6 and the sample clock generated by the clock control unit 8, and 11 is the first trigger. A switch that selectively inputs the trigger signals of the circuit 5 and the second trigger circuit 6 to the jitter detection circuit 10, and is controlled by a CPU (not shown).

The above structure will be described in more detail below together with its operation. The attenuator 1 and the preamplifier 2 convert the analog signal into an appropriate size, and the A / D converter 3 converts the analog signal into a digital signal and stores it in the data memory 4.

Now, when the trigger circuit 6 is set to free run before data input, the CPU sets the switch 11 to connect the first trigger circuit 5 and the jitter detection circuit 10. And after the analog signal is input as above,
The trigger control circuit 7 counts the sample clock generated by the clock control unit 8. When the trigger control circuit 7 takes in the pre-trigger data, it outputs the trigger enable signal to the first trigger circuit 5 and activates the delay circuit 9. As a result, the first trigger circuit 5 detects the trigger by the trigger pickoff output from the preamplifier 2,
The trigger signal A is output. The trigger signal A is input to the jitter detection circuit 10 via the switch 11, and the jitter detection circuit 10 detects the jitter with the sample clock.
When the trigger control circuit 7 receives the delay end signal from the delay circuit 9, it outputs a trigger enable signal to the second trigger circuit 6. As a result, the second trigger circuit 6 starts the trigger detection by the trigger pickoff output from the preamplifier 2 and outputs the trigger signal B by the trigger detection. Since the switch 11 connects the second trigger circuit 6 and the jitter detection circuit 10 under CPU control except for the above free run, the jitter between the trigger signal B output from the second trigger circuit 6 and the sample clock is detected. To do. When the trigger control circuit 7 captures the post-trigger data by counting the sample clocks, it terminates the data capture.

As described above, in the above conventional trigger device for the digital oscilloscope, since one jitter detecting circuit 10 is switched and used, the first and second trigger circuits 5,
Only the jitter of one of the trigger signals of 6 can be detected, and the time difference between the above trigger points A and B is measured by the time difference between sampling points close to the trigger point.

[0007]

However, in the above-mentioned conventional trigger device for the digital oscilloscope, since the sampling points are discrete points, the time difference between the trigger points detected by the first and second trigger circuits 5 and 6 is measured. However, there is a problem that an error of up to twice the cycle of the sample clock occurs.

The present invention solves such a conventional problem, and not only corrects the jitter of the waveform display by detecting the jitter of two triggers by one-time data capture, but also between the two trigger points. It is an object of the present invention to provide a trigger device of a digital oscilloscope capable of detecting the time difference of 1 with high accuracy.

[0009]

In order to achieve the above-mentioned object, the present invention activates the first and second trigger circuits for detecting a trigger of an analog signal and the first trigger circuit for a predetermined time. Control means for controlling the second trigger circuit to be activated after the delay, and first and second trigger signals output from the first and second trigger circuits and the jitter of the sample clock, respectively. And the jitter detecting means of 1.

[0010]

Therefore, according to the present invention, the first and second
By independently providing the first and second jitter detection circuits for detecting the jitter of the trigger signal detected and output by the trigger circuit of, the jitter of two triggers during one data acquisition can be detected at the same time. Jitter correction for both triggers can be performed simultaneously, and the time difference between both trigger points can be detected from both jitter values and the delay time of the delay circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of a trigger device for a digital oscilloscope according to an embodiment of the present invention.

In FIG. 1, 1 is an attenuator for attenuating an analog signal, 2 is a preamplifier for amplifying the attenuated analog signal, 3 is an A / D converter for converting the amplified analog signal into a digital signal. Reference numeral 4 is a data memory for storing the converted data, 5 and 6 are first and second trigger circuits for performing trigger detection by the trigger pickoff output from the preamplifier 2 and outputting a trigger signal, and 7 is a first and a second trigger circuit. A trigger control circuit for controlling the trigger circuits 5 and 6 of 2;
Is a clock control unit for generating a sample clock, and 9 is activated by the control of the trigger control circuit 7,
A delay circuit for outputting a delay signal to the first trigger circuit; and 12 for detecting jitter from the trigger signal output from the first trigger circuit 5 and the sample clock generated by the clock control unit 8.
And a reference numeral 13 is a second jitter detection circuit for detecting jitter from the trigger signal output from the second trigger circuit 6 and the sample clock generated by the clock controller 8.

As described above, according to the present invention, one jitter detection circuit 10 is switched in the configuration in which the jitter detection circuit 12 of the first trigger circuit 5 and the jitter detection circuit 13 of the second trigger circuit 6 are independently provided. This is different from the above-mentioned conventional example in which switching is performed by 11.

The above configuration will be described in more detail below along with the operation thereof. The attenuator 1 and the preamplifier 2 convert the analog signal into an appropriate size, and the A / D converter 3 converts the analog signal into a digital signal and stores it in the data memory 4.

When the analog signal is input as described above and the data acquisition is started, the trigger control circuit 7
Counts the output of the sample clock generated by the clock controller 8. When the trigger control circuit 7 takes in the pre-trigger data, it outputs the trigger enable signal to the first trigger circuit 5 and activates the delay circuit 9.
As a result, the first trigger circuit 5 detects the trigger by the trigger pickoff output from the preamplifier 2 and outputs the trigger signal A to the first jitter detection circuit 12. The first jitter detection circuit 12 detects the jitter between the trigger signal A and the sample clock. When the trigger control circuit 7 receives the delay end signal from the delay circuit 9, it outputs a trigger enable signal to the second trigger circuit 6. As a result, the second trigger circuit 6 detects a trigger by the trigger pickoff output from the preamplifier 2 and outputs the trigger signal B to the second jitter detection circuit 13. The second jitter detection circuit 13 detects the jitter between the trigger signal B and the sample clock. When the trigger control circuit 7 captures the post-trigger data by counting the sample clock after the trigger signal B is generated, it outputs a data capture end signal and terminates the data capture. Then, the CPU (not shown) reads the jitter of the trigger signal A and the jitter of the trigger signal B held in the first and second jitter detection circuits 12 and 13,
Calculate the time difference between both trigger points.

FIG. 2 is an explanatory diagram of an example of calculating the time difference between both trigger points. In FIG. 2, a, b, c, d, e, f,
g is a sampling point, A is a trigger point of the trigger signal A,
B is the trigger point of the trigger signal. After the end of data acquisition, the sample points b and f are separated by four cycles of the sample clock. Therefore, if this is 4T, the jitter value of the A trigger is Aj, and the jitter value of the B trigger is Bj, the CPU is
The time difference between the A and B trigger points is calculated by (4T + Aj-Bj).

[0018]

As described above, according to the present invention, the first and second jitter detecting circuits for detecting the jitter of the trigger signal detected and output by the first and second trigger circuits are independently provided. By providing the jitters of two triggers during one data acquisition at the same time, the time difference between both trigger points can be detected by both the jitter values and the delay time of the delay circuit. Therefore, the time difference between both trigger points can be detected with high accuracy.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a trigger device of a digital oscilloscope according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of calculating a time difference between trigger points by the trigger device.

FIG. 3 is a schematic block diagram showing a trigger device of a conventional digital oscilloscope.

[Explanation of symbols]

 1 attenuator 2 preamplifier 3 A / D converter 4 data memory 5 first trigger circuit 6 second trigger circuit 7 trigger control circuit 8 clock control unit 9 delay circuit 12 first jitter detection circuit 13 second jitter detection circuit

Claims (1)

[Claims] 1. A first and a second trigger circuit for detecting a trigger of an analog signal, and a control for activating the first trigger circuit and activating the second trigger circuit after delaying for a predetermined time. A trigger device for a digital oscilloscope, comprising: a control unit for controlling the trigger signal, and first and second jitter detecting units for detecting the jitters of the trigger signal and the sample clock output from the first and second trigger circuits, respectively.