JPH0531240B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording and reproducing device for audio, etc.
The present invention relates to an electronic audio recording/reproducing device in which a recording/reproducing circuit, a memory circuit, a control circuit, etc. are integrated into one or several semiconductor integrated circuits.

Among audio or image recording and playback devices that can be played back immediately after recording, tape recorders and video tape recorders that use magnetic tape are widely used, but both use magnetic tape as the recording and playback head. Contains mechanically moving parts that run against each other. As a result, there are limits to the miniaturization and weighting of the device, and the number of parts increases, resulting in problems in manufacturing cost, mechanical reliability, and maintenance.

On the other hand, in the field of speech technology, the reproduction of speech using various methods of speech synthesis technology has been developed, and currently on the market are Texas Instruments' Speak and Spell (trademark) and several subsequent Speech synthesis devices are starting to appear.

Speech synthesis apparatuses known to date can be broadly classified into three types: formant synthesis, linear prediction (LPC), and waveform digitization. Normally, the first two methods require less memory capacity per unit time for audio playback, but they require large-scale equipment such as a large computer for audio recording and audio analysis, and are used as recording and playback devices. It is difficult to do so. In addition, in these two methods, audio parameters are often calculated based on a vocal tract model, and as a result, although they are suitable for reproducing human voices, they are considered inappropriate for reproducing sounds in the natural world. ing.

On the other hand, as a third waveform digitization method, the PCM method, which samples an audio waveform at the Nyquist frequency and converts it into a digital signal, and the delta modulation method, which is a variation thereof, are well known. This delta modulation method, which encodes one bit per sample, has the excellent feature of being able to communicate even when there are many code errors in the transmission path, so it is mainly used for special purpose digital communications. Advances in program control digital filters, motor remote control, audio scrambling,
Applications other than communication, such as various measuring instruments, are now being considered.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic audio recording and reproducing device that uses semiconductor memory and has no moving parts.

Another object of the present invention is to provide an electronic audio recording and reproducing device in which a semiconductor memory and a delta modulation circuit are integrated into a single semiconductor chip, and the delta modulation circuit can be used in both recording mode and reproduction mode. be.

Another object of the present invention is to provide a compact and lightweight recording and reproducing device that has the flexibility to be incorporated into objects of various shapes such as dolls and toys. That's true.

Another object of the present invention is to provide an audio recording/playback device that can effectively utilize semiconductor memory and record more content.

General Description of the Apparatus FIG. 1 shows a block diagram of an audio recording/reproducing apparatus 1 according to the present invention, and FIG. 2 shows a perspective view thereof. Human voices or sounds of the natural world (collectively referred to as audio)
A microphone 2, which enters the apparatus, is connected to a microphone amplifier 3. amplified microphone amplifier 3
The outputs are a delta modulator 4, a level detector 5, a control circuit 6, a random access memory (RAM) 7
The signal is then input to an audio recording/reproducing semiconductor chip 9 which has a built-in filter circuit 8. The main part of this audio recording/reproducing semiconductor device 1 is an electronic circuit constituted by one or several large-scale integrated circuits (LSI), the details of which will be described later. The audio analog signal reproduced by the audio recording/reproducing semiconductor chip 9 is amplified by the audio power amplifier 10 and sent to the speaker 1.
1 is output.

As shown in FIG. 2, a microphone 2, a microphone amplifier 3, an audio recording/reproducing semiconductor chip 9, an audio power amplifier 10, and a speaker 11 are connected to a battery power source (not shown), a switch 12 (power switch,
Single small plastic container 13 with record switch and playback switch
will be stored in. The container 13 can also be stored inside a stuffed doll or toy.

General Description of Recording and Reproducing Operations Before explaining the detailed configuration of the recording and reproducing apparatus 1 of the present invention, the recording and reproducing operations thereof will first be briefly explained.

Power switch and recording switch (switch 1
When audio enters the microphone 2 while one of the microphones 2) is on, the audio analog signal is amplified by the microphone amplifier 3, and the audio signal level detector 5 detects that the audio signal is at a predetermined level or higher. Once determined, the delta modulator 4 converts it into a digital signal. (Delta modulation will be explained later) The digitized audio data is sent to the control circuit 6.
The data is temporarily stored in random access memory 7 under the control of.

The playback operation is performed in response to operation of a playback switch (one of the switches 12). The audio data recorded in the random access memory 7 is given again to the delta modulator 4, where it is converted back into an analog signal, and after sampling noise is removed by the filter circuit 8, it is sent to the speaker 11 via the audio power amplifier 10. Output as audio.

Circuit Configuration and Operation for Audio Recording FIG. 3 shows details of the electronic circuit of FIG. 1, that is, the audio recording/reproducing semiconductor chip 9.

A switch 20 for recording audio and a switch 21 for reproducing audio are provided outside the semiconductor chip 9 and connected to the control circuit 6 through pins. An oscillator circuit for defining the cycle of operation within the semiconductor chip 9 is supplied to the control circuit 6 and other circuits through other pins.

The delta modulator 4 includes a first comparator circuit 22, a first gate 23, a sample & hold circuit 24, a pulse pattern detection circuit 25, a Silavik filter 26, a second gate 27, an amplifier 28, and an integration circuit 29. Contains. Delta modulator 4
The main parts can be integrated into an LSI semiconductor chip, and only parts that require large resistance and capacitance values can be externally attached depending on the design conditions.

To record audio data in the RAM 7, first turn on the power switch 30, apply a 9.0 volt power source 31 to the electronic circuit 9, and turn on the push button type recording switch 20. By operating this switch, the recording and reproducing device enters a recording standby state. That is, the control circuit 6 generates a recording signal in response to the recording switch 20, operates the first gate 23,
The output line 32 of the first comparison circuit 22 is connected to the input line 33 of the sampling/holding circuit 24, and at the same time, the RAM 7
The output line 34 from the sampling/holding circuit 24 is cut off from the input line 33 of the sampling/holding circuit 24. This state is the third
The first gate 23 in the figure is indicated by a solid line arrow. This first
The gate 23 can be constructed from a well-known MOSFET transfer gate circuit.

At the same time, the control circuit 6 opens the third gate 35 so that the output of the delta modulator 4 is not input to the filter circuit 8. By blocking the gate 35, howling between the speaker 11 and the microphone 2 can be prevented.

This recording standby state will be described in more detail with reference to FIG. A recording control circuit 41 used in the recording mode is shown in the upper frame of FIG. 4, and a reproduction control circuit 42 (described later) is shown in the lower frame. The recording control circuit 41 and reproduction control circuit 42 shown in FIG. 4 constitute the control circuit 6 shown in FIG. The same level detector 5 as in FIG. 3 is shown in the frame on the left,
It is connected to the recording control circuit 41.

When the recording switch 20 is turned on, the power supply voltage V _DD
(Logic “1”) is the first flip-flop (FF)
It is applied to data input D of circuit 43. first
FF43 is activated by the clock pulse (CP) signal.
The output Q is given to second FFs 44 and 45. The gate 45 receives the output Q of the first FF 43 and the opposite polarity output of the second FF 44, and detects that the recording switch 20 has been pressed.

FIG. 5 shows the first, second, and third FF43, 44,
46 and gate 45 are shown along with the clock pulse (CP). When the recording switch 20 is off (CP1 timing), the first FF4
The input and output of the second FF44 (shown as FF1D and FF1Q in FIG. 5) are both logic "0", and the output of the second FF44 (shown as FF2) is "1",
As a result, the output of gate 45 (denoted as G) is "1"
The output Q (indicated by FF3Q) of the third FF46 is "0".

The recording switch 20 is turned on, and FF43
When a logic "1" is input to the D input of the FF43 (timing of CP2), the Q output of the FF43 becomes "1", but at that time the FF44 maintains its previous state. At the next clock pulse (CP3 timing), FF4
The output of gate 45 becomes "0", and the output of gate 45 remains logic "0" for the time from CP2 to CP3.
Supply to FF46. The signal "1" of the Q output 47 of the FF 46 connects the first gate 23 in FIG.
Switching is performed so that the input line 33 of the holding circuit 24 is connected. Also, the third gate 3 of the filter circuit 8
5 is opened. Furthermore, the sampling/holding circuit 24
The fourth gate 50 is closed so as to close the output line 48 of the RAM 7 and the input line 49 to the RAM 7. The device is now ready for recording.

Returning again to FIG. 3, the explanation of the recording operation will be continued.
Setting and detecting the level of the audio input signal is performed by the level detector 5. This level setting and level detection function is important in the present invention. In this device using semiconductor memory, the memory must be used effectively. Do not record unnecessary sounds (including noise) that are input before or after the sound you want to record on the solid line. This level detector 5 is used to input and record audio data into the RAM 7 only when an input of a predetermined level or higher is received, and to make maximum use of the limited storage capacity of the RAM 7.

The level detector 5 includes a second comparator 54 that compares the input from the audio input terminal 51 with a voltage level set by a resistance divider (a fixed resistor 52 and an external semi-fixed resistor 53). . When the audio input is lower than the set voltage level, the second comparison circuit 54 outputs a logic "0" to the recording control circuit 4, as shown in FIG.
1, and prohibits the RAM operation operation of this recording control circuit 41.

When an audio input with a voltage level (1.0 to 1.5 volts) or higher set by the fixed resistor 52 and the semi-fixed resistor 53 enters the second comparator circuit 54, the logic "1" is output to the recording control circuit 41 in FIG. FF55 to switch it to recording mode.

Microphone 2 audio input (analog signal)
is amplified by the microphone amplifier circuit 3 and introduced into the first comparator 22 of the delta modulator 4. In the first comparison circuit 22, the audio input analog signal X(t) at time (t) is compared with digital data Y(t-1) at the previous time (t-1) in the sampling clock signal. , the result of the comparison is output on output line 32 in the form of a digital signal. Such a coding technique is called delta modulation. This delta modulation method itself is already known, and there are several types.

For delta modulation methods, see Electronics magazine
It is described in the October 13, 1977 issue, pages 86-96 (the corresponding paper is in the February 20, 1978 issue, pages 169-185 of Nikkei Electronics). A part of the recording/reproducing device of the present invention uses continuous variable slope delta modulation, which is a type of delta modulation and is used in telephones.
An adaptive delta modulation method called Variable Slope Delta (CVSD) modulation is employed.

Essentially, a delta modulator is a closed-loop sampled-data control system.
control system), which has a polarity determined by the difference between the input signal to be sampled (analog audio input in the case of the present invention) and the quantized approximation value immediately before (at the previous sampling clock). It outputs binary pulses. Linear delta modulation, one of the typical delta modulation methods, provides high S/N over a wide range of analog input signals.
The disadvantage is that the ratio cannot be maintained. In this device, it is preferable to use the above-mentioned CVSD modulation method in order to improve the S/N characteristics.

The audio analog input signal X(t), which is the input to be sampled, is input from an external microphone amplifier
It enters the first comparator 22 via Co. The signal (quantized approximation value of the previous input signal) Y(t-1) to be compared with this audio analog input is sent to the integrator 29
is similarly input to this first comparator 22.

The output line 32 of the first comparator 22 in FIG.
It is led to the input line 33 of the sampling and holding circuit 24.
At this time, that is, during the recording operation, this gate 23
The output line 34 of the RAM 7 and the input line 33 of the sampling/holding circuit 24 are cut off.

The first comparator 22 outputs a 1-bit word "1" when (1)X(t)>Y(t-1), and (2)X(t)≦Y(t-1).
1), a 1-bit word "0" is output. At this time, the length (pulse width) of the 1-bit word "1" or "0" is determined by the audio input signal and has a completely irregular length.

The audio input signal converted into a 1-bit word binary code by the first comparator 22 is converted into a clock pulse (CP).
is sampled in the sampling/holding circuit 24 and temporarily held there for an extremely short period of time.

FIG. 6 shows the first gate 23, the sampling/holding circuit 24, and the pulse pattern detection circuit 25. The sampling and holding circuit 24 receives from the data input (D) a 1-bit word sent from the first comparator 22 via the gate 23. At the same time, a clock pulse (CP) which is a sampling pulse is also given. The frequency of this sampling pulse can be selected from between 4KHz and 16KHz depending on the design conditions or use of the device.

2 sampled in each sampling pulse
The audio data in decimal code is passed from the Q output 48 of the sampling/holding circuit 24 through the gate 50 (FIG. 3).
It is sent to RAM7 and stored.

In order to simplify the semiconductor chip of this device, it is preferable to use a well-known shift register that can output in the order of input (so-called first-in-first-out format) for the RAM 7, and in this embodiment, it is approximately 10K bits. However, depending on the audio data capacity and application requirements, other types of storage means,
For example, the known circular shift register or the high speed shift register described in US Pat. No. 3,940,747 owned by Texas Instruments
It is also possible to adopt a RAM configuration. In addition, as will be described later, in addition to the semiconductor chip 9, there is also an expansion RAM.
You can also connect it to increase the storage capacity of audio data.

RAM7 is the fourth memory of the recording control circuit 41 in FIG.
It is operated by the Q output 56 (recording signal) of the FF 55. The fourth FF 55 allows audio input of a predetermined level or higher to be sent to the second
The output Q is not output until the comparator circuit 54 detects the
Recording operation of RAM7 is prohibited.

This audio data is simultaneously sent to the pulse pattern detection circuit 25 shown in FIGS. 3 and 6,
Here, it is detected whether the flow of audio data is continuous and of the same polarity. The detection circuit 25 of this device detects 3 sampled audio data of the same polarity.
It is designed to detect this and output a logic "1" and send it to the syllabic filter when the number is consecutive. That is, three consecutive sampled audio data E
(t-2), E(t-1), and E(t) are all “1” or all “0”, the detection circuit outputs “1” with a delay of 1 bit, and the other In this case, "0" is output. Sampling clock frequency is 16K
When the frequency is around Hz or below, it is most preferable to detect three pulse patterns, but when the frequency is high, the number of D-type flip-flop circuits can be changed to detect the flow of audio data of three or more pulse patterns. Can be detected. Generally speaking, the detection circuit 25 receives N (an integer) consecutive strings of sampled audio data from the sampling/holding circuit 24, holds them simultaneously (N=3 in this embodiment), and sequentially stores them one after another. Assuming that the received audio data string has the same polarity or the same logic (“1” or “0”) M (integer) times, it is detected that M≧N and (M-N+1) consecutive When M<N, a high level or "1" detection signal output is generated on the line by sending one bit, and a low level or "0" detection signal output is generated on the line when M<N.

The circuit surrounded by the broken line frame on the right side of FIG. 6 is the pulse pattern detection circuit 25 according to this embodiment.
D-type flip-flops 61 and 62
It includes a NAND gate 63 and a D-type flip-flop 64 that temporarily holds the detection signal.
D-type flip-flops 61, 62, and 64 are circuits that operate using a common clock path CP.

In Fig. 7, corresponding to the crop pulse CP,
The relationship between the output (COMP) of the first comparator 22, the output (S&H) of the sampling/holding circuit 24, and the output (PPD) of the pulse pattern detection circuit 25 is shown. Here, the output (S&H) of the sampling/holding circuit 24 is
It also corresponds to audio data stored in RAM7.
The output 65 of the pulse pattern detection circuit 25 is the third
The signal is applied to the next syllabi filter 26 shown in the figure. The syllabi filter 26 receives the output of the pulse pattern detection circuit 25 and generates a feedback signal Y(t) that is fed back from the integrating circuit 29 to the first comparator 22 in a form corresponding to the envelope of the audio input signal X(t). The voltages E (positive) and -E (negative) that control the step height are
occurs at the output terminal.

The output of the pulse pattern detection circuit 25 charges the capacitor C ₁ 72 connected between the resistor R ₁ 71 and the ground potential through the resistor R ₁ 71 connected to it, and the time constant of these R ₁ and C ₁ , waveforms of voltages E and -E (corresponding to the envelope of the audio input signal)
Create a rising curve. Further, the rise curves of the voltage E and -E waveforms are created by the time constant determined by the resistor _R2 73 and the capacitor _C1 . The falling curve is determined by the selection of the second gate 27.
It is created when the charge stored in C ₁ 72 flows through amplifier 28 to integrator 29 .

Generally, the envelope of an audio signal has a steep rising curve and a gentle falling curve. resistance 7
1 and 73, the time constant of the capacitor 72 is 5~
It is designed to be 10 msec, which is the same as the typical pitch period of voice. In some cases, the time constant can be as high as 100 msec to correspond to the syllable length of the speech. In this embodiment, a time constant corresponding to the pitch period is selected.

The positive voltage E is applied directly to the second gate 27 through a line 74, and the negative voltage -E is applied to the same gate 27 through another line 76, by inverting the positive voltage E through an inverter 75.

At the second gate 27, the positive voltage E and the negative voltage -
A selection of E is made. When the output of the sampling/holding circuit 24 is at a high level "1", the positive voltage E is selected, and conversely, when the output is at a low level "0", the negative voltage -E is selected.

Selected multi-value signal (positive voltage E or negative voltage -
E) passes through the amplifier 28 and the integrator 29 (resistance
R ₃ and capacitor C ₂ ). Integrator 29
The output of Y(t) is given to the first comparator as a feedback signal Y(t), and the above-described modulation operation is repeated. In the recording mode, since the third gate 35 is open, the delta-modulated audio signal is not provided to the filter circuit 8.

Circuit configuration and operation for audio reproduction The important features of the present invention are the CVSD modulator 4 and
The RAM 7 is used for audio reproduction as well as for audio recording.

A playback switch 21 shown in FIGS. 3 and 4 is connected to the control circuit 6 in the semiconductor chip 9 through a pin. The reproduction control circuit 42 shown in the lower frame of FIG.
It responds to the playback switch 21. Playback switch 21
When turned on, a high level signal is applied to the data input D of the fifth flip-flop (FF) circuit 81. The 5th FF81 is the clock pulse CP
As a result, the output Q is transferred to the next 6th FF82 and gate 8
Give to 3. The gate 83 receives the output Q of the 5th FF81.
and the reverse polarity output of the sixth FF 82 are obtained, and it is detected that the playback switch 21 has been pressed. seventh
The FF 84 temporarily holds the output of the gate 83 and provides a reproduced signal to its output line 85. Reproduction control circuit 4
The configuration of the reproduction control circuit 42 is basically the same as that of the recording control circuit 41 described above, and the signal relationship of the reproduction control circuit 42 can be understood by looking at the signal relationship diagram of FIG.

The recording control circuit 41 and the reproduction control circuit 42 are related to each other as shown in FIG. In order to prevent this from occurring, and conversely, in the reproduction mode, only the reproduction control circuit 42 operates and the recording control circuit 41 does not generate a recording signal. This configuration prevents interference between both modes and makes the operation of the device reliable and error-free.

The reproduction control circuit 42 generates a reproduction signal as an output line 85, changes the state of the first gate 23 in FIG. 3, and connects the output line 34 of the RAM 7 and the input line 33 of the sampling/holding circuit 24. and the first comparator 22
The input to the sampling/holding circuit 24 is cut off.

The reproduction signal opens the gate 50 and prevents the output 48 of the sampling and holding circuit 24 from being input to the RAM 7. This is to prevent the arrangement of the audio data stored in the RAM 7 from being changed. Further, the reproduced signal closes the third gate 35 of the filter circuit 8 and enables output to the speaker. Furthermore, the playback signal is
It also enables RAM output operation. When the address in the RAM 7 ends, an address end signal is input to MSTOP in FIG. 4, and the reproduction mode ends at FF84.

The binary encoded audio data stored in the RAM 7 in FIG.
The signal is supplied to a sampling/holding circuit 24, a pulse pattern detection circuit 25, a Silavik filter 26, a second gate 27, an amplifier 28, and an integrator 29 through the circuit. The CVSD modulation here is almost the same as the modulation in the recording mode. The difference from the recording mode is that the analog output of the integrator 29 is not returned to the first comparator 2 but is given to the filter circuit 8.

The filter circuit 8 is a well-known filter circuit including a buffer amplifier 91, a filter amplifier 92, peripheral resistors, capacitor circuits, etc., and removes sampling noise or quantization noise contained in the output from the integrator 29. . The analog audio output with a waveform smoothed by the filter circuit 8 is
Speaker 1 through audio power amplifier 10
Output from 1.

Expansion of audio data storage The audio data storage capacity of the RAM built into the semiconductor chip 9 in Figure 3 is
Can be expanded by adding RAM. FIG. 8 shows a configuration in which multiple external RAM chips are connected to the main semiconductor chip.

The main semiconductor chip 9 is the semiconductor chip shown in FIG. 3, and includes a delta modulator 4, a level detector 5, a control circuit 6, a RAM 7, a filter circuit 8, and the like. In FIG. 8, three external RAMs 101, 102, and 103 are shown. Each external RAM has internal memory in the main semiconductor chip.
It includes a RAM cell (or shift register M) for storing audio data similar to RAM, a control circuit for the RAM cell (or shift register), and a refresh circuit for the dynamic RAM (or dynamic shift register).

Main semiconductor chip 9 and external RAM 101, 10
2, 103 is the data input/output lead 10.
4. A clock lead 105, a lead 106 for a storage start signal, a lead 107 for a playback start signal, a lead 108 for a signal indicating the end of operation of a specific external RAM, and a lead 108 for a signal indicating the start of operation of a specific external RAM. The leads 109 and the like are connected in parallel as shown in FIG.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an audio recording/reproducing apparatus according to the present invention, and FIG. 2 is a perspective view thereof. Third
The figure is a detailed circuit diagram of the electronic circuit of FIG. 1, that is, the audio recording/reproducing semiconductor chip. FIG. 4 is a detailed circuit diagram of the control circuit for explaining the recording standby state. FIG. 5 is a timing diagram showing the logic states of the flip-flop circuit in FIG.
FIG. 6 is a circuit diagram showing details of the first gate, sampling/holding circuit, and pulse pattern detection circuit. FIG. 7 is a timing diagram of the output of the first comparator, the output of the sampling/holding circuit, and the output of the pulse pattern detection circuit. FIG. 8 is a wiring diagram showing the relationship between the audio recording/reproducing semiconductor chip and the external RAM. (Explanation of symbols), 1...Audio recording and playback device, 2
...Microphone, 3...Microphone amplifier, 4...
...Delta modulator, 5...Level detector, 6...Control circuit, 7...Random access memory (RAM), 8...Filter circuit, 9...Audio recording/playback semiconductor chip, 10...Audio power amplifier, 11 ...Speaker.

Claims (1)

[Scope of Claims] 1 (a) A/D conversion means for converting an analog signal into a digital signal; (b) storage means capable of storing the output of the A/D conversion means in the order of input; (c) ) D/A conversion means for converting the digital signal read from the storage means into an analog signal; (d) recording instruction means for instructing recording; and (e) a recording instruction has been issued by the recording instruction means. (f) writing control means for sequentially instructing the storage means to write data by detecting the recording command; (g) storage termination means for detecting when the write instruction has occurred and terminating the write instruction of the write control means; An audio storage/playback device comprising: readout control means for instructing readout;