JPH05307896A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve production yield by providing a selected-circuit and selecting an output from a redundant memory cell array in an initial condition when a defect bit saving storage circuit is not operated. CONSTITUTION:By the selected-circuit 5, the output is selected from the redundant memory cell arrays, 1-1 to 1-6 and outputted in the initial condition when the defect bit saving storage circuit 6 is not operated. In the initial condition, selectors 2-1 to 2-4 are controlled so as to output write data 102-105 by a selective signal 123. Further, the selectors 3-1 to 3-5 are controlled so as to output read data 110-114 by the signal 123. At this time, the write data 101-105 are written in the memory arrays 1-1 to 1-5 and the data are outputted from an output lines 116-120. Then a test containing the AC characteristic of the arrays 1-1 to 1-5 is performed before operating the storage circuit 6 and the yield after operating the circuit 6, e.g. after cutting a fuse is improved effectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a circuit for testing when a memory having a plurality of bits has redundant bits.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional example of the present invention. The memory arrays 1-1 to 1-5 are cell arrays of a normal memory, and the memory array 1-6 is an array of redundant memories, which constitute the memory 1 as a whole. Normally, the write data 101 to 105 are sent to the memory arrays 1-1 to 1-5 through the selectors 2-1 to 2-4. The data read from the memory arrays 1-1 to 1-5 is read as read data from the output lines 116 to 120 through the selectors 3-1 to 3-5. Further, each read data is collected in the selector 5 for testing the operation of each memory cell, and 1 bit is selected and read from the line 122. Here, if the test result shows that the memory array 1-3 is defective, for example, the relief information storage circuit 6 sends the write data 103 to 105 to the memory arrays 1-4 to 1-6. The signals control the selectors 2-3 and 2-4. Similarly, the read data is controlled by the selectors 3-3 to 3-5, and the memory array 1-4 is read.
The read data from 1 to 6 are sent to the output lines 118 to 120. As described above, the redundant memory arrays 1-6 are used to avoid the defective memory arrays 1-3.

[0003]

This conventional semiconductor memory device has a redundant memory array in addition to the normal memory array, but in the initial state (for example, a fuse circuit is used for the relief information storage means). Sometimes before testing the operation of the memory cells in the redundant memory array (before blowing the fuse). For this reason, when a defective cell exists in the redundant memory array, even if the memory array in which the defective cell exists is switched to the redundant memory array, the defective memory cell does not operate normally, and such defective product is detected by the conventional semiconductor memory device. Therefore, there is a problem that the yield of products is low.

[0004]

According to the present invention, a plurality of ordinary memory arrays, redundant memory arrays, defective bit saving storage means, and any memory array from the ordinary memory array and the redundant memory array can be provided. A semiconductor memory device having a selection circuit for selecting is obtained.

[0005]

In the test, since the selection circuit can select and output any output from the outputs of the normal memory array and the redundant memory array, the redundant memory array can be tested. Therefore, the redundant memory array including the defective cell is not recognized as a good product, and the manufacturing yield can be increased.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, the memory 1 includes normal memory arrays 1-1 to 1-5 and a redundant memory array 1-6. The write data 101 is connected to the normal memory array 1-1 and the selector 2-1. The write data 102 is the selectors 2-1 and 2-2.
Further, the write data 103 is the selectors 2-2 and 2-3.
Further, the write data 104 is the selectors 2-3 and 2-4.
Connected to each. The write data 105 is the selector 2-
4 and redundant memory arrays 1-6. The selectors 2-1 to 2-4 select one of the two inputs by the selection signal 123, and send it out from the output lines 106 to 109 as write data of the memory arrays 1-2 to 1-5.

The read data from the memory array 1-1 is sent to the selector 3-1. The read data 111 from the memory array 1-2 is the selectors 3-1 and 3-2.
The read data 112 from the memory array 1-3 to the selectors 3-2 and 3-3, and the read data 113 from the memory array 1-4 to the selectors 3-3 and 3-4.
Then, the read data 114 from the memory array 1-5 is sent to the selectors 3-4 and 3-5, respectively. The read data 115 from the redundant memory array 1-6 is sent to the selector 3-5 and the delay circuit 4. Selector 3
-1 to 3-5 select one of the two inputs by the selection signal 123, and the output is used as read data from the output lines 116 to 120, respectively. The same data is also sent to the selector 5. The output from the delay circuit 4 is sent from the output line 121 to the selector 5. The selector 5 selects one from the data on the output lines 116 to 121 and sends it out from the line 122. The relief information storage circuit 6 includes a selector group 2 (selectors 2-1 to 2-4).
And selector group 3 (selectors 3-1 to 3)
Control signals (including −5) on line 123.

An embodiment of the present invention having the above construction will be further described. First, in the initial state, the selector 2
It is assumed that -1 to 2-4 are controlled by the selection signal 123 so as to output the write data 102 to 105. It is also assumed that the selectors 3-1 to 3-5 are controlled by the selection signal 123 so as to output the read data 110 to 114. At this time, the write data 101 to 105 (that is, bits 0 to 4) are written in the memory arrays 1-1 to 1-5, and the data are output from the output lines 116 to 120. At this time, the redundant memory arrays 1-6 are not used.

FIG. 2 shows an example of the configuration of the rescue information storage circuit 6. The base of the transistor 8 is connected to one end of the fuse 7, and the collector is connected to the ground (GND) level,
The emitter is connected to one end of the resistor 9. Fuse 7
The other end of the resistor 9 is connected to the ground (GND) level, and the resistor 9
The other end is connected to the power supply (VEE) level.
In the initial state, that is, in the state where the fuse 7 is not disconnected, the emitter potential of the transistor 8 becomes the ground (GND) level -V _BE (H level). When the fuse 7 is cut by, for example, laser means, the emitter potential becomes equal to the power source potential (VEE) (L level). The rescue information storage circuit 6 has a plurality of circuits shown in FIG.
-1, 3-1, 2-2, 3-2, 2-3 and 3-3, 2-
The same control signal is given to 4 and 3-4, and an independent selection signal is given to the selector 3-5 from the selection signal 123 as the signal of H level or L level.

The outputs of the output lines 116 to 120 are usually connected to another logic circuit or the like (not shown).
The memory arrays 1-1 to 1-5 are tested by the selector 5
The read data selected by the test output (line 1
It will be done by observing from 22). Further, since the outputs of the redundant memory arrays 1-6 are also connected to the selection circuit 5 via the delay circuit 4, the same test can be performed. Now, as a result of the test, if only the memory array 1-3 of the memory arrays 1-1 to 1-6 is defective, the selectors 2-3 and 3-3, 2-4 and 3-4, and the selector 3- The fuse 7 is cut so as to switch 5. As a result, the write data 103 and 104 are input to the memory arrays 1-4 and 1-5, respectively. The memory arrays 1-4 are connected from the output lines 118 to 120.
Read data 1 to 6 are output, and the defect in the memory array 103 can be relieved. If, as a result of the test, it is found that the memory cells in the other memory arrays including the redundant memory array 1-6 in addition to the memory array 1-3 are defective, it cannot be relieved.

If the delay time of signal propagation in the delay circuit 4 is designed to be equal to the delay time of signal propagation in the selectors 3-1 to 3-5, the access time of the redundant memory array 1-6, etc. Can be measured in the same manner as in the normal memory arrays 1-1 to 1-5.

In the first embodiment, the selectors 3-1 and 3-2 can be constructed as shown in FIG. The selectors 3-1 and 3-2 are the memory arrays 1-1 and 1
-2 also serves as an output stage, and the selector 3-1 includes transistors 9-1 to 9-4 and resistors 10-1 and 10-.
2. The current source 13-1. The transistors 9-1 to 9-3, the resistor 10-1, and the current source 13-1 form a differential amplifier, the output of which is the transistor 9-1.
It is output from the -4 emitter. The sense amplifier output from bit 1-1 is input to the bases of the transistors 9-1 and 9-2. The selection signal 123 from the relief information storage circuit 6 is input to the base of the transistor 9-3. The selector 3-2 also has a similar configuration. Selector 3
-1 and 3-2 are connected to each other, and the selection signal 123 is input to the selector 3-1 "H" to the selector 3-2 "L". The data from 2 is output.

[0014]

As described above, according to the present invention, in a semiconductor memory device having a redundant memory array in addition to a normal memory array, a selection circuit capable of selecting and outputting the outputs of the normal memory array and the redundant memory array is provided. Since it is provided, the redundant memory array can be tested including the AC characteristics before the operation of the defective bit relief storage means (for example, the fuse circuit) (before the fuse is blown). Therefore, it is effective for improving the yield after cutting the fuse. Further, if the selector on the output side is configured as shown in FIG. 3, there is no delay time due to a signal passing through the selector, and therefore there is no deterioration in performance even when compared with a normal memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a rescue information storage circuit 6.

FIG. 3 is a circuit diagram showing an example of a selector.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Memory 2, 3, 5 Selector 4 Delay Circuit 6 Relief Information Storage Circuit

Claims (2)

[Claims] 1. A plurality of main memory cell arrays, a redundant memory cell array, a storage means for repairing defective bits, and a selection circuit for receiving outputs of the main memory cell array and the redundant memory cell array, wherein the selection circuit includes the defective bit repairing. A semiconductor memory device capable of selecting and outputting an output from the redundant memory cell array in an initial state in which the storage means for operation is not operated. 2. The defective bit relief means uses a fuse circuit, and further, a signal propagation time from the output of the main memory cell array to the selection circuit and a signal propagation from the output of the redundant memory array to the selection circuit. 2. The semiconductor memory device according to claim 1, wherein the times are the same.