JP2536333B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a memory cell array is divided into a plurality of blocks and a redundant cell is provided in each of the plurality of blocks.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device of this type, a semiconductor memory device whose conceptual diagram is shown in FIG. 12 is known.

In the figure, 1 is a chip body, 2 ₁ , 2 ₂ ... 2
₈ is a block formed by dividing the memory cell array, 3 ₁ , 3
₂ ... 3 ₈ are fuse circuits (fuse ROM) for storing column (column) redundant addresses of blocks 2 ₁ , 2 ₂ ... 2 ₈ respectively, and 4 ₁ , 4 ₂ ... 4 ₈ are fuse circuits respectively. 3 ₁ , 3 ₂ ... 3 ₈ are part of it, and the column address supplied from the outside and the fuse circuits 3 ₁ , 3 ₂ ... 3 ₈
Is a comparison circuit for comparing with the column redundancy address stored in the column redundancy address, and these comparison circuits 4 ₁ , 4 ₂ ... 4 ₈ form a column redundancy circuit.

FIG. 13 shows a column redundancy circuit provided in this semiconductor memory device. Reference numeral 5 is input from the outside to a column address buffer (not shown) via an external pin, and the column address buffer is supplied from this column address buffer. A column address line for transferring the output column address to the comparison circuits 4 ₁ , 4 ₂ ... 4 ₈ .

Here, the comparison circuits 4 ₁ , 4 ₂ ... 4 ₈ are
Each column address supplied via the column address lines 5, a fuse circuit 3 _1, 3 ₂ ... 3 column redundant address stored in ₈ compared for each bit, the matching bit is logical The comparison signals C ₁ , C ₂ ... C ₈ that are set to “1” (hereinafter simply referred to as “1”) and the bits that do not match are logical “0” (hereinafter simply referred to as “0”) are compared signal lines 6 It is configured to output to ₁ , 6 ₂ ... 6 ₈ .

Reference numeral 7 denotes comparison signals C ₁ , C ₂ ... C supplied from comparison circuits 4 ₁ , 4 ₂ ... 4 ₈ via comparison signal lines 6 ₁ , 6 ₂ ... 6 _{8. 8} is a comparison signal selection circuit for selecting ₈ , and the comparison signal selection circuit 7 is controlled by a block selection signal supplied from a block selection circuit (not shown), and corresponds to the block selected by the block selection signal. It is configured to select the comparison signal of the comparison circuit provided.

Reference numeral 8 indicates whether the column address supplied from the outside and the column redundancy address of the selected block match based on the logical state of the comparison signal selected by the comparison signal selection circuit 7. It is a match determination circuit that determines,
When all the bits of the selected comparison signal are “1”, the match determination circuit 8 checks the match between the column address supplied from the outside and the column redundant address of the selected block, and performs the match determination. "0" is output as a signal, and a logic "1" is output as a match determination signal except when all bits of the comparison signal are "1".

In such a semiconductor memory device, the column addresses supplied from the outside are compared with the comparison circuits 4 ₁ , 4 ₂ ... 4
₈ are transferred to all of the _eight comparison circuits 4 ₁ , 4 ₂ ... 4 ₈
, The column redundancy addresses stored in the fuse circuits 3 ₁ , 3 ₂ ... 3 ₈ are compared, and the comparison signals C ₁ , C ₂ ... C ₈ as the comparison result are compared signal selection circuit 7 Is supplied to.

Further, a block selection signal is supplied to the comparison signal selection circuit 7, a comparison signal output from the comparison circuit provided corresponding to the selected block is selected, and the selected comparison signal is selected. Is supplied to the coincidence determination circuit 8 and it is determined whether or not the column address supplied from the outside and the column redundancy address of the selected block match.

[0010]

In such a conventional semiconductor memory device, the comparison circuits 4 ₁ , 4 ₂ ... 4 ₈ are provided for each of the blocks 2 ₁ , 2 ₂ ... 2 ₈ . , The comparison signal lines 6 ₁ , 6 _2, ..., 6 ₈ need wirings of the number of column address bits × the number of comparison circuits (the number of blocks), which causes an increase in the area of the column redundancy circuit.
There is a problem that the chip size is increasing.
There is a similar problem when a row redundancy circuit having a similar circuit configuration is provided.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a semiconductor memory device in which the area of the redundant circuit can be reduced and the chip size can be reduced.

[0012]

[Means for Solving the Problems]

1st Invention ... FIG. 1 FIG. 1 is a diagram illustrating the principle of the first invention of the present invention. In the semiconductor memory device according to the first aspect of the present invention, the memory cell array is divided into a plurality of blocks 9 ₁ , 9 _2, ... 9 _n , and
It is intended to improve a semiconductor memory device in which a redundant cell is provided in each of the plurality of blocks 9 ₁ , 9 _2, ... 9 _n , and the redundant circuit 10 includes a redundant address memory circuit 11
₁ , 11 ₂ ... 11 _n , a comparison circuit 12, and a match determination circuit 13 are provided. The redundant circuit 10
Can be applied to both the row redundant address circuit and the column redundant address circuit.

Here, the redundant address storage circuits 11 ₁ , 1
1 ₂ ... 11 _n is a plurality of blocks 9 ₁ , 9 ₂ ... 9 _n
Is provided corresponding to each of them, stores the redundant address of the corresponding block, and is selected when the corresponding block is selected, the redundant address of the corresponding block is the same as the address input from the outside. Is output with the logic of or the inverted logic.

The comparison circuit 12 compares the address input from the outside or the address obtained by inverting the address input from the outside with the redundant address output from the selected redundant address storage circuit. is there.

Further, the coincidence determination circuit 13 includes a comparison circuit 12
It is determined based on the comparison result of (1) whether the address input from the outside and the redundant address output from the selected redundant address storage circuit match.

[0016] Incidentally, 14 _1, 14 ₂ ... 14 _n redundant address memory circuit 11 _1, 11 ₂ ... 11 redundant address lines derived from _n, 15 redundant address lines 14 _1, 14 ₂
... A common redundant address line commonly provided for 14 _n ,
Reference numeral 130 is an address line for transferring an address input from the outside or an address obtained by inverting the address input from the outside.

Second Invention ... FIG. 2 FIG. 2 is a diagram for explaining the principle of the second invention in the present invention. In the semiconductor memory device according to the second invention, the memory cell array is composed of a plurality of blocks 9 ₁ , 9 _2, ...
9 _n , and these plural blocks 9 ₁ , 9 ₂ ...
···················· Improves the semiconductor memory device in which redundant cells are provided in each of 9 _n , the redundant circuit 131, the redundant address storage circuit 132 ₁ , 132 ₂ ... 132.
_n , comparison circuits 133 ₁ , 133 _2, ... 133 _n, and a match determination circuit 134 are provided. The redundant circuit 131 can also be applied to both the row redundant address circuit and the column redundant address circuit.

Here, the redundant address storage circuit 132 ₁ ,
132 ₂ ... 132 _n are blocks 9 ₁ , 9 ₂ ... 9 _n
Is provided corresponding to each of the above, and stores the redundant address of the corresponding block.

Further, the comparison circuits 133 ₁ , 133 _2, ... 1
33 _n is provided corresponding to each of the blocks 9 ₁ , 9 _2, ... 9 _n , and redundant address storage circuits 132 ₁ , 132 _{2 are provided.}
... A portion of the redundant address storage circuit that stores the redundant address of the corresponding block among 132 _n ,
When the corresponding block is selected, an address input from the outside or an address obtained by inverting the address input from the outside and the redundancy stored in the redundant address storage circuit that is part of the address It is to compare with the address.

Further, the coincidence determination circuit 134 is the comparison circuit 1
Of the 33 ₁ , 133 _2, ... 133 _n , based on the comparison result of the selected comparison circuit, the redundancy stored in the address input from the outside and the redundancy address storage circuit included in the selected comparison circuit. It is to determine whether or not the address matches.

Note that 135 ₁ , 135 ₂ ... 135 _n are comparison signal lines derived from the comparison circuits 133 ₁ , 133 ₂ ... 133 _n , and 136 is the comparison signals 135 ₁ , 1
Common comparison signal lines 137 provided in common for 35 ₂ ... 135 _n are address lines for transferring an address input from the outside or an address obtained by inverting the address input from the outside.

Third Invention FIG. 3 FIG. 3 is a diagram for explaining the principle of the third invention in the present invention. The semiconductor memory device according to the third aspect of the invention is similar to the first aspect of the invention in that the memory cell array has a plurality of blocks 9 ₁ , 9 _2, ...
9 _n , and these plural blocks 9 ₁ , 9 ₂ ...
···················· Improves the semiconductor memory device in which redundant cells are provided in each of 9 _n , the redundant circuit 138, the redundant address storage circuit 139 ₁ , 139 _2, ...
_n , the redundant address selection circuit 140, and the comparison circuit 141
And a coincidence determination circuit 142. In addition,
The redundant circuit 138 can also be applied to both the row redundant address circuit and the column redundant address circuit.

Here, the redundant address storage circuit 139 ₁ ,
139 ₂ ... 139 _n are blocks 9 ₁ , 9 ₂ ... 9 _n
Is provided corresponding to each of the above, stores the redundant address of the corresponding block, and outputs the redundant address of the corresponding block with the same logic as the address input from the outside or the inverted logic.

Further, the redundant address selection circuit 140 is a redundant address storage provided corresponding to the selected block among the redundant addresses output from the redundant address storage circuits 139 ₁ , 139 ₂ ... 139 _n. The redundant address output by the circuit is selected.

The comparison circuit 141 compares the address input from the outside or the address obtained by inverting the address input from the outside with the redundant address selected by the redundant address selection circuit 140.

Further, the coincidence determination circuit 142 is the comparison circuit 1
Based on the comparison result of 41, it is determined whether the address input from the outside and the redundant address selected by the redundant address selection circuit 140 match.

143 ₁ , 143 _2, ... 143
_n is the redundant address storage circuits 139 ₁ and 139, respectively.
₂ ... Redundant address lines derived from 139 _n , 144
Is an address line for transferring an address input from the outside or an address obtained by inverting the address input from the outside.

[0028]

[Action]

1st Invention ... FIG. 1 In the present invention, in the first invention, redundant address storage circuits 11 ₁ , 11 ₂ ... 11 _n correspond to blocks 9 ₁ , 9 ₂ ... 9 _n , respectively. However, the comparison circuit 12 includes redundant address storage circuits 11 ₁ , 11 ₂ ... 1
It is commonly provided for 1 _n .

As a result, the redundant address storage circuit 11 ₁ ,
Redundant address line 1 derived from 11 ₂ ... 11 _n
4 ₁ , 14 ₂ ... 14 _n can be connected to the common redundant address line 15.

Redundant address lines 14 ₁ , 14 ₂ ...
Each of 14 _n requires wiring as many as the number of bits of the address, and as a whole, wiring of the number of bits of the address × the number of redundant address storage circuits (the number of blocks) is required. As for the common redundant address line 15, wiring of the number of address bits is sufficient.

Further, with respect to the address line 130, the address line 130 is routed so that the redundant address storage circuits 11 ₁ , 11 _2, ...
・ There is no need to wire to 11 _n . Therefore, this first
According to the invention, the area of the redundant circuit 10 can be reduced.

Second invention: FIG. 2 In the second invention, the comparison circuit 133 ₁ ,
133 ₂ ... 133 _n are blocks 9 ₁ , 9 ₂ ... 9 _n
Are provided corresponding to the respective blocks, but are configured to be selected when the corresponding block is selected.

As a result, the address line 137 has to be routed around and wired to the comparison circuits 133 ₁ , 133 _2, ... 133 _n , but the comparison circuits 133 ₁ , 133 _{2 ,.}
Comparison signal line 135 which is derived from 3 _{n 1,} 135 ₂ ···
For 135 _n , these can be connected to the common comparison signal line 136.

Here, the comparison signal lines 135 ₁ , 135 _2, ...
Each of the 135 _n requires wiring as many as the number of bits of the address, and as a whole, wiring as many as the number of bits of the address × the number of comparison circuits (the number of blocks) is required. The comparison signal line 136 may be as many as the number of bits of the address. Therefore, according to the second aspect of the invention, although not so much as the first aspect of the invention, the redundant circuit 131
The area can be reduced.

Third Invention ... FIG. 3 In the present invention, in the third invention, the redundant address line 14 is used.
Although it is not possible to provide a common redundant address line for commonizing 3 ₁ , 143 _2, ... 143 _n , address line 1
For 44, it is not necessary to route this and wire it to the redundant address storage circuits 139 ₁ , 139 _2, ... 139 _n . Therefore, according to the third aspect of the invention, the area of the redundant circuit 138 can be reduced, though not to the extent of the first aspect.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 4 to 11, eight blocks are provided in the first to third embodiments of the present invention as in the case of the conventional semiconductor memory device shown in FIG. A semiconductor memory device having the above structure will be taken as an example to describe a case where the area of the column redundancy circuit is reduced.

First Embodiment ... FIGS. 4 to 9 FIG. 4 is a conceptual diagram of a first embodiment of the present invention (one embodiment of the first invention). In the figure, 16 is a chip body, 17 ₁ and 17 ₂
... 17 ₈ is a block obtained by dividing the memory cell array, 18 ₁ , 18 ₂ ... 18 ₈ is a fuse circuit for storing the column redundant addresses of the blocks 17 ₁ , 17 ₂ ... 17 ₈ , respectively. Reference numeral 19 is a comparison circuit for comparing the column address supplied from the outside with the column redundancy address stored in the selected fuse circuit. In the first embodiment,
Only the fuse circuits 18 ₁ , 18 ₂ ... 18 ₈ are provided corresponding to the blocks 17 ₁ , 17 ₂ ... 17 ₈ , and the comparison circuit 19 includes the fuse circuits 18 ₁ , 18 ₂ ...
It is commonly provided for 18 ₈ .

FIG. 5 shows a column redundancy circuit provided in this first embodiment. In the figure, BA ₀ , BA ₁ and BA ₂ are blocks 17 ₁ and 1 among the addresses supplied from the outside.
The block address for selecting 7 ₂ ... 17 ₈ and the CA ₀ bar, CA ₁ bar ... CA ₇ bar are the columns of blocks 17 ₁ , 17 ₂ ... 17 ₈ among the addresses supplied from the outside. It is an inverted column address obtained by inverting the selected column addresses CA ₀ , CA _1, ... CA ₇ .

Further, 20 is a block address BA ₀ , B
A block selection circuit that decodes A ₁ and BA ₂ and outputs block selection signals BS ₁ bar, BS ₂ bar, ... BS ₈ bar. In the first embodiment, the block selection signals BS ₁ bar and BS ₁ bar are included. ₂ bars ... BS ₈ bars are supplied not only to the blocks 17 ₁ , 17 ₂ ... 17 ₈ but also to the fuse circuits 18 ₁ , 18 ₂ ... 18 ₈ and correspond to the selected blocks. The fuse circuit provided in the above is also selected. The details of the block selection circuit 20 will be described later.

Further, 21 ₁ , 21 ₂ ... 21 ₈ are fuse signal lines derived from the output side of the fuse circuits 18 ₁ , 18 ₂ ... 18 ₈ , respectively. These fuse signal lines 21 ₁ , 21 ₂ ... 21 ₈ respectively have fuse signals FS ₀ , FS _1, ... Inverted logic of column redundancy addresses stored in the fuse circuits 18 ₁ , 18 ₂ ... 18 _8.
・ Output as FS ₇ . Reference numeral 22 is a common fuse signal line provided commonly to the fuse signal lines 21 ₁ , 21 ₂ ... 21 ₈ . The fuse circuits 18 ₁ and 18 ₂
The details of 18 ₈ will be described later.

[0041] Here, the comparison circuit 19, the inverted column address CA ₀ bar obtained by inverting the column address CA _0, CA ₁ ··· CA ₇ input from the outside, and CA ₁ bar · · · CA ₇ bar , Of the fuse circuits 18 ₁ , 18 ₂ ... 18 ₈
Fuse signals FS ₀ , FS ₁ ... FS ₇ output from the fuse circuit selected by the block selection circuit 20.
Are compared for each bit, and the coincident bit is set to "1" and the non-coincident bit is set to "0".
It is configured to output M ₀ , COM ₁ ... COM ₇ . The details of the comparison circuit 19 will also be described later.

Reference numeral 23 is a column address CA ₀ , CA ₁ supplied from the outside based on the logic states of the comparison signals COM ₀ , COM _1, ... COM ₇ supplied from the comparison circuit 19.
... CA ₇ is a match determination circuit that determines whether or not the redundant address of the selected block matches. This match determination circuit 23 includes comparison signals COM ₀ , COM _1, ...
When all of COM ₇ are “1”, “0” is output as the coincidence determination signal, and the comparison signals COM ₀ , COM ₁ ... CO
When all of M ₇ are other than "1", "1" is output as the match determination signal. Details of the coincidence determination circuit 23 will also be described later.

Here, the block selection circuit 20 is configured, for example, as shown in FIG. 6 as a representative of the part that outputs the selection signal BS ₁ bar, that is, the part that selects the block 17 ₁ and the fuse circuit 18 _1. can do. In the figure,
Vcc is the power supply voltage, RAS is a signal obtained by inverting the row address strobe signal RAS bar, and 24 to 29 are nMO.
S and 30 to 35 are pMOS, and in the case of this example, when the block 17 ₁ and the fuse circuit 18 ₁ are selected, RAS = “1” (RAS bar = “0”) is set, and then, BA ₀ = “1”, BA ₁ = “1”, BA ₂ =
It is set to "1" and BS ₁ bar = "0".

Further, the fuse circuits 18 ₁ , 18 ₂ ... 1
8 ₈ can be configured, for example, as shown in FIG. 7 as a representative of the portion of the fuse circuit 18 ₁ that outputs the fuse signal FS ₀ . In the figure, 36 to 47 are nMOS, 48 to
Reference numeral 58 is a pMOS, and 59 and 60 are fuses.

The fuse circuit 18 ₁ is selected by the block selection signal BS ₁ bar = “0” and is not selected by the block selection signal BS ₁ bar = “1”. That is, when the block selection signal BS ₁ bar is set to “0”, the node 61 =
"1", node 62 = "0", node 63 = "1". As a result, both the pMOS 54 and the nMOS 42 become O.
N, the fuse signal FS ₀ can be output. On the other hand, when the block selection signal BS ₁ bar is "1", the node 61 = "0", the node 62 = "1", the node 63 = "0", and as a result, the pMOS 54 and n
Both the MOS 42 are turned off, and the node 64 is brought into a high impedance state.

Further, in this fuse circuit 18 ₁ ,
When "0" is required as the fuse signal FS ₀ , the fuse 59 is blown. Here, RAS = "0"
In the standby state with (RAS bar = “1”), the node 65
= “1”, node 66 = “0”, node 67 = “1”, nMOS 39 is turned on, and node 68 =
"0" and node 69 = "1" are set. Since the fuse 59 is blown here, the “1” of the node 69 is
It is latched by the inverter composed of the nMOS 40, the pMOS 52 and the nMOS 41.

In this case, the pMOS 55 is turned off,
The nMOS 45 is turned on, and the node 61 = “0”, the node 62 = “1”, and the node 63 = “0”. Therefore, in this case, the pMOS 54 and the nMOS 42 are O
It becomes FF, and the node 64 is brought into a high impedance state.

Here, RAS = "1" (RAS bar =
"0") and the read state is reached, the node 65 =
It becomes "0". As a result, pMOS55 is ON, nMO
S45 is turned off, and the level of the node 61 is regulated by the block selection signal BS ₁ bar. As a result, when the block selection signal BS ₁ bar is selected as “0”, the node 61 = “1”, the node 62 = “0”,
Since the node 63 is "1", the pMOS 54 and nM
The OS 42 is turned on, and “0” is output as the fuse signal FS ₀ .

Further, in the fuse circuit 18 ₁ , when the fuse signal FS ₀ needs to be "1", the fuses 59 and 60 are not cut. In this case, RA
When S = “1” and the read state is set, the node 6
5 = “0”, node 66 = “1”, node 67 =
“0”, node 68 = “1”, node 69 = “0”, pMOS 55 is on, nMOS 45 is off.
Becomes Therefore, the block selection signal BS ₁ bar is "0".
Then, the node 61 = “1”, the node 6 is selected.
Since 2 = “0” and node 63 = “1”, pMOS
54 and nMOS 42 are turned on, and the fuse signal FS
“1” is output as ₀ .

The comparison circuit 19 is, for example, as shown in FIG.
Portion for outputting a comparison signal COM _0, i.e., the inverted column address CA ₀ bar obtained by inverting the column address CA ₀ are supplied from the outside, of the fuse circuit 18 _{1-18 8,} the fuse of the fuse circuit selected It can be configured as shown representatively for a portion comparing with the signal FS ₀ . In the figure, 70 to 80 are nMOS, and 81 to 90 are pMOS.

Further, in FIG. 8, FSJ is a signal for controlling whether the comparison circuit 19 is in the use state or the non-use state. When the comparison circuit 19 is in the non-use state, With FSJ = "1", pMOSs 83, 8
6 is turned off, and nMOSs 72, 75, 77 are turned on. Further, in order to put it into a use state, FSJ = “0”, pMOSs 83 and 86 are turned on, nMOSs 72 and 75,
77 is turned off.

In this comparison circuit 19, when FSJ is "1" and "0" is input as the fuse signal FS ₀ , node 91 = "1", node 9
2 = “0”, node 93 = “1”, and nMOS 74
And pMOS85 are turned off, but node 9
Since 4 = “1” and node 95 = “0”, the nMOS
80 and pMOS 89 are turned on.

Therefore, in this case, when the inverted column address CA ₀ bar is "0" having the same logic as the fuse signal FS ₀ , the comparison signal COM ₀ = "1", and the inverted column address CA ₀ bar is When it is "1", the fuse signal FS ₀
When the logic is different from, the comparison signal COM ₀ = “0”.

On the other hand, when the fuse signal FS ₀ = “1”, the node 91 = “0”, the node 92 = “1”, and the node 93 = “0”.
Although 85 is turned on, since the node 94 = “0” and the node 95 = “1”, the nMOS 80 and the pMOS are turned on.
89 is turned off, and the inverter composed of the pMOS 90 and the nMOS 79 is inactivated.

Therefore, in this case, when the inverted column address CA ₀ bar is "1" having the same logic as the fuse signal FS ₀ , the comparison signal COM ₀ = "1", and the inverted column address CA ₀ bar is When it is "0", the fuse signal FS ₀
When the logic is different from, the comparison signal COM ₀ = “0”.

The match determination circuit 23 is, for example, as shown in FIG.
Can be configured as shown in. In the figure, 96-10
Reference numeral 9 is an nMOS and 110 to 123 are pMOSs. In the coincidence determination circuit 23, COM _{0 to} COM ₇ =
In the case of “1”, the nodes 124 to 127 are “0”.
Therefore, the nodes 128 and 129 = “1” again, and as a result, the coincidence determination signal becomes “0”, and the column addresses CA ₀ , CA ₁ ... CA ₇ input from the outside are:
It is determined that the column redundant address is in the selected block.

On the other hand, COM ₀ to COM ₇ are "0".
, Is included, for example, COM _{0 to} COM ₆ = “1”
Then, when COM ₇ = “0”, the nodes 124 to 126 =
Although it is “1”, the node 127 is “0”. As a result, the node 128 becomes "0", but the node 129 becomes "1", and the coincidence determination signal becomes "1". As described above, when COM ₀ to COM ₇ include “0”, the match determination signal becomes “1”, and the column addresses CA ₀ , CA ₁ ... CA ₇ input from the outside are It is determined that it is not the column redundant address in the selected block.

In the first embodiment, the fuse circuits 18 ₁ , 18 ₂ ... 18 ₈ are provided in the block 1 respectively.
It is provided corresponding to 7 ₁ , 17 ₂ ... 17 ₈ ,
The comparison circuit 19 includes fuse circuits 18 ₁ , 18 ₂ ... 18
It is provided in common to ₈ .

As a result, the fuse circuits 18 ₁ , 18 ₂ ...
・ Fuse signal lines 21 ₁ and 21 ₂ derived from 18 ₈
· 21 ₈ may be connected to a common fuse signal line 22.

Here, the fuse signal lines 21 ₁ , 21 ₂ ...
- 21 _8, respectively, the fuse signal FS _0, FS ₁ ··
The number of bits of FS ₇ , that is, the column addresses CA ₀ and CA _1.
..Wiring of the number of bits of CA ₇ is required,
As a whole, the number of bits of the column addresses CA ₀ , CA ₁ ... CA ₇ × the number of fuse circuits 18 ₁ , 18 ₂ ... 18 ₈ (the number of blocks 17 ₁ , 17 ₂ ... 17 ₈ ) However, the common fuse signal line 22 may be as many as the number of bits of the column addresses CA ₀ , CA ₁ ... CA ₇ .

Further, in the first embodiment, the inverted column address lines for transferring the inverted column addresses CA ₀ bar, CA ₁ bar ... CA ₇ bar are laid out as in the conventional semiconductor memory device shown in FIG. No need.

Therefore, according to the first embodiment, the area of the column redundancy circuit can be reduced and the chip size can be reduced. It is needless to say that the area of the row redundancy circuit can be reduced when the row redundancy circuit is similarly configured.

Second Embodiment FIG. 10 FIG. 10 shows a second embodiment of the present invention (one embodiment of the second invention).
FIG. 6 is a diagram showing a main part of the above, that is, a column redundancy circuit provided in the second embodiment. The parts corresponding to those in FIG. 5 are designated by the same reference numerals, and duplicate description thereof will be omitted.

In the figure, 145 is an inverted column address line for transferring the inverted column address CA ₀ bar, CA ₁ bar ... CA ₇ bar, 146 ₁ , 146 ₂ ... 146 ₈ are blocks 17 ₁ and 17 respectively. a fuse circuit for storing the column redundancy address ₂ ... 17 _8.

Also, 147 ₁ , 147 _2, ... 147
₈ are provided corresponding to each of the blocks 17 ₁ , 17 ₂ ... 17 ₈ and the fuse circuits 146 ₁ , 146 ₂ ...
Of 146 _8, a comparator circuit for the corresponding fuse circuit and a part of.

These comparison circuits 147 ₁ , 147 _2, ... 1
47 ₈ is selected by the block selection signals BS ₁ bar, BS ₂ bar, ... BS ₈ bar output from the block selection circuit 20, that is, selected when the corresponding block is selected, and the inverted column address CA. ₀ bar, CA ₁ bar
..CA ₇ bar is compared with the column redundancy address stored in the fuse circuit of which it is a part, and the result is output as a comparison signal.

Further, 148 ₁ , 148 _2, ..., 148 ₈ are comparator circuits 147 ₁ , 148 ₁ for outputting comparison signals, respectively.
147 ₂ ... 147 ₈ derived comparison signal lines, 14
Reference numeral 9 is a common comparison signal line provided commonly to the comparison signal lines 148 ₁ , 148 ₂ ... 148 ₈ .

Further, 150 is a coincidence judging circuit, and this coincidence judging circuit 150 is composed of comparing circuits 147 ₁ , 147 _2, ...
A column address C supplied from the outside based on the comparison signal output from the selected comparison circuit out of 147 ₈
It is configured to determine whether A ₀ , CA ₁ ... CA ₇ and the column redundancy address of the selected block match.

In the second embodiment, the inversion column address line 145 is routed in the same manner as in the conventional semiconductor memory device shown in FIG. 12, and the comparison circuits 147 ₁ , 147 ₂ ... 147.
_It is necessary to wire to ₈ but these comparison circuits 147 ₁ , 1
47 ₂ ... 147 ₈ derived comparison signal line 14
8 ₁ , 148 _2, ..., 148 ₈ can be connected to the common comparison signal line 149.

Here, the comparison signal lines 148 ₁ , 148 _2, ...
148 ₈ are column addresses CA ₀ , CA ₁ ...
The number of wirings corresponding to the number of bits of CA ₇ is required, and as a whole, the number of bits of column addresses CA ₀ , CA ₁ ... CA ₇ x the number of comparison circuits 147 ₁ , 147 ₂ ... 147 ₈ ( (The number of blocks 17 ₁ , 17 ₂ ... 17 ₈ ) is required, but the common comparison signal line 149 is the number of bits of the column addresses CA ₀ , CA ₁ ... CA _7. Is enough.

Therefore, according to the second embodiment, the area of the column redundancy circuit can be reduced and the chip size can be reduced, though not to the extent of the first embodiment. In addition,
Of course, when the row redundancy circuit is similarly configured, the area of the row redundancy circuit can be reduced.

Third Embodiment FIG. 11 FIG. 11 shows a third embodiment of the present invention (one embodiment of the third invention).
FIG. 7 is a diagram showing an essential part of the above, that is, a column redundancy circuit provided in the third embodiment. The parts corresponding to those in FIG. 5 are designated by the same reference numerals, and duplicate description thereof will be omitted.

In the figure, 151 ₁ , 151 _2, ... 151
₈ is a fuse circuit for storing the column redundancy addresses of the blocks 17 ₁ , 17 ₂ ... 17 ₈ respectively, and 152 ₁ , 15
2 ₂ ... 152 _8, respectively, the fuse circuit 15
Fuse signal lines derived from 1 ₁ , 151 _2, ... 151 ₈ , and these fuse signal lines 152 ₁ , 152 _2.
The ... 152 _8, respectively, the fuse circuits 151 _1, 1
The column redundancy address stored in 51 ₂ ... 151 ₈ is output as a fuse signal whose logic is inverted.

Reference numeral 153 denotes a fuse signal selection circuit. The fuse signal selection circuit 153 is controlled by the block selection signals BS ₁ bar, BS ₂ bar ... BS ₈ bar, and the fuse circuits 151 ₁ , 151 ₂ , ...・ ・ 151 ₈
The fuse signal output from the fuse circuit provided corresponding to the block selected by the block selection signals BS ₁ bar, BS ₂ bar, ... BS ₈ bar is selected from the fuse signals output from Has been done.

Reference numeral 154 is a comparison circuit.
The circuit 154 uses the inverted column address CA. ₀Bar, CA₁bar·
..CA₇And the fuse signal selection circuit 153
Configured to compare with the selected fuse signal
ing. 155 is an inverted column address line.

Numeral 156 is a coincidence judging circuit, and the coincidence judging circuit 156 matches the column address inputted from the outside with the column redundancy address of the selected block based on the comparison result of the comparing circuit 154. It is configured to determine whether or not to do.

In the third embodiment, the column address C
The number of bits of A ₀ , CA ₁ ... CA ₇ × fuse circuit 15
The number of 1 ₁ , 151 _2, ... 151 ₈ (blocks 17 ₁ , 17
Fuse signal lines 152 ₁ of the number of number of ₂ ... 17 _8),
Although it is necessary to wire 152 ₂ ... 152 ₈ , the inversion column address line 155 is routed like the conventional semiconductor memory device shown in FIG.
There is no need to wire 51 ₁ , 151 _2, ... 151 ₈ .

Therefore, according to the third embodiment, the area of the column redundancy circuit can be reduced and the chip size can be reduced, though not to the extent of the first embodiment. In addition,
Of course, when the row redundancy circuit is similarly configured, the area of the row redundancy circuit can be reduced.

In the above embodiment, the column redundant address memory circuit is composed of the fuse circuit. However, in the present invention, the column redundant address memory circuit is masked.
It can also be applied to the case of configuring with OM or the like.

[0080]

According to the present invention, it is possible to reduce the number of wires required to form a redundant circuit, reduce the area of the redundant circuit, and reduce the chip size.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention in the present invention.

FIG. 2 is a diagram illustrating the principle of the second invention in the present invention.

FIG. 3 is an explanatory view of the principle of the third invention in the present invention.

FIG. 4 is a first embodiment of the present invention (one embodiment of the first invention).
It is a conceptual diagram of.

FIG. 5 is a circuit diagram showing a column redundancy circuit provided in the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a part of a block selection circuit forming the column redundancy circuit shown in FIG.

FIG. 7 is a circuit diagram showing a part of a fuse circuit forming the column redundancy circuit shown in FIG.

8 is a circuit diagram showing a part of a comparison circuit forming the column redundancy circuit shown in FIG.

9 is a circuit diagram showing a match determination circuit forming the column redundancy circuit shown in FIG.

FIG. 10 is a circuit diagram showing a column redundancy circuit provided in a second embodiment of the present invention (an embodiment of the second invention).

FIG. 11 is a circuit diagram showing a column redundancy circuit provided in a third embodiment (one embodiment of the third invention) of the present invention.

FIG. 12 is a conceptual diagram of an example of a conventional semiconductor memory device.

13 is a circuit diagram showing a column redundancy circuit provided in the conventional semiconductor memory device shown in FIG.

[Explanation of symbols]

9 ₁ , 9 ₂ , 9 _n blocks 10, 131, 138 redundant circuit

Claims (3)

(57) [Claims] [Claim 1] by dividing the memory cell array into a plurality of blocks _{(9 1, 9 2 ··· 9} n) , and each of redundant cells of the plurality of blocks _{(9 1, 9 2 ··· 9} n) A semiconductor memory device provided with a plurality of blocks (9 ₁ , 9 _2, ... 9 _n ) respectively corresponding to the redundant addresses of the corresponding blocks. When a block is selected, a plurality of redundant address storage circuits (11 ₁ , 11 ₂₎ which are selected and output the redundant address of the corresponding block with the same logic as the address input from the outside or the inverted logic
... 11 _n ), an address externally input or an address obtained by inverting an externally input address, and among the plurality of redundant address storage circuits (11 ₁ , 11 _2, ... 11 _n ). A comparison circuit (12) for comparing the redundant address output from the selected redundant address storage circuit, and the address input from the outside and the selected address based on the comparison result of the comparison circuit (12). Redundancy circuit (1) including a match determination circuit (13) for determining whether or not the redundant address stored in the redundant address storage circuit matches
0) is provided to configure the semiconductor memory device. Wherein a memory cell array is divided into a plurality of blocks _{(9 1, 9 2 ··· 9} n) , and each of redundant cells of the plurality of blocks _{(9 1, 9 2 ··· 9} n) A semiconductor memory device comprising: a plurality of redundancy blocks each of which is provided corresponding to each of the plurality of blocks (9 ₁ , 9 _2, ... 9 _n ) and stores redundant addresses of the corresponding blocks. Address storage circuit (1
32 ₁ , 132 ₂ ... 132 _n ) and the plurality of blocks (9 ₁ , 9 ₂ ... 9 _n ) respectively corresponding to the plurality of redundant address storage circuits (132 ₁ , 132 _n ). ₂ ... 132 _n ) has a redundant address storage circuit for storing the redundant address of the corresponding block in a part thereof, and is selected when the corresponding block is selected, and an address input from the outside or A comparison circuit (133 ₁ , 133 ₂₎ that compares an address obtained by inverting an address input from the outside with a redundant address stored in a redundant address storage circuit that it has
... 133 _n ) and the comparison result of a comparison circuit selected from among the comparison circuits (133 ₁ , 133 ₂ ... 133 _n ) based on the address inputted from the outside and the comparison circuit selected. Is provided with a redundancy circuit (131) including a match determination circuit (134) for determining whether or not the redundancy address stored in the redundancy address storage circuit included in Semiconductor memory device. Wherein a memory cell array is divided into a plurality of blocks _{(9 1, 9 2 ··· 9} n) , and each of redundant cells of the plurality of blocks _{(9 1, 9 2 ··· 9} n) A semiconductor memory device comprising: a plurality of blocks (9 ₁ , 9 ₂ ... 9 _n ) provided corresponding to each of the plurality of blocks (9 ₁ , 9 ₂ ... 9 _n ) and storing redundant addresses of the corresponding blocks. A plurality of redundant address storage circuits (13) that output the redundant address of the block to be output with the same logic as the address input from the outside or the inverted logic.
9 ₁ , 139 _2, ... 139 _n ) and the plurality of redundant address storage circuits (139 ₁ , 139 _2, ...
A redundant address selection circuit (140) for selecting a redundant address output from a redundant address storage circuit provided corresponding to the selected block among the redundant addresses output from 139 _n ) Comparing circuit (141) for comparing the address obtained by inverting the address inputted from the outside or the address inputted from the outside with the redundant address selected by the redundant address selecting circuit (140), and comparing the comparing circuit (141) A redundancy circuit (consisting of a match determination circuit (142) for determining whether or not the address input from the outside and the redundancy address selected by the redundancy address selection circuit (140) match based on the result ( 138) is provided to configure the semiconductor memory device.