JPH05307182A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To decrease defects generated on a gate line by linearizing the gate line without branching. CONSTITUTION:A switching transistor(TR) is turned on and off under the control of the signal of the gate line 1 to charge a data holding capacitor connected to the drain with the voltage of a source line 2 through a channel part when the switching TR is turned on or hold the electric charges accumulated in the capacitor until the TR is turned on next time when the TR is OFF. In this case, the gate line 1 is linearized to form a pattern wherein the channel part of the switching TR is right below the gate line 1. Therefore, the gate line 1 is made less in area than before, so the defect generation rate becomes 2/3-1/2 time as large as before. The defect generation rate of the gate line 1 is basically low, but further approximated to defect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to aligning gate lines of an integrated circuit for driving an active matrix panel (hereinafter referred to as an active matrix substrate).

On an active matrix substrate shown in FIG.
FIG. 3 is a schematic view of an element portion including individual switching transistors and data holding capacitors arranged in a matrix. A portion surrounded by a dotted line 3 in the drawing is an element portion, which is formed by a switching transistor 4, a data holding capacitor 5, a liquid crystal driving electrode, and a liquid crystal 6 in a repetitive matrix in a horizontal direction and a vertical direction. The basic operation is to control ON / OFF of the switching transistor by the signal of the gate line 1, and when the switching transistor is turned ON, the data of the voltage of the source line 2 is connected to the drain via the channel part. The holding capacitor is charged, and when it is turned off, the charge stored in the capacitor is turned on next by the transistor.
It is something to hold for the time to do.

FIG. 2 shows a conventional pattern formed on a Si substrate in order to realize the element portion shown in FIG. In the figure, 1 is a gate line made of polycrystalline silicon, and 2 is a source line Al. 3 is switching
Transistors 4 are data holding capacitors. Each switching transistor is located at the intersection of the gate line and the source line, and from the drain to the capacitor made of polycrystalline silicon and Si substrate and thin Si oxide film, Al
Connected by. In an actual active matrix substrate, this pattern is repeatedly patterned at least 200 times in the horizontal and vertical directions. Therefore, the gate line and the source line, and
If a leak occurs even in some places, it causes a line defect and a device defect, and such an active matrix substrate is considered defective. However, because it is possible to cut the defective location of the defective chip due to the balance with the yield and correct it to a non-defective chip, it is branched from the gate line and the source line and the switching transistor It forms a contact with the source and a gate. According to the data actually measured on the chip, as for the source line, a hole must be formed in the field oxide film in order to connect with the source diffusion region of each element, so there is a defect that causes leakage around the contact hole. Since it easily occurs, it can be said that the merit of branching from the main line is great. However, in the gate line, it is formed on the field oxide film, and at the channel part,
Since the gate oxide film is interposed, the occurrence rate of defects that cause leakage is sufficiently lower than that of the source line. As a result, it can be said that there is almost no merit in branching from the main line to the channel section. On the contrary, the disadvantage is that defects are more likely to occur because the area of the polycrystalline silicon forming the gate line is large. Further, in the photo-etching step of polycrystalline silicon, the compatibility with that of the existing Si gate integrated circuit is extremely low, and if polycrystalline silicon of 10 μm size is formed by 3 to 4 cm with the gate line pattern of FIG. There is a drawback in that the photo resist formed for etching the polycrystalline silicon pattern branched from the main line to the channel portion is peeled off, and a defective pattern of the polycrystalline silicon is likely to occur. If the chip yield is to be improved by the existing Si gate technology, improvement of the gate / line pattern is desired. Further, in the conventional gate line pattern, it is necessary to provide a space of several μm to several tens of μm between the gate polycrystal silicon of the channel portion and the polycrystal silicon forming the data holding capacitor in order to insulate the polycrystal silicon. There is a drawback that the capacity of the capacitor cannot be increased. Since the liquid crystal is driven by the electric charge stored in the capacitor, it is necessary to hold the electric charge in the capacitor during the time from when the switching transistor is first turned on to when the switching transistor is turned on next. However, considering the leakage between the polycrystalline silicon, which is one of the electrodes of the capacitor, and the Si substrate and the leakage due to the train junction, the capacity of the conventional capacitor has a small margin, and the voltage does not change during the charge hold time. It was difficult to stably drive the liquid crystal.

The present invention eliminates such drawbacks. Its purpose is to first reduce the defects generated in the gate line and secondly to reduce the capacitance of the data holding capacitor.
It is to increase the size of the element part without changing it. The present invention will be described in detail below based on examples.

FIG. 3 shows an embodiment according to the present invention. The numbers in the figure are the same as those in FIG. 2 and are omitted here. In this embodiment, the gate line is linearized so that the channel portion of the switching transistor is directly below the gate line. Since the area of the gate line is smaller than the conventional one, the defect occurrence rate is 2/3 that of the conventional one.
~ 1/2. Although the defect occurrence rate of the gate line is basically low, it is possible to further approach the zero defect by this embodiment. Further, since the line is a simple polycrystalline silicon line, patterning can be easily performed even with the existing Si gate technology. Further, since the gate channel portion is not branched by the polycrystalline silicon, the area of the polycrystalline silicon forming the capacitor can be increased. As is clear from the figure, the area increases by about 30%, so that the area easily increases by about 30% in proportion to the area.

With the above structure, the following effects can be obtained.

(A) By straightening the gate line without branching it, the area of the gate line is reduced, and patterning is simple and easy. Can be significantly reduced.

(B) Since the area of the data holding capacitor can be increased without changing the area of the switching element, the display area can be increased and the aperture ratio can be greatly improved. (C) Since the wiring resistance and the wiring capacitance can be reduced, the size of the entire screen of the display device can be increased.

(D) Since the wiring area is reduced, it is not necessary to apply an unnecessary DC electric field to the liquid crystal, the reliability is improved, and the life of the liquid crystal is extended.

(E) Since the capacity of the data holding capacitor can be increased, the liquid crystal can be removed even if the drain / junction leakage and the discharge between the polycrystalline silicon and the substrate are discharged. It is possible to realize an active matrix type liquid crystal device which can hold a sufficient charge for driving and has a large capacity margin.

[Brief description of drawings]

FIG. 1 is a schematic view of an element portion including a switching transistor and a capacitor.

FIG. 2 is a pattern diagram of a conventional element portion.

FIG. 3 is a pattern diagram of an element unit according to the present invention.

Claims (1)

[Claims] 1. A liquid crystal is sealed in a pair of substrates, and pixel electrodes arranged in a matrix, transistors connected to the pixel electrodes, and source regions of the transistors are provided on one substrate of the substrates. In a liquid crystal display device having a data line for supplying a data signal and a gate line for supplying a gate signal to the gate electrode of the transistor, a channel region is arranged to intersect the gate line in the width direction of the gate line. A liquid crystal display device, comprising a transistor formed so that a source region connected to a data line is located at a first pixel and a drain region is located at a second pixel.