JPH05307168A - Driving circuit of liquid crystal display panel - Google Patents

Abstract

PURPOSE:To use the driving circuit for either of an active matrix-type or a simple matrix-type liquid crystal display panel by varying the appearance timing of the 'presence' and 'absence' of a display signal in common units. CONSTITUTION:In addition to the driving circuit of the general active matrix- type liquid crystal display panel part 5, this liquid crystal display panel is equipped with a display data generation part 6 which has a color table previously set corresponding to display colors and outputs a digital RGB signal found by the color table corresponding to display data from a display memory part 3 to a liquid crystal display panel part 7 including the simple matrix-type liquid crystal display panel. This display data generation part 6 controls the 'selection' and 'nonselection' of pixels at intersection of the command and segments of the simple matrix type liquid crystal display panel with the 'presence' of the display signal, thins out several pixels in a group consisting of plural pixels, and varies the timing of the 'presence' and 'absence' of the display signal in common units to adjust the transmissivity of the group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit of a simple matrix type liquid crystal display panel for displaying gradation.

[0002]

2. Description of the Related Art T is provided between a plurality of scanning signal electrodes (common) and a plurality of display signal electrodes (segments) arranged orthogonally.
An active matrix type liquid crystal display panel in which liquid crystal such as N and STN is sealed is provided with a switching element such as a thin film transistor at the intersection of a common and a segment (for example, Japanese Patent Laid-Open No. 3-70279). A simple matrix type without a switching element (for example, Japanese Unexamined Patent Publication No.
135319 gazette).

[0003]

In the former (active matrix type), the problem of driving duty does not occur even if the number of pixels (the above-mentioned intersections or a set of several intersections) is large, but uniform characteristics are obtained. Since it is difficult to form the switching element, it is difficult and expensive to manufacture a device having a large number of pixels. On the other hand, in the latter (simple matrix type), it is possible to easily manufacture a pixel having a large number of pixels and it is inexpensive, but the driving duty ratio becomes small and the contrast decreases, so that it is difficult to display halftone.

Particularly, in the simple matrix type, it is difficult to obtain stable gradation display. As a conventionally known drive circuit for gradation display, as disclosed in Japanese Patent Application Laid-Open No. 2-262122, "selection" and "non-selection" of display change are performed at the same pulse crest value of the display signal. By changing the pulse width of the "and" to distinguish between "selected" and "non-selected", or JP-A-3-2722 and JP-A-3-37622
As disclosed in Japanese Patent Laid-Open Publication No. JP-A-2003-264, the selection field is divided into two or more time regions and the number of selection fields is changed to distinguish "selection" from "non-selection".
Furthermore, as disclosed in JP-A-3-185490,
Although a combination of the above two methods has been proposed, in any of these methods, the aperture ratio (transmittance) at the intersection is adjusted by changing the voltage difference generated at the intersection in a stepwise manner. However, since the aperture ratio with respect to the voltage difference fluctuates under the influence of external factors such as the ambient temperature, the display quality becomes unstable.

Further, when a color filter of R (red), G (green) and B (blue) is provided in a segment of a liquid crystal display panel to form a multi-color display type, the former is a display signal to the liquid crystal display panel. An analog RGB signal is used as
Since the latter uses digital RGB signals, when either an active matrix type drive circuit or a simple matrix type drive circuit is selected, the liquid crystal display panel is not compatible and limited to use.

In view of the above-mentioned problems, the present invention can use either an active matrix type liquid crystal display panel or a simple matrix type liquid crystal display panel, and particularly provides stable gray scale display when using the simple matrix type liquid crystal display panel. It is an object of the present invention to provide a driving circuit characterized by performing.

[0007]

According to the present invention, "selection" and "non-selection" of pixels, which are intersections of commons and segments of a simple matrix type liquid crystal display panel, are applied to the segments of the liquid crystal display panel. It is possible to control by "present" and "absent" of the display signal, and to make several pixels into one group to thin out some pixels in this group. In this case, "present" and "present" of the display signal. By changing the appearance timing of "none" in the common unit, the display data for adjusting the transmittance of the group and performing the gradation display.
The data generator is compatible with the active matrix type liquid crystal display panel by sharing a signal in the middle of the drive circuit of the active matrix type liquid crystal display panel and converting it into a simple matrix type signal.

[0008]

With the display data generating section, the "selection" and "non-selection" of the pixel, which is the intersection of the common and the segment of the simple matrix type liquid crystal display panel, are changed to "present" and "none" of the display signal.
, And plural pixels are regarded as one group to thin out some pixels in this group, and the appearance timing of “present” or “none” of the display signal changes in the common unit. By doing so, gradation display can be performed by adjusting the transmittance of the group. Further, compared to the conventional technique of changing the potential difference generated at the intersection stepwise, it is less affected by external factors, and the gradation display of the simple matrix type liquid crystal display panel can be performed stably, and By sharing the signal of and converting to the simple matrix type, it has compatibility with the active matrix type.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment, in which 1 is controlled according to a program preset in accordance with an input signal so that a display image in accordance with the input signal is displayed on a liquid crystal display panel described later. CPU that outputs signals, 2
Write the data based on the graphic signal corresponding to the display image to the display memory unit 3 by the control signal, and read the stored contents of the display memory unit 3 in synchronization with the scanning timing of the liquid crystal display panel described later to obtain the display image. A graphic controller unit 3 which controls to output suitable display data to the color palette 4 is a graphic controller.
The display memory unit 4 which holds the memory content written by the controller unit 2 and outputs 4-bit display data described later to the color pallet 4 in accordance with an instruction from the graphic controller unit 4 is preset in accordance with the display color. A color palette is set, and an analog RGB signal obtained by the color table according to the display data from the display memory section 3 is output to the active matrix type liquid crystal display panel section 5 by a color palette. Thus, the above configuration constitutes a drive circuit of a general active matrix type liquid crystal display panel section 5.

The features of the present invention will be clarified by the following.
That is, 6 has a color table set in advance according to the display color, and a digital RGB signal obtained by the color table according to the display data from the display memory section 3 is displayed in a simple matrix type liquid crystal display. This is a display data generating section for outputting to a liquid crystal display panel section 7 including a panel, and together with the CPU 1, the graphic controller section 2 and the display memory section 3, constitutes a drive circuit of the simple matrix type liquid crystal display panel section 7.

FIG. 2 shows a concrete circuit configuration of the display data generating section 6, which is constituted by logic in this embodiment. That is, two 2-bit counters 611 and 61
2 and two AND elements 613 and 614 and two knot elements 615 and 616, the mask pattern generating section 61 is used for horizontal synchronization with the vertical synchronization signal VS from the graphic controller section 2 (see FIG. 1). Signal HS and CL of counter 612
The clock signal DOTCLK is input to the R bar terminal, the CK bar terminal, the CLR bar terminal and the LOAD bar terminal of the counter 612, and the clock signal DOTCLK is input to the CK bar terminal of the counter 612. The Q0 terminal and the Q1 terminal of the counter 611 are connected to the D0 terminal and the D1 terminal of the counter 612 through the AND elements 613 and 614 and the knot element 615, respectively, and are connected to the Q1 terminal of the counter 612 through the knot element 613. An output signal MD indicated by 3 is output.

The output signal MD of the mask pattern generator 61 becomes one input of the OR element 62, and the output of this OR element 62 becomes one input of the AND elements 63, 64, 65, and the AND element 63, The outputs of 64 and 65 are selectors 66, 67 and 68.
It is the input of the B terminal. The output signal MD of the mask pattern generator 61 is inverted and the selectors 66, 67,
68 A terminal input. The display data b0, b1, b2 from the display memory unit 3 (see FIG. 1) is
It is the other input of the AND elements 65, 64, 63 and the OR element 69, and the output of this OR element 69 is the input of the S terminal of the selectors 66, 67, 68. Further, the display data b3 becomes the other input of the OR element 62 and is inverted at the same time so that the OR element 69
Is input. As shown in FIG. 4, the selectors 66, 67, 68 determine the output of the Y terminal according to the input of the A terminal, B terminal, and S terminal, and these become RGB signals, and the liquid crystal display panel section 7 (see FIG. 1). ) Is supplied to.

The input (display data b0, b1, b2, b3 from the display memory 3) and the output (RGB signal, that is, the output of the Y terminal of the selectors 66, 67, 68) in the display data generating unit 6 The relationship is configured to implement the preset color table shown in FIG.

Next, the operation of the present embodiment will be described. Since the active matrix type liquid crystal display panel section 5 is a general driving circuit, its explanation is omitted, and the simple matrix type which is a feature of the present invention will be described below. The drive circuit of the liquid crystal display panel section 7 will be described with reference to the time chart of FIG.

As shown in FIG. 6, when the vertical synchronizing signal VS changes from "high (H)" to "low (L)", the counter 611 of the mask pattern generating section 61 is reset.
Next, when the vertical synchronizing signal VS becomes "H", the counter 611
Is normally 1 every time the horizontal synchronization signal HS of “H” becomes “L”
The count is incremented by one, and from the Q0 and Q1 terminals, "0,0 (decimal 0)""1,0 (decimal 1)"
The count value of “0, 1 (2 in decimal) 2” and “1, 1 (3 in decimal)” is repeatedly output to the counter 612.

FIG. 7A is an explanatory view of the range A of FIG. 6, that is, a portion where the count value of the counter 611 changes from "0" to "1", and FIG. 7B further shows that of FIG. It is an enlarged view of the range a. When the vertical synchronizing signal HS changes from "H" to "L", the counter 612 enters the reset state with the reset value "2" as shown in FIG. 3 according to the count value "1" of the counter 611. Then, the horizontal synchronization signal HS is "L".
Counter 612 changes to clock signal D
Each time OTCLK changes from "H" to "L", the count value is incremented by one, and the mask pattern generator 61 outputs the output signal M shown in FIG. 7B according to the operation characteristics of FIG.
D is output.

FIG. 8A is an explanatory diagram of the range B of FIG. 6, that is, a portion in which the count value of the counter 611 changes from "1" to "2", and FIG. 8B further shows that of FIG. It is an enlarged view of the range b. 7 is different from FIG. 7 in that the counter 612 is in a reset state with the reset value “0” according to the count value “2” of the counter 611, as shown in FIG. The output signal MD shown is output.

FIG. 9 (a) is an explanatory view of the range C of FIG. 6, that is, the portion where the count value of the counter 611 changes from "2" to "3", and FIG. 9 (b) further shows that of FIG. 9 (a). It is an enlarged view of the range c. The difference from FIG. 7 is that the counter 612 is in the reset state with the reset value “1” as shown in FIG. 3 according to the count value “3” of the counter 611, and the mask pattern generating unit 61 changes the state from FIG. 9 (b). The output signal MD shown is output.

FIG. 10 shows the range D or counter of FIG.
An explanatory view of a portion in which the count value of 611 changes from “3” to “0”, and FIG. 6B is an enlarged view of a range d in FIG. The counter 612 is in the reset state as shown in FIG. 3 according to the count value “0” of the counter 611 as shown in FIG. 3, and as shown in FIG.
The same output signal MD as in (b) is output from the mask pattern generator 61.

FIG. 11 is an explanatory view showing the structure of the liquid crystal display panel section 7, that is, the graphic controller section 2 (see FIG. 1).
Control unit 71 which receives the vertical synchronizing signal VS and the horizontal synchronizing signal HS from the reference pattern) and outputs the synchronizing signal to the common driver 72, and the digital RGB from the display pattern generating unit 6 (see FIGS. 1 and 2). A segment driver 73 that receives the synchronization signal from the signal and control unit 71, and a common driver 72
The liquid crystal display panel section 7 is composed of a liquid crystal display panel 74 driven by the scanning signal of (1) and the display signal of the segment driver 73.

FIG. 12 shows an electrode pattern of the liquid crystal display panel 74.
FIG. 4 is an explanatory view showing the commons C1 and C that run in the lateral direction.
2, C3, ..., Cn and segment S running in the vertical direction
1, S2, S3, ..., Sm, and each of the segments S1, S2, S3, ..., Sm is divided into three and RGB color filters are individually provided, and a common C1 is provided. And a segment S1 composed of segments R1, G1 and B1 at a pixel P11, a common C1 and a segment R1.
The intersection with the segment S2 composed of 2, G2 and B2 is constituted by the pixel P12, and the intersection between the common C2 and the segment S1 composed of the segments R1, G1 and B1 is constituted by the pixel P21.

Next, a simple matrix type liquid crystal display panel
The driving method of 74 will be described. Common C1, C2, C
, ..., Cn one scan, one frame is divided by the number n of commons C1, C2, C3, ..., Cn of the liquid crystal display panel 74, and 1 / n duty and applied voltage level The voltage driving waveform shown in FIG. 13 is used as a scanning signal by the common driver 71 to drive the common C1 and C of the liquid crystal display panel 74 so that the driving is performed by the ⅕ bias set in five stages.
, C3, ..., Cn.

On the other hand, the segment S of the liquid crystal display panel 74
1, S2, S3, ..., Sm have pixels P11, P12, P13 ,.
Of P21, ..., P31, ..., Pnm, the part that transmits light is “selected”, and the part that does not transmit light is “unselected”.
14 (the waveform of "selection" in FIG. 14 has pixels P51, P52, P53, ..., P at the intersection with the common C5.
The case where 5m is selected is shown. ) Is used as a display signal by the segment driver 73 for the segments S1, S2, S3, ..., Of the liquid crystal display panel 74.
Applied to Sm. By the way, the segments S1, S2
Since S3, ..., Sm are each divided into three parts and RGB color filters are individually provided, for example, pixel P
In order to bring 11 into the "selected" state, the segment S1 shown in FIG.
Even if the "selection" display signal of No. 4 is applied, the pixel P11 looks red if the display signal is applied only to the segment G1, and the pixel P11 is green if the display signal is applied only to the segment G1. When the display signal is applied only to the segment B1, the pixel P11 looks blue, and a composite color can be displayed depending on the combination of the segments R1, G1, and B1.

Next, the liquid crystal display panel 74 according to the present embodiment.
A specific driving method of will be described.

When the liquid crystal display panel 74 performs white display in response to the input from the CPU 1, the display data b of the display memory unit 3 is displayed.
3 ・ b2 ・ b1 ・ b0 is displayed as "1 ・ 1 ・ 1 ・ 1"
It becomes an input to the data generator 6. Further, since the S terminals of the selectors 66, 67, 68 are "H", the outputs from the Y terminals of the selectors 66, 67, 68 are the selectors 66, 67, 68 as shown in FIG.
It is determined by the input of the B terminal of. Since the output of the OR element 62 is "H" due to the display data b3, the outputs of the AND elements 63, 64 and 65 having this as one input and the display data b2, b1 and b0 respectively as the other input. Ie selectors 66, 6
The inputs to the B terminals of 7, 68 are always "H" regardless of the output signal MD of the mask pattern generation unit 61. Therefore,
The RGB signals from the display data generator 6, which are the outputs of the selectors 68, 67 and 66, are always "H" as shown in FIG.
In response to this, the segment driver 73 causes the segment S1, S2, S3, ..., Sm of the liquid crystal display panel 74.
By applying the display signal of "selection" in FIG.
Pixels P11, P12, P13, ..., P of the liquid crystal display panel 74
nm gets the display image displayed entirely in white.

When the liquid crystal display panel 74 displays a black color in response to the input of the CPU 1, the display data b of the display memory unit 3 is displayed.
3 ・ b2 ・ b1 ・ b0 is displayed as "0 ・ 0 ・ 0 ・ 0"
It becomes an input to the data generator 6. Further, since the display device b3 receives the inverted "H" input and outputs an "H" output, the S terminals of the selectors 66, 67, 68 are set to "H". , 67, 68 output from the Y terminals is determined by the input of the B terminals of the selectors 66, 67, 68 as shown in FIG. The inputs of the B terminals of the selectors 66, 67 and 68 are always "L" regardless of the output signal MD of the mask pattern generator 61. Therefore, the RGB signals from the display data generator 6 which are the outputs of the selectors 68, 67 and 66 are shown in FIG.
As shown by, the segment driver 73 is always "L", and accordingly, the segment driver 73 causes the segment S1, S
2, S3, ..., Sm by applying the display signal of "non-selection" in FIG. 14 to the pixel P1 of the liquid crystal display panel 74.
1, P12, P13, ..., Pnm obtain a display image displayed in black that does not allow light to pass through.

When the liquid crystal display panel 74 displays a red color in response to an input from the CPU 1, the display data b of the display memory section 3 is displayed.
3 ・ b2 ・ b1 ・ b0 is displayed as "1.0.0.1"
It becomes an input to the data generator 6. Further, the selector 6 is operated by the OR element 69 which inputs the display data b0 and outputs the output of "H".
Since the S terminals of 6, 67, 68 become "H", the selectors 66, 6
The output from the Y terminals of 7, 68 is determined by the input of the B terminals of the selectors 66, 67, 68 as shown in FIG. Selector 6
Since the outputs of the AND elements 64 and 63 are always "L" at the inputs of the B terminals of 7 and 66, the GB signal from the display data generating unit 6 which is the output of the selectors 67 and 66 is shown in FIG. It is always "L" as indicated by. On the other hand, with respect to the input of the B terminal of the selector 68, since the output of the AND element 65 is always "H", the R signal from the display data generating section 6 which is the output of the selector 68 is shown in FIG. Is always "H". In response to this, the segment driver 73 causes the segment R1, R2, R3, ..., Rm of the segments S1, S2, S3 ,. Is applied to the segments G1, G2, G3, ...
.., Gm and segments B1, B2, B3, ..., B
By applying the display signal of "non-selection" in FIG. 14 to m, the pixels P11, P12, P13, ...
・, Pnm obtains a display image that is entirely displayed in red.

The pixels P11 and P1 of the liquid crystal display panel 74
2, P13, ..., Pnm are displayed in green or blue as a whole, as in the case of red, the segment S
1, S2, S3, ..., Sm segment G1,
G2, G3, ..., Gm or segments B1, B
, Bm are applied by applying the display signal of "selection" in FIG. 14, and the others are applied by applying the display signal of "non-selection" in FIG. Further, by combining the segments R, G, and B, it is possible to obtain a display image in which the display color of the segment S is a composite color.

When the liquid crystal display panel 74 displays a dark red color according to the input of the CPU 1, the display data of the display memory unit 3 is displayed.
The data b3, b2, b1, and b0 are "0, 0, 0, 1" and are input to the display data generating unit 6. Further, the S element of the selectors 66, 67, 68 is set to "H" by the OR element 69 which inputs the display data b0 and outputs the output of "H".
The output from the Y terminals of 6, 67 and 68 is determined by the input of the B terminals of the selectors 66, 67 and 68 as shown in FIG. Since the outputs of the AND elements 64 and 63 are always "L" at the inputs of the B terminals of the selectors 67 and 66, the GB signal from the display data generating unit 6 which is the output of the selectors 67 and 66 is shown in FIG. ), It is always “L”. On the other hand, the output of the selector 68 is determined by the input of the B terminal of the selector 68, that is, the output of the AND element 65, and the output of the AND element 65 is
Since one input of the display data b0 is always "H" at 65, it is determined by the output signal MD of the mask pattern generating unit 61 which is the other input. That is, the R signal from the display data generator 6, which is the output of the selector 68, repeats "H" and "L" in synchronization with the output MD as shown in FIG. Each time the signal HS is generated, that is, the appearance timing of “H” and “L” changes in the common unit (see FIGS. 7 to 10), the R
Depending on the signal, the segments S1 and S of the liquid crystal display panel 74
, S3, ..., Sm segments R1, R2
Since the display signal of "selection" in FIG. 14 is applied only to R3, ..., Rm, the liquid crystal display panel 74 has pixels P11, P12, P13, ..., Pnm as shown in FIG. Only a specific part (hatched part) is displayed in red and the other part (blank part) is displayed in black that does not transmit light. Therefore, the liquid crystal display panel 74 as a whole is a mixture of red and black. Obtain a display image displayed in dark red. Thus, by using three pixels as one group and thinning out one pixel in this group, it is possible to adjust the transmittance of the group and perform gray scale display.

The pixels P11 and P1 of the liquid crystal display panel 74
When the whole 2, P13, ..., Pnm is displayed in dark green or dark blue, the display data generator 6 outputs the output signal MD of the mask pattern generator 61 as in the case of the dark red. By repeating “H” and “L” in synchronization, and by outputting the G signal or the B signal in which the appearance timing of “H” and “L” changes each time the horizontal synchronization signal HS is generated, the segment S1 is output. , S2, S3, ..., Sm
, Gm or segments B1, B2, B3, ..., Bm among the segments are applied with the display signal of "selection" in FIG. It is obtained by applying the display signal of "select".
Further, by combining the segments R, G, and B, it is possible to obtain a display image in which the display color of the segment S is a composite color.

The display data generating section 6 is composed of logic as in the above-mentioned embodiment, and, for example, the mask pattern generating section 61 is composed of a memory and a counter.
It may be processed by software so as to control the output signal MD based on the control signal from U1.

Further, the output signal MD of the mask pattern 61
In addition to changing the appearance timing of "H" and "L" every time the horizontal synchronizing signal HS is generated, as shown in FIGS. 7 to 10, the horizontal synchronizing signal HS is generated. It is also possible to output a plurality of patterns in which the appearance timings of "H" and "L" are completely different.

[0034]

According to the present invention, the display data generating section causes the "selection" and "non-selection" of the pixel, which is the intersection of the common and the segment of the simple matrix type liquid crystal display panel, to be "displayed". "It is controlled by" none ", and it is possible to thin out some pixels in this group by setting a plurality of pixels as one group, and in this case, the appearance timing of" yes "and" none "of the display signal. Is changed in the common unit, the gray scale display can be performed by adjusting the transmittance of the group. In addition, compared to the conventional technology in which the potential difference generated at the intersection is changed stepwise, it is less affected by external factors, and the gradation display of the simple matrix type liquid crystal display panel can be performed stably, and the display quality is improved. And the compatibility with the active matrix type can be obtained by sharing the signal on the way and converting it for the simple matrix type.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram of a display data generating unit according to the embodiment.

FIG. 3 is a logic diagram for explaining the operation of the mask pattern generation unit of the above embodiment.

FIG. 4 is a logic diagram for explaining the operation of the selector of the display data generating unit of the above embodiment.

FIG. 5 is a logic diagram illustrating a color table of a display data generating unit according to the above embodiment.

FIG. 6 is a time chart for explaining the signal states of the mask pattern generation unit of the above embodiment.

7 is an explanatory diagram of a range A in FIG.

8 is an explanatory diagram of a range B in FIG.

9 is an explanatory diagram of a range C in FIG.

10 is an explanatory diagram of a range D in FIG.

FIG. 11 is a block diagram illustrating a configuration of a simple matrix type liquid crystal display panel unit according to the same embodiment.

FIG. 12 is a plan view illustrating commons and segments of the liquid crystal display panel of the simple matrix type liquid crystal display panel section of the above-described embodiment.

FIG. 13 is a voltage waveform diagram illustrating a voltage waveform applied to a common of the liquid crystal display panel of the simple matrix type liquid crystal display panel unit of the above-mentioned embodiment.

FIG. 14 is a voltage waveform diagram for explaining a voltage waveform applied to a segment of the liquid crystal display panel of the simple matrix type liquid crystal display panel unit of the above-mentioned embodiment.

FIG. 15 is a time chart explaining an RGB signal which is an output of the display data generating unit of the embodiment.

FIG. 16 is a plan view for explaining thinning-out of the liquid crystal display panel of the simple matrix type liquid crystal display panel unit of the above embodiment.

[Explanation of symbols]

 1 CPU 2 Graphic controller section 3 Display memory section 4 Color palette 5 Active matrix type liquid crystal display panel section 6 Display data generating section 7 Simple matrix type liquid crystal display panel section

Claims (1)

[Claims] 1. A “selection” or “non-selection” of a pixel, which is an intersection of a common and a segment of a simple matrix type liquid crystal display panel, is “present” or “none” of a display signal applied to the segment of the liquid crystal display panel. , And it is possible to thin out some pixels in this group by setting a plurality of pixels as one group, and in this case, the appearance timing of "present" or "none" of the display signal is set to the common. The display data generating unit for performing gradation display by adjusting the transmittance of the group by changing the unit shares the signal in the middle of the drive circuit of the active matrix type liquid crystal display panel. A drive circuit for a liquid crystal display panel, which is compatible with an active matrix type liquid crystal display panel by being converted into a simple matrix type.