JPH05307065A - Dynamic type semiconductor memory - Google Patents

Abstract

PURPOSE:To make aging while the electric field applied to the insulative film of a memory cell capacitor is varied in the range from the intensity at normal service to an intensity stronger than it, by varying the potential given to the plate electrode of capacitor between four different supply voltages. CONSTITUTION:Vss first supply potential, Vcc second supply potential, 1/2 Vcc third supply potential, and super-Vcc fourth supply potential can be impressed on a plate electrode by a super Vcc generator circuit where the super- Vcc is impressed through a PAD 2 and control signals X, Y, Z for testing given externally. Thereby, aging can be conducted while the electric field applied to the insulative film of a memory cell capacitor is varied between the intensity at normal service and an intensity twice as large as it, and an intensity still stronger than it. When the voltage applied to the plate electrode is made higher than the supply voltage Vcc in order to perform a stronger aging, current flows from the node A side toward the supply voltage Vcc terminal, that, however, can be avoided by the work of p-type transistors Q4, Q5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory, and more particularly to a dynamic semiconductor memory in which each memory cell has a capacitor for storing information and a capacitor oxide film of the memory cell can be screened.

[0002]

2. Description of the Related Art Recent large-capacity dynamic semiconductor memory (DRA) adopting a 1/2 Vcc cell plate system.
In M), it has been confirmed that the memory cell capacitor insulating film has a slower convergence rate of the occurrence rate of the initial failure during the burn-in test than the wiring layer.

Therefore, aging is applied to the memory cell capacitor insulating film by applying an electric field and a temperature higher than the actual use conditions, and the defective factor of the device having the potential defective factor of the memory cell capacitor insulating film is revealed and the device is exposed. Is screened to remove the product from the shipment (The Institute of Electronics, Information and Communication Engineers, C-II Vol. J7
3-C-II No. 5 pp. 302-309 199
May 0 '-Paper-High-speed screening method for DRAM memory cell insulating film).

By the way, conventionally, the screening has been carried out as follows. When a potential higher than the standard is applied to an input pin, a screening p-channel MOS transistor (hereinafter referred to as "p-type transistor") connected between the power supply voltage Vcc terminal and the plate electrode.
". ) Is turned on and the plate electrode is changed from 1/2 Vcc to the power supply voltage Vcc, and screening is performed by applying an electric field having twice the strength of the electric field originally applied to the capacitor insulating film.

[0005]

By the way, there has been a problem in the prior art that the plate electrode cannot be screened more effectively. The reason for this is that in order to more fully reveal potential memory cell capacitor insulating film failure factors, the plate electrode should be at the original voltage of 1/2 Vcc,
This is because it is necessary to apply a voltage higher than double the voltage.
Therefore, it was considered that a voltage higher than the power supply voltage Vcc (hereinafter referred to as "super Vcc") is applied to the plate electrode by using an external power supply during the pellet check, but this has not been possible in the past.

This is because the p-type transistor for screening connected between the power supply voltage Vcc terminal and the plate electrode has a gate electrode and a substrate (substrate for the p-type transistor) as shown in FIG. In this case, since the potential of the n-type well) is at the power supply voltage Vcc level, a through current flows from the plate electrode side (external power supply side) to which the super Vcc is applied toward the power supply voltage Vcc terminal, This is because the device may be destroyed by latch-up.

The present invention has been made to solve such a problem. First, the voltage applied to the plate electrode of the memory cell capacitor is changed in four steps between the first to fourth power supply voltages. Secondly, to make it possible to perform testing and aging without hindrance, and secondly, to make it possible to apply a voltage whose absolute value is larger than the power supply voltage to the plate electrode without hindrance and to strengthen aging. Thirdly, the third object is to enable strong aging without using an external power source.

[0008]

According to another aspect of the present invention, there is provided a dynamic semiconductor memory including:
Power supply potential, a capacitor having an absolute value larger than the first power supply potential, a third power supply potential intermediate between the first power supply potential and the capacitor, and an absolute value larger than the capacitor. It is characterized in that four kinds of power source potentials of the fourth power source potential can be applied during the test.

According to another aspect of the dynamic semiconductor memory of the present invention, the first transistor for transmitting the first power source potential to the plate electrode, the second transistor for transmitting the second power source potential to the plate electrode, and the third transistor for the plate electrode are provided. Connected between the second transistor and the plate electrode for transmitting the power supply potential of the second transistor and having a conductivity type opposite to those of the first and third transistors and applying the fourth power supply potential to the plate electrode. At this time, the fourth M in which the substrate and the gate electrode have the same potential
A feature is that an OS transistor is provided. Claim 3
The dynamic semiconductor memory is characterized by having a high voltage generating circuit for generating a fourth power supply potential.

[0010]

According to the dynamic semiconductor memory of the present invention, since the potential applied to the plate electrode of the capacitor can be changed among the four types of power source potentials of the first to fourth types, it is added to the memory cell capacitor insulating film. Aging can be performed by changing the electric field between the strength at the time of normal use, twice as high as that at the time of use, and higher. Further, since the first power supply potential and the second power supply potential can be applied to the plate electrode, defective cells can be detected by operating the memory in that state.

According to another aspect of the dynamic semiconductor memory of the present invention, the fourth power supply potential is applied to the plate electrode between the second transistor for transmitting the second power supply potential to the plate electrode and the plate electrode. When there is a fourth transistor in which the gate electrode and the substrate have the same potential, the fourth transistor is turned off when a fourth power source potential is applied to the plate electrode and the second power source terminal and the plate are turned off. Electrically cut between the electrodes. Therefore, even if the fourth power supply potential is applied to the plate electrode,
There is no possibility that a through current will flow between the power supply terminal and the terminal. Therefore, it is possible to apply a power supply potential having an absolute value higher than that of the second power supply potential to the plate electrode for strong aging, and it is possible to perform more effective screening.

According to another aspect of the dynamic semiconductor memory of the present invention, since the dynamic semiconductor memory itself has a built-in high voltage generating circuit for producing the fourth power supply potential, the fourth power supply potential is generated at the time of screening. There is no need for an external power supply to operate and no high voltage application pad is required. Further, even after the device is packaged, the fourth power supply potential is applied to the plate electrode of the capacitor, and strong aging screening can be performed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The dynamic semiconductor memory of the present invention will be described in detail below with reference to the illustrated embodiments. FIG. 1 is a circuit diagram showing one embodiment of the dynamic semiconductor memory of the present invention. The portion indicated by the chain double-dashed line in the figure does not exist in this embodiment, but exists in other embodiments. In the drawing, C is an information storage capacitor of the memory cell, and Qs is a switching transistor of the memory cell. Then, the plate electrode of the capacitor C becomes the node A.

Q1 is a first n-channel type MOS transistor (hereinafter referred to as "n-type transistor" referred to as "n-type transistor") connected between a plate electrode and ground (a terminal having a first power supply potential Vss). And the signal Y is received by the gate electrode. Q2 is a p-channel type second transistor that transmits the second power supply potential Vcc to the plate electrode (node A), and is formed in the n-type well selectively formed in the p-type semiconductor substrate (FIG. 2). The substrate of the p-type transistor Q2 (n
The type well) is connected to the source connected to the Vcc (second power supply potential) terminal, and the drain is connected to the p-type transistor (Q4) described later. Further, the gate electrode receives a signal obtained by inverting the signal X by an inverter.

Reference numeral 1 denotes a half Vcc generating circuit, which has a power supply voltage V
A voltage of, for example, one half of cc is generated. Q3 is an n-type transistor connected between the output terminal of the half Vcc generating circuit 1 and the plate electrode, and receives the signal Z at its gate electrode. Therefore, the signal Z is at the "high" level, that is, Vc
When the voltage reaches the c level, a voltage of ½ of Vcc, that is, half Vcc (third power supply potential) is applied to the plate electrode. In other words, it receives the same voltage as the normal time of the memory. Since it is necessary to apply the same voltage to the plate electrode as in the normal state for the test, the half Vcc generation circuit 1 is thus provided.

Reference numeral 2 denotes a pad, which is provided so that a voltage higher than the power supply voltage Vcc, that is, super Vcc can be applied to the plate electrode from the outside. Q4 is a p-type transistor connected between the p-type transistor Q2 and the plate electrode.
Type fourth transistor, which is formed in an n-type well selectively formed in a p-type semiconductor substrate. And
The substrate (n-type well) of the p-type transistor Q4 is connected to the source connected to the plate electrode, and the drain is connected to the drain of the p-type transistor Q2.
A connection point between the p-type transistors Q2 and Q4 is referred to as a node C.

Q5 is a p-type transistor connected between the gate electrode and source of the p-type transistor Q4, and its gate electrode receives the signal X. Q6 is an n-type transistor connected between the gate electrode of the p-type transistor Q4 and the ground (first power supply potential Vss), and the gate electrode thereof receives the signal X. In addition, this gate electrode is referred to as a node B.

Next, the operation of this circuit will be described. Table 1 below shows a mode in which the first power supply potential Vss is applied to the plate electrode as mode 1 and a third power supply potential as half V
cc, that is, a mode in which 1/2 Vcc is applied is mode 2, a mode in which a power supply voltage Vcc that is the second power supply potential is mode 3 and a mode in which super Vcc that is the fourth power supply potential is mode 4 are State of test control signals X, Y, Z and pads in each mode and each node A,
The states of B and C are shown.

[0019]

[Table 1]

In mode 1, the test control signal X,
Z is set to "low" level, that is, Vss level, and signal Y is set to "high" level, that is, Vcc level. Of course, the power supply voltage is not applied to the pad 2 from the outside (the power supply voltage is applied to the pad 2 only in the mode 4).
Both the transistors Q5 and Q6 receiving the signal X at their gate electrodes are turned off, and the node B becomes floating. Therefore, the transistor Q4 is also turned off. Further, the transistor Q2 receiving the inverted signal of the signal X, that is, the signal of "high" is also turned off. Therefore, the node C also becomes floating.

The first transistor Q1 is turned on in the mode 1, and the node A is grounded (first power supply potential Vss) by the transistor Q1. next,
In the mode 2, the test control signals X and Y become the first power supply potential Vss and the test control signal Z becomes the second power supply potential.
Becomes Vcc which is the power supply potential of. Since the test control signal Z becomes "high", the n-type transistor Q3 receiving it at the gate electrode is turned on, and the half Vcc generated by the half Vcc generating circuit 1 is applied to the plate electrode. Of course, the transistor Q1 is turned off.

The source of the p-type transistor Q5 is turned on when the source has a higher potential than the gate electrode, and as a result, the node B also has the same potential as the node A, that is, half Vcc. However, the p-type transistor Q4 is in the off state because the substrate and the gate electrode are both at the same half Vcc level, and the transistors Q6 and Q2 are also in the off state as in the mode 1. Therefore, the node C is floating.

In the mode 3, the test control signal X becomes the power supply voltage Vcc, and Y and Z become Vss. Therefore,
First, Vss and half Vcc are the transistors Q1 and Q3.
Is electrically separated from the plate electrode. Also, p
The type transistor Q2 is turned on because its gate receives the Vss level output from the inverter, and as a result, the node C becomes the power supply voltage Vcc level which is the second power supply potential. In addition, the transistor Q6 has a power supply voltage V
Since it receives cc, it turns on, and p-type transistor Q5 turns off because it receives power supply voltage Vcc on its gate electrode. As a result, the p-type transistor Q4 is turned on, and the potential of the node C, that is, the level of the power supply voltage Vcc which is the second power supply potential is transmitted to the plate electrode. That is, it is possible to apply a voltage twice as high as that during normal use to the plate electrode.

In mode 4, the test control signal X,
All of Y and Z are set to the Vss level, and a super Vcc considerably higher than the power supply voltage Vcc is externally applied to the pad 2. At this time, the plate electrode, that is, the node A is separated from the first power supply potential Vss and the half Vcc by the transistors Q1 and Q3, as in the mode 3. Then, node A has a super Vc higher than Vcc.
Transistors Q2, Q4 due to the change to the c level,
The operations of Q5 and Q6 are as follows.

The p-type transistor Q5 has a gate electrode of Vs.
s and the source receives super Vcc, so it turns on. The gate electrode of the n-type transistor Q6 is Vs
Because it receives s, it turns off. Therefore, the potential of node A, super Vcc, is transmitted to node B as it is through p-type transistor Q5. Therefore, the node B becomes the super Vcc level. By the way, in the p-type transistor Q4 whose gate electrode potential is set to the super Vcc level, the potential of the substrate (n-type well) is also set to super Vcc, that is, since the gate electrode and the substrate have the same potential, they are turned off. .. Therefore, the invasion of current from the node A side to the node C side is blocked by the p-type transistor Q4, and the node C becomes a floating state. Therefore, as shown in FIG. 2, the p-type transistor Q2 does not receive a super Vcc higher than Vcc at its drain and a through current flows to the Vcc side.

That is, in the present dynamic semiconductor memory, the p-type transistor Q2 that transmits the second power source potential Vcc to the plate electrode (node A) side and the plate electrode are not directly connected, but the p-type transistor Q2 is interposed therebetween. When the p-type transistor Q5 is connected between the gate electrode and the source (substrate, that is, n-type well) of the p-type transistor Q4 via the transistor Q4, and the plate electrode, that is, the node A becomes the super Vcc. Then, the p-type transistor Q5 is turned on and the gate electrode and the source (and the substrate) of the p-type transistor Q4 are set to the same potential (both super Vcc) to turn off the p-type transistor Q4. Therefore, the power supply voltage Vcc is applied to the node A side.
Even if it is set higher than that, no problem will occur and strong aging can be applied without any problem.

As described above, according to the present dynamic semiconductor memory, the test control signals X, Y, Z from the outside are supplied.
And Vss (first power supply potential) by the super Vcc generation circuit for applying super Vcc via the pad 2,
Vcc (second power supply potential), 1/2 Vcc (third power supply potential), and super Vcc (fourth power supply potential) can be applied to the plate electrode. Therefore, the aging can be performed by changing the electric field applied to the memory cell capacitor insulating film between the strength during normal use, about twice as high as that during normal use, and more than that. Of course, when the voltage applied to the plate electrode is made higher than the power supply voltage Vcc to apply strong aging, the current flows from the node A side to the power supply voltage Vcc terminal side, as described above, because the p-type transistors Q4 and Q5 function. As described above, it does not cause any trouble (latch-up).

In view of the series of operations described above, the pellet check at the time of production can be performed by putting the dynamic semiconductor memory in the mode 4 state of Table 1, and the high speed screening can be performed. At this time, if a high voltage is applied to the plate electrode, the capacitor C
It is also possible to detect a defect that the capacity of the capacitor changes. Therefore, if the pellet check is performed before the redundancy repair, it is possible to repair a cell in which the capacitor oxide film is destroyed by high-speed screening and a cell in which the capacitor capacitance is changed at the same time to obtain a good product, so that the yield can be improved.

Next, after the assembly is completed, it becomes impossible to apply a voltage from the pad 2. However, the potentials applied to the plate electrodes can be switched among Vss, Vcc, and half Vcc by the test control signals X, Y, and Z. Therefore, during burn-in, the plate electrodes of the capacitors are connected to the power supply voltage Vcc or ground (Vss). ) Level and can be screened.

The presence / absence of a defect in the capacitor insulating film can be checked as follows. First, the mode 1 (see Table 1) is set (that is, the plate electrode is set to Vs
s) The dynamic semiconductor memory (device) is operated. Then, the defective memory cell can read only "low" regardless of whether "high" is written or "low" is written, so that the presence or absence of the defective cell can be detected by utilizing its property. This is the reason why there is a mode for applying a ground (Vss) level to the plate electrode, that is, mode 1.

Next, the plate electrode is set to the power supply voltage Vcc, that is, the mode 3 is set, and the device is operated. Then, the defective memory cell can read only "high" even if "high" is written or "low" is written, so that the presence or absence of the defective cell can be detected by utilizing the property. The mode 3 is provided so that one can be subjected to aging (weaker aging than when super Vcc is applied), and the other is to detect a defective cell.

After all, according to the present dynamic semiconductor memory, the plate is super Vc when the pellet chuck is performed.
It is possible to perform high-speed screening with c, and after packaging, perform plate-in (aging) and failure analysis with Vcc and Vss plates.

As shown by the chain double-dashed line in FIG. 1, a half Vc composed of a booster circuit is provided in the dynamic semiconductor memory.
If the c generation circuit is provided and the booster circuit is operated at any time, it is not necessary to provide the pad 2. Of course, it is not necessary to prepare an external power supply for screening and connect it to the dynamic semiconductor memory with a probe. In addition, even after the packaging is over, Super V
Screening can be performed by applying cc to the gate electrode, and defective pellets can be removed more reliably by screening again before shipping.

[0034]

According to the dynamic semiconductor memory of the first aspect, the capacitor of the plate electrode is provided with the first power supply potential,
A second power source potential having an absolute value larger than that of the first power source potential; a third power source potential that is an intermediate potential between the first power source potential and the second power source potential; and the second power source. It is characterized in that four types of power source potentials, which are fourth power source potentials having an absolute value larger than the potential, can be applied at the time of a test. Therefore, according to the dynamic semiconductor memory of the first aspect, the potential applied to the plate electrode of the capacitor can be changed among the four types of power source potentials of the first to fourth types, so that the electric field applied to the memory cell capacitor insulating film can be changed. Can be aged by changing the strength between normal use, about twice as high as that at the time of use, and more. Further, since the first power supply potential and the second power supply potential can be applied to the plate electrode, the defective cell can be detected by operating the memory in that state.

According to another aspect of the dynamic semiconductor memory of the present invention, a first transistor for transmitting a first power supply potential to a plate electrode, a second transistor for transmitting a second power supply potential, and a third power supply potential for a plate electrode. A substrate and a gate electrode which are connected between the transmitting third transistor and the second transistor and the plate electrode, and which are of opposite conductivity type of the first and third transistors and when a fourth power supply potential is applied to the plate electrode. It is characterized in that a fourth MOS transistor having the same potential as that of and is provided. Therefore, according to the dynamic semiconductor memory of claim 2, when a fourth power supply potential is applied to the plate electrode between the second transistor transmitting the second power supply potential to the plate electrode and the plate electrode. Since there is a fourth transistor in which the gate electrode and the substrate have the same potential, the fourth transistor is turned off when the fourth power source potential is applied to the plate electrode and the terminal of the second power source potential and the plate electrode. Electrically cut between and. Therefore, even if the fourth power supply potential is applied to the plate electrode, there is no fear that a through current will flow between the terminal of the fourth power supply potential and the terminal of the second power supply potential. Therefore, it is possible to apply a power supply potential having an absolute value higher than that of the second power supply potential to the plate electrode for strong aging, and it is possible to perform more effective screening.

According to a third aspect of the dynamic semiconductor memory, a circuit for generating a fourth power supply potential is incorporated. Therefore, according to the dynamic semiconductor memory of the third aspect, since the dynamic semiconductor memory itself has the built-in high voltage generating circuit for generating the fourth power supply potential, the fourth power supply potential is generated at the time of screening. No external power supply is needed and no high voltage application pad is required. Further, even after the device is packaged, the fourth power supply potential is applied to the plate electrode of the capacitor, and strong aging screening can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a dynamic semiconductor memory of the present invention.

FIG. 2 is a cross-sectional view of a p-type transistor for explaining a problem to be solved by the invention.

[Explanation of symbols]

Vss first power supply potential Vcc second power supply potential 1/2 Vcc third power supply potential (half Vcc) super Vcc fourth power supply potential Q1 transistor for transmitting first power supply potential (Vss) Q2 second power supply potential ( Transistor for transmitting Vcc) Q3 Transistor for transmitting third power supply potential (half Vcc) Q4 Transistor in which the substrate and the gate electrode have the same potential when the fourth power supply potential is applied to the plate

Claims (3)

[Claims] 1. A plate electrode capacitor includes a first power supply potential and a second power supply potential having an absolute value larger than that of the first power supply potential.
Power source potential, a third power source potential which is an intermediate potential between the first power source potential and the second power source potential, and a fourth power source potential having an absolute value larger than the second power source potential. Dynamic type semiconductor memory characterized in that four kinds of power supply potentials can be applied at the time of test 2. A first transistor for transmitting a first power supply potential to the plate electrode of the capacitor, a second transistor for transmitting a second power supply potential to the plate electrode of the capacitor, and a third power supply to the plate electrode of the capacitor. A third power source, which is connected between the third transistor for transmitting a potential and the second transistor and the plate electrode, has a conductivity type opposite to that of the first and third transistors and has an absolute value of the plate electrode is the second power source. A dynamic semiconductor memory including at least a fourth transistor in which a substrate and a gate electrode are substantially equal when the potential is higher than an absolute value. 3. A dynamic semiconductor memory according to claim 1, further comprising a circuit for generating a fourth power supply potential.