JPH05304321A - Power supply for josephson circuit - Google Patents

Abstract

PURPOSE:To realize a power supply for Josephson circuit in which power consumption can be suppressed and heat design is facilitated. CONSTITUTION:High frequency current is fed from a current source through a line having predetermined characteristic impedance to the primary winding of a matching transformer and AC current induced in the secondary winding thereof is fed through first and second wiring patterns, formed on a same chip while being coupled capacitively, to a Josephson circuit which is also fed with a predetermined DC bias current through the second wiring pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device for a Josephson circuit, and more particularly to a power supply device for a Josephson circuit whose thermal design is easy.

[0002]

2. Description of the Related Art Generally, a superconducting logic circuit using a Josephson element is current driven and normally operates in a latching mode (a mode in which a switch state is maintained as it is unless the power supply current is cut off). Therefore, the power supply current is cut off and the circuit is reset every cycle. FIG. 9 shows an example of the power supply current waveform. In this example, a substantially rectangular actual current waveform including a circuit reset section is generated based on the sinusoidal current waveform supplied to the chip, and this is supplied to the superconducting gate as a power supply current. Note that the example of FIG. 9 shows a single-phase bipolar waveform, but other than this, various power supply current waveforms such as two-phase, three-phase, or unipolar with a DC offset are proposed. All the waveforms are the same in that they are reset when the power supply waveform is 0 (zero).

In FIG. 10, a sinusoidal high frequency current i generated by a current source 1 is a coaxial cable 2 and a package 3.
Is supplied to the Josephson circuit 6 through the strip line 4 and the terminating resistor 5 inside, and after being shaped into an actual current waveform by a waveform shaping circuit (not shown) in the Josephson circuit 6, the inside of the Josephson circuit 6 Is supplied to the superconducting logic circuit.

Here, the terminating resistor 5 is a characteristic impedance Z _O system (generally Z _O) of the current source 1 and the coaxial cable 2.
Is 50Ω: hereinafter, this system is referred to as a 50Ω impedance system) and the impedance Z _J system of the Josephson circuit (generally Z _J is about 0.01 to 0.1Ω: hereinafter, this system is referred to as a minimum impedance system). And has the same resistance value as the 50Ω impedance system.

[0005]

However, in such a conventional power supply device for the Josephson circuit, since the high frequency current i is made to flow into the Josephson circuit 6 through the terminating resistor 5, the terminating resistor 5 is used. ,
Wasted power corresponding to “i ² × 50Ω” is generated and consumed as heat.

Therefore, there are problems that the current source 1 becomes large and the thermal design for maintaining the low temperature operation of the Josephson circuit 6 becomes complicated. [Purpose] Therefore, an object of the present invention is to realize a power supply device for a Josephson circuit that can suppress power consumption and that can be easily thermal-designed.

[0007]

In order to achieve the above-mentioned object, the present invention provides a matching transformer of a high frequency current generated by a current source through a line having a predetermined characteristic impedance as shown in the principle diagram of FIG. The alternating current induced in the secondary winding of the matching transformer and induced in the secondary winding of the matching transformer is capacitively coupled with the first wiring pattern on the chip and the second wiring pattern on the same chip. It is characterized in that it is supplied to the Josephson circuit through a wiring pattern and a predetermined DC bias current is supplied to the Josephson circuit through the second wiring pattern.

[0008]

According to the present invention, the alternating current induced in the secondary winding of the matching transformer for impedance matching is capacitively coupled from the first wiring pattern to the second wiring pattern, and the alternating current on the second wiring pattern is formed. It is combined with the DC bias current and supplied to the Josephson circuit.

Therefore, since it is not necessary to use the terminating resistor, it is possible to suppress wasteful power (that is, heat generation),
It is possible to realize a Josephson circuit power supply device with easy thermal design. Further, the first wiring pattern and the second wiring pattern form equivalent capacitances for separating the direct current system and the alternating current system, so that it is not necessary to independently form a capacitive device (capacitor, etc.) The production can be facilitated.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 2 and 3 are views showing a first embodiment of a power supply device for a Josephson circuit according to the present invention.

In FIG. 2, 10 is a current source for generating a sinusoidal high-frequency current i, 11 is a line such as a coaxial cable having a characteristic impedance Z _{O of} 50Ω, and 12 is a superconducting integrated circuit chip (hereinafter simply referred to as a chip). Say) 1
3 is a matching transformer having a primary winding 13a and a secondary winding 13b having a predetermined winding ratio, 14 is a first wiring pattern, 15 is a second wiring pattern, J _{1 to} J _n are Josephson circuits,
Reference numeral 16 is a bias generation circuit. Although the matching transformer 13 is provided in the chip 12 in the figure, it may be provided outside. In the Josephson circuits J _{1 to} J _n , R is a load resistance, and G is a superconducting logic gate using a Josephson element (input and output are omitted). Further, V _R of the bias generation circuit 16 is a variable resistor for adjusting the amount of current, and E is a DC power supply.

Here, the first wiring pattern 14 and the second wiring pattern 15 formed on the chip 12 have portions facing each other with a predetermined width and length, and the capacitance C is provided at the facing portion. That is, the equivalent capacitance C determined by the facing area (width × length), the facing distance, the dielectric constant of the insulating material interposed between the patterns, and the like is formed. Figure 3
FIG. 6 is a chip structure diagram showing in detail the vicinity of a facing portion of a first wiring pattern 14 and a second wiring pattern 15. In this figure, reference numeral 20 denotes a silicon substrate (hereinafter referred to as a substrate), on which a first wiring pattern 14 (for example, Nb) is formed and a predetermined dielectric layer 21 (for example, Nb _2).
Second wiring pattern 15 facing each other with O ₅ ) interposed therebetween
(For example, Nb) is formed. The upper portion of the second wiring pattern 15, the first insulating layer 22 (e.g., S _i O _2),
Superconducting ground plane 23 (eg Nb) and second insulating layer 2
4 (e.g., S _i O ₂₎ are sequentially laminated, these layers 22
The second wiring pattern 15 and the Josephson circuit group 26 are electrically connected to each other through a hole 25 penetrating through .about.24. i _dc is a DC bias current from the bias generation source (see reference numeral 16 in FIG. 2), and i _ac is an alternating current induced in the secondary winding (see reference numeral 13b in FIG. 2) of the matching transformer.

In such a configuration, the matching transformer 1
When a high-frequency current i is flown into the primary winding 13a of No. 3, the above high-frequency current i
An alternating current i _ac having a magnitude corresponding to is induced, and this alternating current i _ac flows into the second wiring pattern 15 via the first wiring pattern 14 and the capacitor C. A DC bias current i _dc is supplied from the bias generation circuit 16 to the second wiring pattern 15, and the Josephson circuits J _{1 to} J _n.
(In FIG. 3, the Josephson circuit group 26) is supplied with a combined current of the alternating current i _ac and the direct current bias current i _dc .

As described above, according to the present embodiment, impedance matching is performed by the matching transformer 13, so that a terminating resistor, which is disadvantageous in terms of power consumption, can be eliminated. Therefore, it is possible to simplify together, the thermal design for maintaining the low temperature operation of the Josephson circuit J ₁ through J _n can be miniaturized current source 10. Further, the direct current system and the alternating current system are separated by an equivalent capacitance C (not a substantial capacitance device) formed between the first wiring pattern 14 and the second wiring pattern 15. Therefore, it is not necessary to separately form a capacitor or the like that requires a large area.

Here, for example, the frequency of the high frequency current i is set to 1
00MHz, the Josephson circuit impedance to 0.
If it is set to 1Ω, a large capacitance (thus a large area) of about 100 nF is required in calculation. If this is to be realized with an actual capacitance device (eg, capacitor), a large area corresponding to the electrode size must be secured on the chip, or if it is difficult to secure it, it must be built on another chip. I have to. On the other hand, in the present embodiment, since the width and length of the wiring pattern originally required as the current path are expanded to form the equivalent capacitance C, only the area corresponding to the expansion is newly secured. do it. Therefore, there is a unique merit that the occupied area on the chip can be reduced and the chip can be easily manufactured, as compared with the case where a substantial capacitance device is built.

The present invention is not limited to the above embodiment, and various modifications can be considered within the intended range. Other preferable examples will be listed below.
In each of the following embodiments, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. [Second Embodiment] In FIG. 4, reference numerals 30 to 33 _denote divided wiring patterns provided for each of the Josephson circuits J _{1 to} J _n , which together form a second wiring pattern 34. Each of the divided wiring patterns 30 to 33 is
The first wiring pattern 14 has small portions facing each other with a predetermined width and length, and each facing portion has a facing area (width × width).
The division capacitors C _{30 to} C ₃₃ that are determined by the length), the facing distance, the dielectric constant of the insulating material interposed between the patterns, and the like are formed. Therefore, the additive combined capacitance C of the division capacitors C _{30 to} C ₃₃ is equivalently formed between the first wiring pattern 14 and the second wiring pattern 34.

According to this embodiment as well, the same effect as that of the first embodiment can be obtained, and since the capacitance is divided into a plurality of parts,
It is possible to improve the resistance to noise such as static electricity generated during the manufacturing process or during packaging. [Third Embodiment] In this embodiment, the upper and lower relations of the first wiring pattern and the second wiring pattern of the first embodiment are interchanged. That is, as shown in FIG.
The first wiring pattern 35 for supplying _ac and the second wiring pattern 3 for supplying DC bias current i _dc
6 is formed on the upper layer. [Fourth Embodiment] In this embodiment, the upper and lower positions of the first wiring pattern and the second wiring pattern of the second embodiment are interchanged. That is, as shown in FIG.
The first wiring pattern 37 for supplying _ac and the second wiring pattern 3 for supplying DC bias current i _dc
8 (formed by a plurality of divided wiring patterns 39 to 42). [Fifth Embodiment] This embodiment, as shown in FIG.
Of the first wiring pattern 4 by duplicating the wiring pattern 43 of
It is in line with 4. That is, the second wiring pattern 43 is formed on the lower layer of the first wiring pattern 44 and the plurality of wiring patterns 45 to 48 formed on the upper layer of the first wiring pattern 44. And one wiring pattern 49. According to such a configuration,
Since a large number of capacitors are formed between the first wiring pattern 44 and the respective wiring patterns 45 to 49 that form the second wiring pattern 43, a large combined capacitance is secured for the area occupied by the wiring patterns. can do. [Sixth Embodiment] In this embodiment, the upper and lower relations of the first wiring pattern and the second wiring pattern of the fifth embodiment are interchanged. That is, as shown in FIG. 8, one wiring pattern 51 is formed in the upper layer of the first wiring pattern 50, and a plurality of wiring patterns 52 to 55 are formed in the lower layer of the first wiring pattern 50. Are formed, and the one wiring pattern 51 and the plurality of wiring patterns 52 to 55 form a second wiring pattern 56.

[0018]

According to the present invention, since impedance matching is performed by the matching transformer, the terminating resistor can be eliminated. Therefore, it is possible to suppress wasteful power (that is, heat generation), and it is possible to realize a power supply device of a Josephson circuit whose thermal design is easy. Further, the first wiring pattern and the second wiring pattern form equivalent capacitances for separating the direct current system and the alternating current system, so that it is not necessary to independently form a capacitive device (capacitor, etc.) The production can be facilitated.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a first embodiment.

FIG. 3 is a chip structure diagram showing in detail the vicinity of a facing portion of a first wiring pattern and a second wiring pattern.

FIG. 4 is a configuration diagram of a second embodiment.

FIG. 5 is a configuration diagram of a third embodiment.

FIG. 6 is a configuration diagram of a fourth embodiment.

FIG. 7 is a configuration diagram of a fifth embodiment.

FIG. 8 is a configuration diagram of a sixth embodiment.

FIG. 9 is a waveform diagram of a power supply current.

FIG. 10 is a conventional conceptual configuration diagram.

[Explanation of symbols]

i: high frequency current i _ac : alternating current i _dc : direct current bias current J _{1 to} J _n : Josephson circuit 10: current source 11: line 13 matching transformer 13 a: primary side winding 13 b: secondary side winding 12: Chip 14: First wiring pattern 15: Second wiring pattern 34: Second wiring pattern 35: First wiring pattern 36: Second wiring pattern 37: First wiring pattern 38: Second wiring pattern 43: second wiring pattern 44: first wiring pattern 50: first wiring pattern 56: second wiring pattern

Claims (1)

[Claims] 1. A high frequency current generated by a current source is led to a primary winding of a matching transformer through a line having a predetermined characteristic impedance, and an alternating current induced in a secondary winding of the matching transformer is supplied to a chip. The above first wiring pattern and the second wiring pattern on the same chip that is capacitively coupled to the first wiring pattern are supplied to the Josephson circuit, and a predetermined DC bias current is supplied to the second wiring pattern. A power supply device for the Josephson circuit, characterized in that the power is supplied to the Josephson circuit through the power supply device.