JPH053030B2 - - Google Patents
Info
- Publication number
- JPH053030B2 JPH053030B2 JP61004742A JP474286A JPH053030B2 JP H053030 B2 JPH053030 B2 JP H053030B2 JP 61004742 A JP61004742 A JP 61004742A JP 474286 A JP474286 A JP 474286A JP H053030 B2 JPH053030 B2 JP H053030B2
- Authority
- JP
- Japan
- Prior art keywords
- vector
- loops
- unit
- processing
- execution order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Devices For Executing Special Programs (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP474286A JPS62163168A (ja) | 1986-01-13 | 1986-01-13 | ベクトル処理方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP474286A JPS62163168A (ja) | 1986-01-13 | 1986-01-13 | ベクトル処理方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62163168A JPS62163168A (ja) | 1987-07-18 |
JPH053030B2 true JPH053030B2 (enrdf_load_html_response) | 1993-01-13 |
Family
ID=11592367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP474286A Granted JPS62163168A (ja) | 1986-01-13 | 1986-01-13 | ベクトル処理方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62163168A (enrdf_load_html_response) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2844492B1 (fr) | 2002-09-12 | 2005-06-10 | Valeo Systemes Dessuyage | Agencement de fixation d'un balai d'essuie glace sur un bras |
JP6555005B2 (ja) * | 2015-08-21 | 2019-08-07 | 日本電気株式会社 | 最適化装置、方法およびプログラム |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58149567A (ja) * | 1982-02-27 | 1983-09-05 | Fujitsu Ltd | ベクトル・レングス制御範囲融合処理方式 |
-
1986
- 1986-01-13 JP JP474286A patent/JPS62163168A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62163168A (ja) | 1987-07-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Padua et al. | Advanced compiler optimizations for supercomputers | |
US6202204B1 (en) | Comprehensive redundant load elimination for architectures supporting control and data speculation | |
US5303377A (en) | Method for compiling computer instructions for increasing instruction cache efficiency | |
US4251861A (en) | Cellular network of processors | |
KR100290269B1 (ko) | 추론적명령에있어서의예외처리 | |
US5526499A (en) | Speculative load instruction rescheduler for a compiler which moves load instructions across basic block boundaries while avoiding program exceptions | |
US5619680A (en) | Methods and apparatus for concurrent execution of serial computing instructions using combinatorial architecture for program partitioning | |
US5339429A (en) | Parallel processing system and compiling method used therefor | |
US5247696A (en) | Method for compiling loops having recursive equations by detecting and correcting recurring data points before storing the result to memory | |
Chamberlin | The" single-assignment" approach to parallel processing | |
JPH04336378A (ja) | 情報処理装置 | |
JPH053030B2 (enrdf_load_html_response) | ||
Foley et al. | Efficient partitioning of fragment shaders for multiple-output hardware | |
Amamiya | Data flow computing and parallel reduction machine | |
Dhamdhere et al. | Characterization of program loops in code optimization | |
Nicolau | Loop quantization: unwinding for fine-grain parallelism exploitation | |
JPH02132525A (ja) | コンパイル方法 | |
JPS6319906B2 (enrdf_load_html_response) | ||
Hamel et al. | An optimizing C* compiler for a hypercube multicomputer | |
JPH046020B2 (enrdf_load_html_response) | ||
JPH01123328A (ja) | 計算機方式 | |
Cui et al. | Multithreaded parallel computer model with performance evaluation | |
Shin et al. | Identification of microprogrammable loops for problem oriented architecture synthesis | |
JPS6321946B2 (enrdf_load_html_response) | ||
Reif | Code motion |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |