JPH0530216B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention measures the edge interval corresponding to the repetition period of a rectangular wave signal obtained by waveform shaping an FG signal output from a frequency generator (FG), for example. The present invention relates to an edge spacing measuring device.

[Background technology and its problems]

Conventionally, for example, in a video tape recorder, a rotating drum to which a magnetic head is attached needs to be rotated at a constant rate of 30 Hz in the case of the NTSC system in response to a vertical synchronization signal of a video signal. To do this, the rotational speed of the motor for the rotating drum is detected by a frequency generator (hereinafter referred to as FG).
A method of controlling the rotational speed of the motor based on this detection result is generally known. As an example, as shown in FIG. 1, a motor 1 is constructed integrally with an FG 2, and a magnetic ring 4 having a plurality of magnetic poles magnetized along the rotational direction is attached to a rotating shaft 3 of the motor 1. ing. The magnetic pole of this magnetic ring 4 is detected by a magnetically sensitive head 5 made of a ferromagnetic metal magnetoresistive element or the like. That is, the magnetically sensitive head 5 of the FG 2 generates a substantially sinusoidal waveform that changes in accordance with changes in the magnetic pole of the magnetic ring 4.
FG signal is being output. This FG signal is shaped by the waveform shaping circuit 6 into a rectangular waveform signal as shown in FIG. 2, and sent to the rising edge detection circuit 7, which is an example of an edge detection circuit. The rise detection circuit 7 detects the rising points P ₁ , P ₂ , P _{3 .} . . of the waveform-shaped FG signal, and detects the time between these rising points P ₁ , P ₂ , P ₃ . The rising interval corresponding to the repetition period of
The FG periods T _FG1 , T _FG2 , . . . are sequentially measured by the counter 8. FG period measured by counter 8
T _FG1 , T _FG2 , ... are D/A conversion circuits (digital/
After being sequentially sent to an analog conversion circuit (analog conversion circuit) 9 and converted into an analog signal, it is sent to a comparison circuit 10 and compared with a reference value, and the error is sent to a motor drive circuit 11 as an error signal. In response to this error signal, the motor drive circuit 11 controls the rotational speed of the motor 1 to a predetermined value.

Although it is possible to apply servo to some extent using such a control system, increasing the frequency of the clock supplied to the counter 8 in order to improve the measurement accuracy of the FG period increases the scale of the hardware and requires high-speed operating elements. is required, which causes an increase in costs. In addition, since this control system is composed only of hardware, once it is set to a predetermined value, the predetermined value cannot be easily changed. There is a problem in that when a change occurs, it cannot be responded to immediately and the degree of freedom is low.

Also, instead of counter 8 in the hardware configuration,
It is also possible to measure the FG period by configuring a counter using a CPU (central processing circuit) and a program called software. In this case, even if the standards change as mentioned above, it can be handled simply by rearranging the program, but since the time that is the unit of counting operation, that is, the unit of measurement, is determined by the number of steps in the loop by the program, There is a problem that the measurement accuracy is inferior to that when the counter 8 is used.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned conventional problems. For example, the present invention measures edge intervals such as rise intervals of a rectangular wave signal obtained by waveform shaping an FG signal with high precision, and also makes various changes. The purpose is to increase the degree of freedom in measurement so that even if a problem occurs, it can be dealt with immediately.

[Summary of the invention]

In order to achieve the above-mentioned object, the edge interval measuring device according to the present invention detects the edges of the input rectangular wave signal by detecting the level of the input rectangular wave signal at least at each timing determined according to the program. , a CPU system that inputs count value data and outputs a clear signal at this edge detection timing, measures the interval between these edge detection timings, and performs data calculation;
A counter that performs clock measurement in a finer measurement unit than the clock measurement unit by the CPU system, and a counter that instantly detects the edge of the input rectangular wave signal and causes the counter to start counting, and also receives the clear signal from the CPU system. and an edge detection circuit that generates a signal to stop the counting operation of the counter in accordance with the above. calculate the edge interval data of the input rectangular wave signal based on the counted value data from the counter and the measured value data of the edge detection timing interval from one edge to the next edge. This is a characteristic feature.

〔Example〕

Embodiments of the edge interval measuring device according to the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing a rising interval measuring device to which the present invention is applied. This rising interval measuring device measures the rising interval as an example of the edge interval. First, the basic operation will be explained while clarifying the configuration using the time charts of FIGS. 3 and 4. Signal input terminal 21
For example, a repetition frequency of 720 Hz as shown in Figure 4A is generated from an FG (frequency generator) not shown.
A rectangular waveform FG signal _SFG whose waveform has been shaped to a certain degree is supplied. This FG signal S _FG is the rising edge detection circuit 22
and a CPU (central processing circuit) 23. For example, the CPU 23 operates at a constant period T _LP as shown in FIG. 4B.
An edge, that is, a rising or falling edge, is detected by detecting whether the FG signal _SFG is at H level (high level) or L level (low level). Further, the CPU 23 performs a counting operation using this detection period _TLP as a time measurement unit. In addition,
Here, to simplify the explanation, the detection period is
Although T _LP was assumed to be constant, the number of steps in the loop to detect the H level and the number of steps in the loop to detect the L level determined by the program were different, and the cycle of each detection was also considered to be different. It will be done. However, if the number of steps is known in advance, time data corresponding to count value data _DK by the CPU 23, which will be described later, can be obtained.

Then, first, the rising edge detection circuit 22 detects the FG.
The rise of the signal _SFG (change from L level to H level) is detected at time _t1 . Then, the enable signal _SEN is sent from the rising edge detection circuit 22 to the counter 24, and the counting operation of the counter 24 is started as shown in FIG. 4C. It is assumed that the counter 24 performs a counting operation and measures time in a measurement unit finer than the time measurement unit by the CPU 23 (in this embodiment, the detection period T _LP ). Therefore, the counter 24 can measure time with higher resolution, that is, with higher precision than the CPU 23.

Next, at time _t2 , which is delayed from the rising edge detection circuit 22,
The rise of the FG signal _SFG is detected by the CPU 23. Then, a clear signal S _C is sent from the CPU 23 to the rising edge detection circuit 22, the rising edge detection circuit 22 is cleared, and the counting operation of the counter 24 is completed. Then, the count value data _dK of the counter 24 at this time is taken into the CPU 23 via the gate circuit 25. At this point, the counter 24 is cleared.

Incidentally, the count value data d _K is the k _- th (k=1, 2, 3,...
...) indicates that the count value data is from the counter 24 corresponding to the rising edge detection.

Subsequently, the CPU 23 detects that the FG signal _SFG falls at time _t3 , confirming that approximately half of the rising interval to be measured, that is, the FG period _TFGK, has elapsed. Next, the rising edge of the FG signal _SFG is detected by the rising edge detection circuit 22 at time _t4 .
Then, the enable signal S EN is sent from the rising edge detection circuit 22 to the counter 24, and the enable signal S _EN is sent to the counter 24.
The counting operation of the counter 24 is restarted as shown in FIG. Then, the rise of the FG signal _SFG is detected by the CPU 23 at time _t5 , later than the rise detection circuit 22. Then, a clear signal S _C is sent from the CPU 23 to the rising edge detection circuit 22, the rising edge detection circuit 22 is cleared, and the counting operation of the counter 24 is completed. Then, the count value data d _K+1 of the counter 24 at this time is taken into the CPU 23 via the gate circuit 25 . At this point, the counter 25 is cleared. Note that count value data d _K+1 indicates count value data from the counter 24 corresponding to the (k+1)th rise detection of the FG signal _SFG by the rise detection circuit 22.

Further, the CPU 23 calculates count value data D _K from time t ₂ to time _{t 5} . This count value data D _K is FG
The CPU 23 detects the k-th rising edge and the k+1-th rising edge of the signal _SFG , respectively, and shows data measured by the CPU 23 as an interval between these rising detection timings. In this embodiment, count value data was obtained because the detection cycle of the H level and L level of the CPU 23 was constant _TLP , but even when the detection cycle is different, it is possible to obtain data from time _t2 to
It is possible to obtain data for times up to t ₅ .

Then, each count value data d _K ,
The operation d _K −d _K +1 +D _K is performed on d _K+1 and D _K ,
Data corresponding to the rising interval of the FG signal _SFG , that is, the FG period _TFGK, can be obtained. Furthermore, this data is transferred from the CPU 23 to the D/D with a latch.
A conversion circuit (digital/analog conversion circuit) 26
and output from the signal output terminal 27 as an analog output signal S _OUT . Note that this output signal
S _OUT is sent to a comparison circuit (not shown) and compared with a reference value to obtain an error signal.

The basic operations have been described above, but as will be described later, the operations described above are performed continuously in a steady state.

Figure 5 shows the rise interval measuring device described above.
This is a flowchart showing the operation of the CPU 23 in detail. This will be explained according to this flowchart.

First, in step S1, it is determined whether the FG signal S _FG is at H level or not. If YES, the process goes to step S3, but if NO, the process goes to step S2, where counting and other operations are performed and then the process is started again. step
Return to S1. That is, until the YES condition is satisfied, the loop of steps S1 and S2 is repeated. If the YES condition is satisfied, the process advances to step S3, and the counted value data of the counter 24 at that point is sent to the gate circuit 2.
5 into register R _A. The count value data taken into register R _A is transferred to register R _B in step S4.

In step S5, it is determined whether the FG signal _SFG is at the L level, and if YES, the process proceeds to step S7.
However, in the case of NO, the process proceeds to step S6, where a counting operation and other operations are performed, and then returns to step S5. If the YES condition is satisfied, step S7
Then, it is determined whether the FG signal _SFG is at the H level. If YES, proceed to step S9,
If NO, the process advances to step S8, where a counting operation and other operations are performed, and then returns to step S7.

Here, the rise detection of the FG signal _SFG by the program is generally performed by detecting the L level and then the H level.

Note that the period for detecting the L level of the FG signal _SFG mentioned above is determined by the loop consisting of step S5 and step S6, and the period for detecting the H level is determined by the loop consisting of step S7 and step S8. Ru.

If the YES condition is satisfied in step S7, the process advances to step S9, and the count value data of the counter 24 at that time is taken into the register R _A via the gate circuit 25. Here, each register currently
For example, each count value data by the counter 24 stored in R _A and R _B is used as lower data, and
The count value data by the CPU 23 is used as upper data. Between this upper data and lower data, for example, upper data = lower data × n (n = natural number)
It is assumed that the relationship holds true.

Then, in step S10, a lower order calculation is performed in which the count value data stored in register R _B is subtracted from the count value data stored in register R _B , and lower order data Δd is determined. That is,
Assuming that count value data d _K+1 and d _K as shown in FIG. 4C are currently stored in each register R _A and R _B , respectively, the kth lower order data Δd _K from the start of operation
=d _K −d _K+1 .

In step S11, it is determined whether the lower-order data Δd obtained in step S10 is greater than or equal to zero, and YES is determined.
In the case of YES, the process proceeds to step S13, but in the case of NO, the process proceeds to step S12. In this step S12,
A correction calculation is performed to borrow data from the upper data to make the lower data greater than or equal to zero, and the process returns to step S11.

Then, if the YES condition is satisfied, the step
Proceeding to S13, lower-order calculations are performed using the data of the starting point position of the slope wave, so-called ramp wave. That is, as shown in FIG. 4D, for example, this slope wave has a constant starting point position, a constant slope, and
and a width T _R of the slope portion, and in analog use, it is used to detect a change in the rise time of the FG signal _SFG as a change in level. Here, it is used as data for detecting a change in time rather than a change in level.
Furthermore, the data of the starting point position of the above-mentioned slope wave is assumed to be R, the lower data of this data is R _L , and the upper data is R _U. Then, a low-order calculation is performed in which the low-order data R _L representing the starting point position of the slope wave is subtracted from the low-order data from step S11, and new low-order data W _L is determined.

In step S14, it is determined whether this lower data W _L is greater than or equal to zero, and if YES, the step
Proceed to step S16, but if NO, proceed to step S15. In this step S15, a correction calculation similar to that in step S12 is performed, and the process returns to step S14 again. Then, if the YES condition is satisfied, the process advances to step S16 and upper level calculation is performed. That is, the count value data currently obtained by the CPU 23, for example, D _K shown in FIG _. The upper data W _U is found.

In step S17, it is determined whether this upper data W _U is greater than or equal to zero. If YES, the process advances to step S18, but if NO, processing outside the predetermined range is performed, for example, invalidating the upper data W _U and updating the previous data. Processing is performed that uses the calculated data as is. In step S18, the FG period T _FGK is calculated from the currently obtained lower data W _L and upper data W _U.
Data W corresponding to is created. Step S19
Now, this data W is the width of the slope part of the slope wave mentioned above.
It is determined whether or not it is below T _R. If YES, the process proceeds to step S20, but if NO, the above-mentioned out-of-range processing is performed.

In step S20, data W from step S19 is rounded according to the number of bits handled by the D/A conversion circuit 26, and is sent to the D/A conversion circuit 26. In the above data rounding, for example, the number of bits of data W is set to n,
The number of bits handled by the D/A conversion circuit 26 is m(n
>m), when the m+1st bit of data W is 0, m bits are used as is, and when it is 1, 1 is added to m bits of data and used.

In this way, the output signal S _OUT corresponding to one FG period T _FGK of the FG signal S _FG can be obtained. Then, in order to perform further continuous operation, the process advances to step S21, where processing is performed to transfer the count value data currently stored in register _RA to register _RB , and the process returns to step S5 again. That is, step S1~
Step S4 is performed only once after the start of operation, and in steady state, steps S5 to S5 are performed only once.
S21 is repeated and continuous operation is performed.

As mentioned above, according to the rise interval measuring device of this embodiment, the program (software)
The CPU 23 constitutes a counter, and the CPU 23 performs rough measurements, and the counter 24 performs fine measurements, so that the rise interval, that is, the FG period _TFGK can be measured with high precision. Therefore, if you configure a control system for the rotational speed of the motor using FG using such a rise interval measuring device, the accuracy of measuring the FG period T _{and FGK} will not deteriorate compared to the conventional configuration using only hardware. Furthermore, simply by rearranging the program, data on the starting point position of a slope wave can be changed, for example, and various changes can be made, so there is a high degree of freedom in measurement.

Further, as shown in FIG. 6, the present invention uses an up-down counter 30 as a counter, and
It can also be configured using two rise detection circuits 31 and 32. That is, for example, at time _t1 shown in _FIG.
When the rising edge of is detected, an enable signal _SEN1 is generated to cause the up-down counter 30 to start counting in the up direction. This rise detection circuit 31 generates a clear signal when the CPU 23 detects the H level of the FG signal S _FG at time _t2 .
Cleared by S _C1 , up-down counter 3
The zero counting operation is now terminated.

On the other hand, at time _t4 , the rise detection circuit 32 causes the FG
Enable signal when the rising edge of signal S _FG is detected
_{S_EN2} is generated and causes the up-down counter 30 to start counting in the countdown direction. This rising edge detection circuit 32 is activated by the CPU 23 at time _t5 .
When the L level of the signal _SFG is detected, it is cleared by the clear signal _SC2 generated, and the counting operation of the up-down counter 30 is completed. With this configuration, the above-mentioned d _K −d _K+1
can be performed by the up-down counter 30. However, this configuration is effective only when performing intermittent measurement, and when performing continuous measurement, another counter is required. Therefore, when performing continuous measurements, it is preferable to use an apparatus having the configuration shown in FIG. 3.

In this embodiment, the count value data is obtained by detecting the rising edge of the FG signal _SFG , but it is of course possible to obtain the counting value data by detecting the falling edge of the FG signal SFG. Furthermore, when the duty of the FG signal _SFG is 50%, measurement may be performed by detecting both the rising edge and the falling edge to obtain count value data. Furthermore,
The input signal is not limited to the FG signal, but may be a rectangular wave signal, and the edge interval, that is, the rising interval or falling interval of the rectangular wave signal can be measured.

〔Effect of the invention〕

As is clear from the description of the embodiments described above, according to the present invention, a counter is configured in the CPU by a program, that is, software, and time is measured in coarse measurement units by the CPU, and the hardware configuration outside the CPU is configured. Because the counter measures time in fine measurement units, it is possible to measure the edge interval of a square wave signal with high precision, and when making various changes, it is possible to simply rearrange the program that operates the CPU. It is possible to increase the degree of freedom in measurements that can be taken immediately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a motor rotational speed control system using FG, and FIG. 2 is a waveform diagram showing a waveform-shaped FG signal. FIG. 3 is a block diagram showing an embodiment of the edge interval measuring device according to the present invention, FIG. 4 is a time chart showing the operation of the above embodiment, and FIG.
Flowchart showing detailed CPU operation, Part 6
The figure is a block diagram showing another embodiment of the edge interval measuring device according to the present invention. 22, 31, 32...Rise detection circuit, 23...
...CPU, 24...Counter, 30...Up-down counter.

Claims (1)

[Claims] 1. Detecting the edge of the input rectangular wave signal by detecting the level of the input rectangular wave signal at least at each timing determined according to the program;
A CPU system inputs count value data and outputs a clear signal at this edge detection timing, measures the interval between these edge detection timings, and calculates the data. A counter that performs measurement; and a signal that instantaneously detects the edge of the input rectangular wave signal to cause the counter to start counting, and to stop the counting operation of the counter in response to the clear signal from the CPU system. and an edge detection circuit, the CPU system detects count value data from the counter at one edge detection timing, count value data from the counter at the next edge detection timing, and one of these. An edge interval measuring device characterized in that data of the edge interval of the input rectangular wave signal is calculated based on measurement value data of the edge detection timing interval from one edge to the next edge.