JPH05300392A - Control circuit for horizontal deflection current, horizontal deflection circuit provided with the control circuit, high voltage horizontal deflection integrated circuit and pin cushion distortion correction circuit - Google Patents

Abstract

PURPOSE:To control a horizontal deflection current without varying a voltage of a drive power supply 3. CONSTITUTION:A series circuit comprising a 1st switch block circuit 13 and a 2nd switch block circuit 14 is connected between a primary coil 2 of a flyback transformer 1 and ground. A series circuit comprising a deflection yoke 7, an S-shaped correction capacitor 8, and a 3rd switch block circuit 18 is connected between ground and the series connection of the switch block circuits 13, 14. A 3rd switch block circuit 18 consists of a parallel circuit comprising a capacitor 20, a diode 21 of reverse polarity connection and a MOSFET 22. The deflection current is increased by quickening the timing of OFF of the MOSFET 22 for a blanking period and the deflection current is decreased by slowing down the timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection current control circuit for controlling the flow rate of a sawtooth wave horizontal deflection current, a horizontal deflection circuit equipped with this control circuit, a high voltage / horizontal deflection integrated circuit, and The present invention relates to a pincushion distortion correction circuit.

[0002]

2. Description of the Related Art FIG. 5 shows a high voltage / horizontal deflection integrated side circuit in which a high voltage generating side circuit and a deflection side circuit are integrated. In this circuit, a drive power supply 3 is connected to one end side (winding end end side in this figure) of a primary coil 2 of a flyback transformer 1, and the other end side (winding start end side) of the primary coil 2 outputs a horizontal output. The transistor 4, the damper diode 5, and the resonance capacitor 6 are connected to the ground side through a parallel circuit. A series circuit of the deflection yoke 7 and the S-shaped correction capacitor 8 is connected in parallel to the parallel circuit of the horizontal output transistor 4, the damper diode 5, and the resonance capacitor 6.

The high-voltage end side of the secondary coil 10 of the flyback transformer 1 is connected to the anode of a cathode ray tube (not shown) via a half-wave rectifying circuit composed of a high-voltage rectifying diode 11 and a high-voltage capacitor 12. In this circuit, the portion except the series circuit of the deflection yoke 7 and the S-shaped correction capacitor 8 functions as a high-voltage generation side circuit, and the primary side circuit of the flyback transformer 1 including the deflection yoke 7 and the S-shaped correction capacitor 8 is It functions as a circuit on the deflection side.

According to this circuit, a horizontal drive signal is applied to the horizontal output transistor 4 from a horizontal drive circuit (not shown), so that the switching operation of the horizontal output transistor 4 and the cooperation of the damper diode 5 cause a sawtooth shape. A horizontal deflection current of the wave is produced and this horizontal deflection current is applied to the deflection yoke 7. On the other hand, a series resonance of the deflection yoke 7 and the resonance capacitor 6 produces a collector pulse (flyback pulse), and the collector pulse is generated by the flyback transformer 1.
After being boosted by, it is applied to the anode of the cathode ray tube as a high voltage output voltage through a half-wave rectification circuit.

[0005]

Recently, multi-scan type display devices and television receivers having a wide driving band of horizontal deflection frequency have been used. In a multi-scan type display device of this type, when the horizontal deflection frequency band changes, the voltage of the DC input power supply of the horizontal deflection circuit (voltage of the driving power supply 3) is changed to change the flow rate of the horizontal deflection current. Means are provided for controlling and keeping the screen amplitude of the cathode ray tube constant. However, when the voltage of the DC input power supply is changed, the output voltage extracted by the scanning period rectification on the secondary side of the flyback transformer changes in proportion to the DC input voltage. Therefore, the secondary side of the flyback transformer 1 is changed. To 3
When a coil for extracting the next output is provided and an output that does not fluctuate due to a change in the horizontal deflection frequency is extracted from this coil, only the output by the blanking period rectification can be extracted, and the output by the blanking period rectification is 1 There is a problem that it cannot be applied to such a load because it has a property that the voltage fluctuation due to the ripple for each cycle is large and it is not suitable for a load with a low voltage and a large amount of current.

In order to inexpensively construct a CRT display device or a television receiver, as shown in FIG. 5, a high voltage / horizontal deflection integrated type circuit in which a high voltage side circuit and a deflection side circuit are integrated. Is desirable. But,
In such an integrated circuit, if a control function for stabilizing the high voltage that corrects the drop amount of the high voltage output voltage is added, the circuit on the deflection side is affected when the high voltage output voltage is corrected, and the high voltage output voltage There is a problem that the flow rate of the horizontal deflection current is changed in association with the control operation, resulting in screen distortion.

Further, in the conventional general left-right pincushion distortion correction, the reactor type correction circuit shown in FIG. 6 (a) has been adopted. In this circuit, the left-right pincushion distortion is corrected by causing a vertical synchronizing parabolic current to flow in the primary winding of the side pin transformer in which the secondary winding is connected in series with the deflection yoke. However, with this method, the collector pulse voltage on the primary side of the flyback transformer fluctuates, and accordingly, the 2
There is a problem that the high voltage output voltage, focus voltage, and screen voltage on the secondary side also change.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to perform horizontal deflection without being affected by the correction operation of the high-voltage output voltage and without changing the voltage of the driving power supply. A horizontal deflection current control circuit capable of controlling the flow rate of a current, a horizontal deflection circuit including the circuit, a high voltage / horizontal deflection integrated circuit, and a left and right pincushion distortion correction circuit are provided.

[0009]

In order to achieve the above object, the present invention is configured as follows. That is, the horizontal deflection current control circuit of the present invention is a circuit for controlling a horizontal deflection current of a sawtooth wave flowing in a series circuit of a deflection yoke and an S-shaped correction capacitor, wherein the deflection yoke and the S-shaped correction capacitor are connected in series. A parallel circuit of a switch element, a capacitor, and a diode is provided in the circuit path, and a switch control circuit that controls the flow rate of the horizontal deflection current by varying the OFF timing of the switch element during the blanking period is provided. It is characterized by that,
Further, the horizontal deflection circuit including the horizontal deflection current control circuit, the high voltage / horizontal deflection integrated circuit, and the left and right pincushion distortion correction circuit are also characteristic configurations of the present invention.

[0010]

In the present invention having the above-described structure, the horizontal output transistor performs a switching operation according to the horizontal drive signal in the same manner as the normal horizontal deflection current generating operation, so that the deflection current is generated in cooperation with the damper diode.
This deflection current is applied to the deflection yoke. Then, when the switch element of the parallel circuit is turned off in the blanking period,
A capacitor connected in parallel with this switch element,
The series capacitance of the S-shaped correction capacitor, the resonance capacitor, and the inductance of the deflection yoke resonate in series to generate a pulse voltage across the capacitors of the parallel circuit. The magnitude of the peak value of the pulse voltage increases as the timing of turning off the switch element increases, and the voltage across the S-shaped correction capacitor increases during the scanning period.
The flow rate of the horizontal deflection current flowing through the deflection yoke increases. On the other hand, if the timing of turning off the switch element is delayed, the voltage across the S-shaped correction capacitor decreases, so
The flow rate of the horizontal deflection current flowing through the deflection yoke is also reduced.
As described above, the flow rate of the horizontal deflection current flowing through the deflection yoke is controlled by controlling the OFF timing of the switch element during the blanking period.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a high voltage / horizontal deflection integrated type circuit having a horizontal deflection current control circuit according to the present invention. In the figure, one end side (winding end side) of the primary coil 2 of the flyback transformer 1 is connected to the drive power source 3, and is connected between the other end side (winding start side) of the primary coil 2 and the ground. Is provided with a series circuit of a first switch block circuit 13 and a second switch block circuit 14.

The first switch block circuit 13 comprises a parallel circuit of a resonance capacitor 6, a damper diode 5 and a horizontal output transistor (first switch element) 4,
A horizontal drive signal ((b) of FIG. 2) is applied to the base of the horizontal output transistor 4 as a first switch control signal. The second switch block circuit 14 is composed of a MOS FET 15 functioning as a second switch element, a parallel circuit of a diode 16 and a capacitor 17. First switch block circuit 13 and second switch block circuit 14
A series circuit of the deflection yoke 7, the S-shaped correction capacitor 8 and the third switch block circuit 18 is connected between the series connection part of the above and the ground. The third switch block circuit 18 is composed of a capacitor 20, a MOSFET 22 functioning as a third switch element, and a series circuit of a MOS FET 22 and an opposite diode 21. This deflection yoke 7
And S-shaped correction capacitor 8 and third switch block circuit
Amorphous bead core 23 in the path of the series circuit with 18
Is provided.

MO of the second switch block circuit 14
The gate of the SFET 15 has a second switch control signal (Fig. 2) synchronized with the horizontal drive signal from the high voltage correction signal circuit 24.
(C)) is added, and the deflection current correction signal circuit 19 which also functions as a switch control circuit is provided to the gate of the MOS FET 22 of the third switch block circuit 18.
To the horizontal drive signal, a third switch control signal ((e) in FIG. 2) is added.

Secondary coil of the flyback transformer 1
A series circuit of voltage dividing resistors 25 and 26 is connected to the high voltage side of 10. The voltage dividing resistors 25 and 26 perform resistance division to detect a high voltage output voltage. It is added to the side input terminal. The operational amplifier 27 compares the detected voltage of the high voltage output voltage with the reference voltage of the reference power source 28, and applies a signal corresponding to the amount of drop of the high voltage output voltage to the high voltage correction signal circuit 24 and the deflection current correction signal circuit 19, respectively. There is. The correction voltage signal circuit 24 synchronizes the second switch control signal with the narrowed ON pulse width with the horizontal drive signal as the drop amount of the high voltage output voltage increases, and
In addition to the gate of the S FET15, the deflection current correction signal circuit 19 uses the third switch control signal, which has an earlier OFF timing in the retrace line period, as a horizontal drive signal as the amount of drop of the high voltage output voltage increases. MOS in synchronization
It is added to the gate of FET22. In this embodiment, the deflection yoke 7, the S-shaped correction capacitor 8, the third switch block circuit 18, and the deflection current correction signal circuit 19 constitute a horizontal deflection current control circuit.

This embodiment is constructed as described above. Next, the circuit operation will be described with reference to the circuit diagram of FIG. 1 and the time chart of FIG. First, when the horizontal transistor 4 is turned on in accordance with the horizontal drive signal in the state where the electric charge is not accumulated in the capacitor 17 of the second switch block circuit 14, the primary coil 2, the diode 16 and the horizontal output transistor are driven from the drive power source 3 side. The current I _N1 flows through the path through 4 to the ground. At this time, if the power supply voltage of the driving power supply 3 is E _B and the inductance of the primary coil 2 is L ₁ , I _N1 increases in accordance with the linear slope of E _B / L ₁ .

On the other hand, during the period in which the horizontal output transistor 4 is on, as shown in FIG.
T22 is in the ON state. At this time, since the electric charge is accumulated in the S-shaped correction capacitor 8 in the direction in which the collector side of the horizontal output transistor 4 is positive and the ground side is negative, the deflection from the S-shaped correction capacitor 8 is made. The deflection current I is formed in a closed loop that returns to the S-shaped correction capacitor 8 through the yoke 7, the horizontal output transistor 4, and the MOS FET 22 in this order.
_DY flows. At this time, assuming that the voltage across the S-shaped correction capacitor 8 is V _CS and the inductance of the deflection yoke 7 is L _DY , the deflection current I _DY increases along the linear gradient of V _CS / L _DY (Fig. 2 (g)).

Next, when the horizontal output transistor 4 is turned off in accordance with the horizontal drive signal, the currents I _N1 and I _N
The current energy stored in the primary coil 2 and the deflection yoke 7 due to the flow of _DY flows into the resonance capacitor 6, and resonance occurs due to the series resonance of the parallel inductance of the primary coil 2 and the deflection yoke 7 and the capacitance of the resonance capacitor 6. A collector pulse voltage V _C1 is generated across the capacitor 6. In the first half of the generation period of the collector pulse voltage V _C1 , that is, in the first half of the blanking period, the MOS
When the FET 22 is turned off, a pulse voltage V _C3 is generated at both ends of the capacitor 20 due to the series resonance of the S-correction capacitor 8, the capacitor 20 having a smaller capacity, the resonance capacitor 6, and the inductance of the deflection yoke 7. ((F) of FIG. 2).

The magnitude of the peak value of the pulse voltage V _C3 has a correlation with the OFF timing of the MOS FET 22, and the earlier the OFF timing of the MOS FET 22, the larger the peak value. When the peak value of the pulse voltage V _C3 becomes large, the S-shaped correction capacitor 8
Since a larger amount of electric charge is stored in the positive direction on the collector side of the horizontal output transistor 4 and in the negative direction on the ground side, the value of the voltage V _CS across the S-shaped correction capacitor during the scanning period increases, so that V _CS / L _DY The value, that is, the current I _DY flowing through the deflection yoke 7 increases. On the contrary, when the turning-off timing of the MOS FET 22 is delayed, the peak value of the pulse voltage V _C3 generated at both ends of the capacitor 20 becomes small, so that the voltage V _CS at both ends of the S-shaped correction capacitor 8 also becomes small and the deflection The deflection current I _DY flowing through the yoke 7 decreases. Thus, within the blanking period, M
By controlling the OFF timing of the OS FET 22 by the third switch control signal from the deflection current correction signal circuit 19, the flow rate of the deflection current I _DY flowing through the deflection yoke 7 is controlled.

Next, the collector pulse voltage is generated by series resonance.
V_C1When reaches the peak, this time from the resonance capacitor 6
Deflection yoke 7, S-shaped correction capacitor 8, capacitor 20
A current flows through the path that returns to the resonance capacitor 6 via
Voltage across sensor 20 V_C3Is decreasing. This V_C3Is 0V
In the following cases, the diode 21 becomes conductive and this diode
Current continues to flow through 21. At this time, the MOS
 Since FET15 is in the ON state,
Vibration capacitor 6, MOS FET 15 and primary coil 2
The current also flows through the route through the
Pulse voltage V _C1Decreases and V_C1Is below 0V
Then, the damper diode 5 becomes conductive and the current continues to flow.
It

When the MOS FET 15 is turned off during the damper period during which the damper diode 5 is conducting, the pulse voltage V _C2 across the capacitor 17 is generated by series resonance due to the inductance of the primary coil 2 and the capacitance of the capacitor 17.
Occurs. The peak value of V _C2 becomes larger as the turning-off timing of the MOS FET 15 becomes earlier. The voltage across the primary coil 2 of the flyback transformer 1 is a value obtained by adding the voltage V _C2 across the capacitor 17 to the voltage E _B of the drive power source 3 during the pulse period (during the scanning period) of the capacitor 17, so that V _The larger the peak value of _C2, the more the primary coil 2
Is increased, the peak value of the collector pulse V _C1 generated by the resonance of the resonance capacitor 6 is increased, and the high-voltage output voltage E _H is corrected to be increased. In this way, by controlling the OFF timing of the MOS FET 15 by the second switch control signal from the high voltage correction signal circuit 24, the high voltage output voltage is stabilized and controlled.

As described above, this embodiment is a MOS FET
The deflection current I _DY is controlled by controlling the OFF timing of 22 and the high output voltage is controlled independently of the control of the deflection current I _DY by controlling the OFF timing of the MOS FET 15. Will be seen. Therefore, when the high-voltage output voltage drops, the decrease in the high-voltage output voltage is effectively corrected by advancing the timing of turning off the MOS FET 15 accordingly. Accordingly, a part of the electrostatic energy stored in the resonance capacitor 6 is extracted to the secondary side of the flyback transformer 1 to decrease the flow rate of the deflection current I _DY , but at this time, the MOS Since the turning-off timing of the FET 22 is advanced, the deflection current is controlled to increase, and as a result, the decrease in the deflection current due to the high voltage correction is compensated. Therefore, the deflection current I _DY does not change due to the correction of the high voltage output voltage, and the deflection current is stabilized.

The switch-on operation of the horizontal transistor 4 is performed when a current is flowing through the damper diode 5, and the on-operation of the MOS FET 15 is also performed when a current is flowing through the diode 16, and further, MOS
The switch-on operation of the FET 22 is also performed when the current is flowing in the diode 21, so that the zero-voltage switch-on operation is performed, and also when the horizontal output transistor 4 and the MOS FETs 15 and 22 are switched off, At the moment of switch-off, the voltage gradually changes along the series resonance curve, so that the zero-voltage switch-off operation state is achieved. Thus, the horizontal output transistor 4 and the MOS FETs 15 and 22 all perform zero-voltage switching operation. Since the switching noise is generated, since the switching operation of the horizontal output transistor 4 and the MOS FET 22 is performed within the blanking period, the noise during switching does not affect the screen at all.

Moreover, in this embodiment, the deflection yoke 7 and the S-shaped correction capacitor 8 are arranged so that the switching noise of the MOS FET 15 and the ringing of the flyback transformer 1 are not superimposed on the deflection current I _DY and affect the screen of the cathode ray tube. Since the amorphous bead core 23 is provided on the path of the series circuit of the third switch block circuit 18 and
It is possible to obtain a high-definition stable screen that is not affected by these switching noises and ringing.

FIG. 3 shows the effect of the screen characteristics of this embodiment in comparison with the conventional example. 5A shows an image on the screen when a rectangular white pattern is produced on the screen of the cathode ray tube by using the conventional circuit shown in FIG. In a high-voltage / horizontal-deflection integrated circuit without such a correction circuit, the high-voltage output voltage is reduced in the white pattern portion with high brightness, and as a result, a trapezoidal pattern with a wide lower portion is projected. (B) of the same figure
Tried to create a similar rectangular white pattern using a circuit with a high-voltage output voltage correction function, but with a circuit with this high-voltage correction function, the deflection current was transferred to the secondary side during high-voltage correction. Since it is pulled out and the deflection current is reduced accordingly, the pattern becomes slightly narrower in the lower part, contrary to (a) in the figure. On the other hand, in the circuit of this embodiment, the correction of the high-voltage output voltage and the correction of the deflection current are simultaneously performed, so that a stable rectangular white pattern without distortion is obtained as shown in FIG. Be done.

Further, according to the circuit of this embodiment, the voltage V _C3 across the capacitor 20 caused by the turning off of the MOSFET 22 during the blanking period (pulse period) and the voltage V across the S-shaped correction capacitor 8 during the scanning period are increased. _Since the increased amount of _CS acts to cancel each other, the above V
_{The peak} value of the collector pulse hardly changes due to the influence of the increase of _{C3 and} the increase of V _CS , and the high voltage output voltage can be stabilized without being influenced by the control operation of the deflection current I _DY. ..

Furthermore, in this embodiment, the magnitude of the deflection current I _DY can be arbitrarily controlled while the voltage of the driving power source 3 is kept constant by controlling the OFF timing of the MOS FET 22, so that, for example, When applied to a multi-scan type display device or the like, the tertiary output can be taken out from the flyback transformer 1 without any trouble, which is very advantageous in handling the circuit.

The present invention is not limited to the above-mentioned embodiments, and various embodiments can be adopted. For example, in the above embodiment, the second switch element and the third switch element are constituted by the MOS FETs 15 and 22, respectively, but these switch elements can be constituted by using other switch elements such as bipolar transistors.

In the above embodiment, the high voltage / horizontal deflection integrated circuit has been described, but the horizontal deflection current control circuit of the present invention is a circuit of the type in which a sawtooth wave deflection current is passed. The present invention can be applied to other circuits, for example, various other circuits such as a horizontal deflection circuit (horizontal deflection drive circuit) shown in FIG. 4 and a pincushion distortion correction circuit (not shown). Also in the case of the horizontal deflection circuit shown in FIG. 4, for example, a MOS functioning as a third switch element is used.
By controlling the OFF timing of the FET 22, the magnitude of the deflection current I _DY flowing in the deflection yoke 7 can be controlled arbitrarily. Also, when the circuit of the present invention is applied to the left and right pincushion distortion correction, by controlling the off timing of the switch elements such as the MOS FET 22, for example, the deflection current I _DY can be applied to the start and end portions of the vertical deflection cycle. The waveform can be controlled to be smaller and larger in the middle portion as shown in FIG. 7, whereby the left and right pincushion distortion is corrected. At this time, fluctuations in the high-voltage output voltage, the focus voltage, and the like due to the control of the horizontal deflection current hardly occur.

[0029]

According to the present invention, a parallel circuit in which a switch element, a capacitor and a diode are connected in parallel is provided in a path of a series circuit of a deflection yoke and an S-shaped correction capacitor, and an off timing of the switch element in a blanking period is set. Since it is configured to variably control the flow rate of the horizontal deflection current, the flow rate of the horizontal deflection current can be set arbitrarily by changing the timing of turning off the switch element without changing the voltage of the driving power supply. It becomes possible to control. Therefore, when applied to a multi-scan type display or the like, the flow rate of the deflection current can be controlled without changing the input voltage, and the tertiary output can be taken out from the flyback transformer without being affected by voltage fluctuations. ,
It is very advantageous in handling.

Further, although the horizontal deflection current control circuit of the present invention is applied to an inexpensive and simple circuit such as a high voltage / horizontal deflection integrated circuit, the deflection current has an influence on the control operation of the high voltage output voltage. Since it can be stabilized without being affected, it becomes an appearance in which a low-grade circuit is transformed into a high-grade circuit, and high-quality screen characteristics can be obtained.

Further, since the switch element performs zero voltage switching, it is possible to perform highly efficient circuit operation with almost no switching loss, and moreover, the switching operation is performed within the blanking period, so that the cathode ray tube A high-definition, high-quality screen can be obtained without the effects of switching noise or the like appearing on the screen.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a high-voltage / horizontal deflection integrated circuit including a horizontal deflection current control circuit according to the present invention.

FIG. 2 is a time chart showing a waveform of each part of the circuit of the embodiment.

FIG. 3 is an explanatory diagram showing screen characteristics of the embodiment in comparison with a conventional example.

FIG. 4 is a circuit diagram of another embodiment in which the horizontal deflection current control circuit according to the present invention is applied to a horizontal deflection circuit.

FIG. 5 is a circuit diagram of a general high voltage / horizontal deflection integrated circuit.

FIG. 6 is a circuit diagram of a left and right pincushion distortion correction circuit using a reactor system.

FIG. 7 is a waveform diagram of left and right pincushion distortion correction currents.

[Explanation of symbols]

 1 Flyback Transformer 2 Primary Coil 3 Drive Power Supply 4 Horizontal Output Transistor 6 Resonant Capacitor 7 Deflection Yoke 8 S-Shape Correction Capacitor 13 First Switch Block Circuit 14 Second Switch Block Circuit 15 MOS FET 16 Diode 17 Capacitor 18 Third Switch block circuit

Claims (4)

[Claims] 1. A circuit for controlling a horizontal deflection current of a sawtooth wave flowing in a series circuit of a deflection yoke and an S-shaped correction capacitor, wherein a switch element and a capacitor are provided in a path of the series circuit of the deflection yoke and the S-shaped correction capacitor. And a diode in parallel, and a horizontal deflection current control circuit provided with a switch control circuit that controls the flow rate of the horizontal deflection current by varying the OFF timing in the blanking period of the switch element. 2. A horizontal deflection circuit comprising the horizontal deflection current control circuit according to claim 1. 3. A high voltage / horizontal deflection integrated circuit comprising the horizontal deflection current control circuit according to claim 1. 4. A left and right pincushion distortion correction circuit comprising the horizontal deflection current control circuit according to claim 1.