JPH05252409A - High voltage generating circuit - Google Patents

Abstract

PURPOSE:To enhance the circuit efficiency and to prevent an undesirable influence exerted on a screen due to a turn-on switch operation of a MOSFET by executing a stabilizing operation of a high voltage output voltage by controlling a turn-off time point of the MOSFET in a period in which a reverse current is flowing to a driving power source through a low voltage coil from a resonance capacitor or a damper diode side. CONSTITUTION:To one end side of a low voltage coil of a fly-back transformer 11, a MOSFET17 and a driving power source 18 are connected in series, and to the MOSFET17, a diode 20 and a charge capacitor 21 are connected in parallel. Between the other end side of the low voltage coil 12 and a ground line, a parallel circuit of a transistor 13, a damper diode 14 and a resonance capacitor 15 are connected. To a gate of the MOSFET17, a driving pulse signal whose pulse width becomes narrow as a drop amount of a high voltage output voltage becomes large, is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage generating circuit for boosting a collector pulse and applying the boosted output to the anode of a cathode ray tube.

[0002]

2. Description of the Related Art A high voltage of several tens KV is applied to a cathode ray tube of a television receiver or a display device from a high voltage generating circuit. As this high voltage generation circuit, the flyback pulse generated by the horizontal output circuit is boosted by the flyback transformer, rectified and added to the anode of the cathode ray tube, and the flyback transformer has a low voltage coil side. Deflection current of sawtooth wave is generated by connecting deflection yoke and using flyback pulse.
A method of adding this to the deflection yoke is known, but this method of circuit corrects the high-voltage output voltage in order to stabilize the high-voltage output voltage by applying a correction voltage that corresponds to the drop amount of the high-voltage output voltage. There is a problem in that the operation interferes with the circuit operation on the deflection yoke side and adversely affects it. In recent years, in order to avoid interference between the circuit on the high voltage generation side and the circuit on the deflection yoke side, the circuit on the high voltage side and the deflection yoke side have a problem. It has been proposed that the circuit on the side is configured separately and independently. This kind of high voltage generation circuit generates a collector pulse (flyback pulse) in synchronization with the horizontal output circuit, boosts this collector pulse with a flyback transformer, rectifies this and adds it to the anode of the cathode ray tube. Is.

FIG. 12 shows a conventional high voltage generating circuit (Japanese Patent Laid-Open No. 222222/1990) which is separated from the circuit on the deflection yoke side. This circuit controls the ON period of the transistor 1 in accordance with the drop amount of the high voltage output voltage by signal processing of the signal applied from the horizontal drive circuit side and the detection signal of the high voltage output voltage. The larger the amount of drop, the larger the pulse width of the pulse control signal applied to the base of the transistor 1 ((b) of FIG. 13) and the magnitude of the collector current ((c) of FIG. 13).
It is intended to increase the peak value of the collector pulse generated by the OFF operation of (1) in FIG. That is, when the pulse width of the ON period of the transistor 1 becomes wider, the magnitude of the collector current that goes around the closed loop that returns to the diode 2, the diode 2, the low-voltage coil 3, and the output transistor 4 in order when the transistor 1 is turned OFF increases. Inevitably, the peak value of the collector pulse becomes large.
Thus, the width of the ON period of the transistor 1, that is,
By controlling the off time of the transistor 1, the peak value of the collector pulse is changed to stabilize the high voltage output voltage.

[0004]

However, in this type of high voltage generating circuit, the collector current flowing from the diode 2 to the diode 2 through the low voltage coil 3 and the output transistor 4 to the diode 2 in the section in which the transistor 1 is off is Flyback operation requires a large amount of energy, which causes a large current to circulate in a closed loop. Therefore, the circulation of the current causes a loss when passing through each circuit element, resulting in a problem of poor circuit efficiency.

In the conventional circuit, the transistor 1
Since the off operation is always performed during the scanning period of the television receiver or the display device, switching noise appears when the transistor 1 is off, which may adversely affect the screen.

Further, in the conventional circuit, the circuit operates so as to lower the output voltage as compared with the non-corrected state by applying the correction, and accordingly, the input voltage of the + B side drive power supply and the step-up ratio of the flyback transformer are increased. Need to be bigger,
There is a problem that the burden on the electronic components used increases.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to improve the circuit efficiency by eliminating the loss caused by circulating a large current after the transistor 1 is turned off, and The flyback transformer is operated by zero-voltage switching to turn off the switching elements such as transistors that generate collector pulses, to minimize noise generation during the scanning period, and to correct the output voltage higher than in the uncorrected state. It is an object of the present invention to provide a high-voltage generation circuit that can reduce the boosting ratio of the above and can reduce the burden on the electronic components used.

[0008]

In order to achieve the above object, the present invention is configured as follows. That is, in the high voltage generating circuit of the present invention, one end of the low voltage coil of the flyback transformer is connected to the ground side and the other end is connected to the driving power source side, and the low voltage coil has the first switch element and the resonance capacitor. In the connected high voltage generating circuit, a second switch element is provided on a path from the drive power source through the low voltage coil to the ground, and a reverse current flowing from the low voltage coil side to the drive power source during an off period of the second switch element. A resonance circuit in which a charge capacitor charged by a current is provided, and a part or all of the charge capacitor charged by the reverse current is connected to the first switch element. The capacitor is also used, and the inductance element is connected in parallel with the low-voltage coil of the flyback transformer. And that it, and it has also been a characteristic structure of the present invention, respectively the series circuit of the deflection yoke and the capacitor as an inductance element in parallel with the first switching element is connected.

[0009]

In the present invention having the above-described structure, during the ON period of the first switch element, the current on the drive power source side flows from, for example, the low voltage coil through the first switch element, and energy is accumulated in the low voltage coil. In this state, when the first switch element is turned off and the second switch element is turned on, the current on the drive power source side flows from the low voltage coil to the resonance capacitor, and the energy of the low voltage coil is transferred to and accumulated in the resonance capacitor. When the energy of the low voltage coil is completely transferred to the resonance capacitor, a reverse current flows from the resonance capacitor side through the low voltage coil to the driving power supply side. If the second switch element is turned off while this reverse current is flowing, the reverse current will flow through the charge capacitor, so the charge capacitor is charged and the voltage of the drive power supply and the charge capacitor are charged in the low voltage coil. The added voltage with the charged voltage is applied. The voltage charged in the charge capacitor becomes larger as the ON period of the second switch element becomes shorter and the period in which the reverse current flows to the charge capacitor becomes longer, so that the collector pulse generated by the resonance operation of the low voltage coil and the resonance capacitor becomes larger. The peak value of the pulse voltage of becomes large. On the contrary, when the ON period of the second switch element becomes long, the voltage charged in the charge capacitor becomes small, and the peak value of the pulse voltage of the collector pulse becomes small. In this way, the high output voltage is stabilized by controlling the ON period of the second switch element, that is, the OFF timing in accordance with the drop amount of the high output voltage.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic circuit of a high voltage generating circuit according to the present invention, and FIG. 2 shows a circuit configuration of a first embodiment of the high voltage generating circuit according to the present invention which is a more specific form of this basic circuit. It is shown. In FIG. 2, one end side of the low-voltage coil 12 of the flyback transformer 11 (the winding start side in this figure)
A transistor 13 as a first switch element is connected in series with the transistor 13, and a damper diode 14 and a resonance capacitor 15 are connected in parallel with the transistor 13. The emitter of the transistor 13 is connected to the ground (ground line in this figure). A horizontal drive signal synchronized with a horizontal output circuit (not shown) as shown in FIG. 4A is applied to the base of the transistor 13 from the horizontal drive circuit 16.

A MOS functioning as a second switch element is provided on the other end side (winding end side in this figure) of the low voltage coil 12.
The drain side of the FET 17 is connected. And M
The drive power source 18 is connected to the source side of the OSFET 17. A diode 20 and a charge capacitor 21 are connected in parallel between the drain and source of the MOS FET 17, respectively. This diode 20 is a MOS FET
17 may be connected externally, but it is a MOS FET
Since 17 has a built-in diode as an equivalent circuit from the beginning, the built-in diode may be used without externally mounting the diode 20. A capacitor 22 having a capacity much larger than that of the charge capacitor 21 is connected between the source of the MOS FET 17 and the ground line.

The high voltage end of the high voltage coil 24 of the flyback transformer 11 is connected to the anode of a cathode ray tube (not shown) via a high voltage rectifying diode 25. A bleeder resistor 26 is connected to the high voltage end side of the high voltage coil 24, and the high voltage output voltage is detected through the bleeder resistor 26. In this embodiment, the drive pulse signal of the MOS FET 17 is generated by using the detection signal of the high voltage output voltage and the horizontal drive signal of the horizontal drive circuit 16.

The circuit that produces this drive pulse signal is an inverter circuit 27, an integrating circuit 28, a comparator 30, and
It has a buffer amplifier 31, an error amplifier 32, a drive amplifier circuit 33, and a drive transformer 34. The inverter circuit 27 inverts the horizontal drive signal shown in FIG. 3B as shown in FIG. Integrator circuit
Reference numeral 28 integrates the output of the inverter circuit 27 and adds the signal having the integrated waveform shown in FIG. 3D to the negative terminal of the comparator 30 with an inverter.

On the other hand, the buffer amplifier 31 amplifies the detection signal of the high voltage output voltage and applies it to the error amplifier 32. The error amplifier 32 compares the reference voltage of the constant voltage power supply 35 with the output of the buffer amplifier 31, and when the high voltage output voltage drops with time as shown in FIG. 3A, for example, FIG. As indicated by the broken line, an error amplifier signal that increases as the amount of drop in the high voltage output voltage increases is applied to the positive terminal of the comparator 30.

The comparator 30 compares the integrated output applied from the integrating circuit 28 with the error amplifier signal applied from the error amplifier 32, and rises at the rising edge of the integrated waveform as shown in (d) and (e) of FIG. , Output the pulse drive signal that falls at the intersection of the integrated waveform and the error amplifier signal. That is, the comparator 30 produces a pulse drive signal having a narrow pulse width as the amount of drop of the high voltage output voltage increases, and adds this to the drive amplifier circuit 33.

The drive amplifier circuit 33 amplifies the pulse drive signal and applies it to the coil 36 on the primary side of the drive transformer 34. As a result, the coil 37 on the secondary side of the drive transformer 34 is connected to the gate of the MOS FET 17 as shown in FIG. (B) of the drive pulse signal obtained by amplifying the pulse drive signal shown in FIG. 4, that is, the pulse width becomes narrower as the drop amount of the high voltage output voltage becomes larger, and becomes wider as the drop amount of the high voltage output voltage becomes smaller. The drive pulse signal shown in) is M
It is added to OS FET17.

The first embodiment is configured as described above. Next, the stabilizing operation of the high voltage output voltage will be described based on the circuit of FIG. 2 and the time chart of FIG. First, since the MOS FET 17 is off when the transistor 13 is turned on in the state where the charge is not stored in the charge capacitor 21, the drive power source 18 passes through the diode 20 in the forward direction, and further the low voltage coil 12 causes the transistor 13 to pass. Through which the collector current i _c of the transistor 13 flows to the ground line. At this time, the voltage of the driving power source 18 E _B, the low pressure coil
If the inductance of 12 is L ₁ , then i _c is E _B / L ₁
It increases with a linear slope determined by.

When the transistor 13 is turned off in this state, the current energy stored in the inductance L ₁ of the low voltage coil 12 causes the resonance capacitor to move from the low voltage coil 12.
A current flows into 15 and a collector pulse voltage as shown in FIG. 4 (c) is generated. When the MOS FET 17 is turned on while the transistor 13 is off and a forward current is flowing from the drive power supply 18 through the diode 20, the current supplied from the drive power supply 18 passes through the MOS FET 17 and the diode 20 and is low voltage. The current energy flowing through the coil 12 and the resonance capacitor 15 to the ground line side and accumulated on the low voltage coil 12 side is continuously accumulated on the resonance capacitor 15, but the current energy on the low voltage coil 12 side gradually decreases and t ₁ reaches 0. At this time, the collector pulse voltage reaches a peak.

When all the current energy of the low voltage coil 12 is transferred to the resonance capacitor 15 side, the voltage energy stored in the resonance capacitor 15 causes the resonance capacitor 15, low voltage coil 12 and MOS FET 17 to be sequentially driven from the ground line. Reverse current flows through the power supply 18. When the resonance of the inductance L ₁ of the low voltage coil 12 and the resonance capacitor 15 progresses and the collector voltage becomes 0 V or less at t ₂ , the damper diode 14 is turned on and passes from the damper diode 14 through the low voltage coil 12 to the MOS FET 17. Drive power
Reverse current up to 18 flows. Thus, the resonant capacitor
From 15 or from damper diode 14 to MOS F
If the MOS FET 17 is turned off during the period in which the reverse current flows through the ET 17 to the drive power supply 18, the reverse current flows into the charge capacitor 21 and the charge capacitor
The voltage V _C across 21 starts to rise at a gentle slope as shown in (f) of FIG. 4 according to the series resonance waveform due to the capacitance of the charge capacitor 21 and the inductance of the low-voltage coil 12. When this charge voltage V _C rises, the voltage V _A of the output side of the MOS FET 17 with respect to the ground line, that is, the voltage A at the end of the winding of the low voltage coil 12 at the end A of the drive power source 18 is as shown in FIG. 4 (f). It becomes a voltage obtained by adding the charge voltage V _C to the voltage E _B. That is, V _A = E
_B + V _C , and the charge voltage V _C is generated, so that the voltage E _B of the driving power supply rises by V _C , that is, the same state as the voltage of the A portion of the low voltage coil 12 rises by V _C , and the low voltage The reverse current from the coil 12 through the charge capacitor 21 to the driving power supply 18 sharply decreases.

When the reverse current flows from the damper diode 14 side, the transistor 13 is turned on, and when the reverse current decreases and becomes 0 at t ₃ , the charge voltage V _C of the charge capacitor 21 reaches a peak. And the drive power supply 18
Voltage V _A that is the sum of the charge voltage V _C and the charge voltage V _C
Is applied to the low voltage coil 12, the collector current gradually starts to flow in the transistor 13, and at the same time, the charge voltage V _C starts to decrease. Then, when the charge voltage decreases to 0, the operation state returns to the initial one, and the above operation is repeated.

According to this embodiment, the pulse width of the drive pulse signal applied to the gate of the MOS FET 17 is controlled to become narrower as the drop amount of the high voltage output voltage becomes larger. FET
Since the ON period of 17 becomes shorter, the reverse current flowing from the low voltage coil 12 side to the drive power supply 18 side is correspondingly increased by the charge capacitor.
The time for passing through 21 becomes long, and accordingly, the charge voltage V _C of the charge capacitor 21 becomes large, and the low voltage coil 12
Since the voltage V _A applied to the A portion of the above becomes large, when the current next flows to the transistor 13 side, the peak value of the collector current i _c becomes large and the peak value of the collector voltage becomes high. That is, the peak value of the collector pulse voltage increases as the drop amount of the high voltage output voltage increases, and the high voltage output voltage is stabilized.

Further, in the MOS FET 17, when the forward current flows through the diode 20, that is, as at t ₅ in FIG. 4F, the current and voltage between the drain and source of the MOS FET 17 are zero. Since it turns on at the time, switching operation of zero current and zero voltage is achieved,
Similarly, the MOS FET 17 is a MOS from the low voltage coil 12 side.
Since it is turned off when a reverse current flows through the FET 17 to the drive power supply 18 side, as shown by t _{4 in} FIG.
The switching operation can be performed in a state where the drain-source voltage of the OS FET 17 is zero, and thus, the switching operation can be performed efficiently with almost no power loss during the switching operation.

Further, in this embodiment, as described above, the MO
The peak value of the collector pulse is controlled by controlling the ON period of the S FET 17, that is, the OFF timing. At this time, the large current does not flow back through the closed loop as in the conventional example, and this large current is controlled. Since there is no power loss due to the recirculation, the circuit efficiency can be significantly increased. The rising edge of the ON period of the MOS FET 17 coincides with the falling edge of the horizontal drive signal as shown in FIG. 3, but may be slightly delayed as shown in FIG. 4B using a delay element.

Further, since the time of turning off the MOS FET 17 can be arbitrarily set within the period in which the reverse current flows from the low voltage coil 12 side to the driving power supply 18 side, the control period of turning off the MOS FET 17 can be widened. (In this embodiment, t
₁ ~t can vary the timing of the off period of _3), therefore, a wide correction range can have a relative high output voltage, also correspond to any multi-scan type television receiver or a display device the current Is possible.

Moreover, since the OFF operation of the MOS FET 17 is a switching operation at zero voltage, the switching noise can be minimized, and the switching noise hardly affects the screen.

Further, when the high-voltage output voltage drops, the crest value of the collector pulse is controlled to be higher than that in the uncorrected state. Therefore, the voltage of the driving power supply and the step-up ratio of the flyback transformer are correspondingly increased. The size of the flyback transformer can be reduced, the load on the electronic components used in the circuit can be reduced, and the heat generation of the flyback transformer can be reduced.

FIG. 5 shows the circuit configuration of the second embodiment of the present invention. Also in this embodiment, similarly to the first embodiment, a drive pulse signal having a different pulse width is applied to the MOS FET 17 according to the amount of drop of the high voltage output voltage. The circuit for generating this drive pulse signal is the first one. It is omitted because it is similar to the embodiment. In this embodiment, MOS FE
A DC cut capacitor 38 having a capacity much larger than that of the charge capacitor 21, for example, 30 to 40 times larger than that of the charge capacitor 21, is connected in series on the drain side of T17, and the diode 20 and the charge capacitor are connected to the series circuit of the MOS FET 17 and the capacitor 38. 21 are connected in parallel, and MOS F
A diode 19 is connected in parallel with the ET17.

In the second embodiment, when a forward current flows from the driving power source 18 to the low voltage coil 12, the MOS FE is
When T17 is off, it flows from the drive power supply 18 side through the diode 20, and when MOS FET17 is on, it is from the MOS FET17 to the DC cut capacitor 38.
Flowing through. When the reverse current flows from the low-voltage coil 12 side to the drive power supply 18, it flows through the capacitor 38 and the MOS FET 17 when the MOS FET 17 is on, and flows through the charge capacitor 21 when the MOS FET 17 is off. At this time, the charge voltage V _C is stored in the charge capacitor 21 and the high voltage output voltage correction operation is performed as in the first embodiment. In the circuit of FIG. 5, a series circuit of a dummy yoke 40 and an S-shaped correction capacitor 41 is connected in parallel with the resonance capacitor 15, but this circuit reduces the load of the current flowing through the low voltage coil 12 and the flyback. It is provided in order to suppress heat generation of the transformer 11 and improve the regulation characteristic of the flyback transformer 11, and can be omitted if not particularly necessary.

FIG. 6 shows a third embodiment of the present invention. In the circuit of this embodiment as well, as in the first embodiment, a drive pulse signal having a pulse width corresponding to the amount of drop of the high voltage output voltage is applied to the gate of the MOS FET 17, and this drive pulse signal is produced. The circuit is the same as that of the first embodiment and is omitted. This embodiment is a MOS
The FET 17, the diode 42, and the charge capacitor 21 are connected in parallel, and a capacitor 38 having a capacity much larger than that of the charge capacitor 21, for example, a capacity of 30 to 40 times larger is connected in series to the parallel connection body. The diode 20 is connected in parallel to the series connection body of the charge capacitor 21 and the capacitor 38.

In this circuit, when a forward current flows from the drive power source 18 side to the low voltage coil 12 side, the MOS FET
Flows through diode 20 when 17 is off,
When MOS FET17 is on, MOS FE
Flow from T17 through the DC cut capacitor 38,
Also, the reverse current flowing from the low voltage coil 12 side to the drive power source 18 side is a capacitor when the MOS FET 17 is on.
Flow from 38 through MOS FET17, MOS
When the FET 17 is off, it flows through the route passing through the capacitor 38 and the charge capacitor 21, and at this time, the charge voltage is stored in the capacitor 38 and the charge capacitor 21 (actually, the capacitance of the capacitor 38 is the charge capacitor).
Since the charging voltage is much larger than that of 21, the charging voltage is hardly generated and a large charging voltage is generated on the side of the charging capacitor 21), and the high output voltage is stabilized by the same operation as in the first embodiment. is there. In this embodiment as well, as in the second embodiment, the dummy yoke 40 and the S
Although the character correction capacitor 41 is provided, it can be omitted if not particularly required.

FIG. 7 shows the circuit of the fourth embodiment of the present invention.
FIG. 8 shows the circuits of the fifth embodiment.
In these embodiments, the second switch element 8 composed of a MOS FET or the like is arranged between the low voltage coil 12 and the ground, and the parallel circuit of the charge capacitor 21, the diode 20 and the second switch element 8 is the second circuit. Similarly, a parallel circuit of the resonance capacitor 15, the damper diode 14, and the first switch element 7 formed of a transistor or the like is formed as a block 10, and the first circuit block 9 is formed. The second circuit block 10 is connected in series and is arranged between the low voltage coil 12 and the ground, and the other configurations are the same as those in the above-described respective embodiments. The fourth embodiment is the second
Is connected in series with the first circuit block 9 on the low voltage coil 12 side and the first circuit block 9 on the ground side.
The switch element 8 is driven by the drive transformer 34 as in the above embodiments.

Further, in the fifth embodiment, the first circuit block 9 is connected to the low-voltage coil 12 side and the second circuit block 10 is connected to the ground side to be connected in series. On / off driving is usually performed by a drive transformer.

In each of the fourth and fifth embodiments, the high voltage output voltage is stabilized by the same circuit operation as in the first to third embodiments.

FIG. 9 shows a sixth embodiment of the present invention. In this embodiment, an inductance element 40 is connected in parallel with the low voltage coil 12, and a parallel circuit of a transistor 13 and a damper diode 14 that functions as a first switch element is provided on the winding start end side of the low voltage coil 12. A first circuit block is connected in series, and a second circuit block including a parallel circuit of a transistor 43 functioning as a second switching element, a diode 20, and a charge capacitor 21 is connected in series to the first circuit block. And the resonance capacitor 15 is connected in parallel to the series circuit of the first circuit block and the second circuit block, and the other configuration is the same as that of the first embodiment.

In this embodiment, since the dummy yoke 40 as an inductance element is connected to the low voltage coil 12, while suppressing the leakage flux of the flyback transformer 11, the heat generation of the low voltage coil 12 of the flyback transformer 11 is suppressed. can do.

Also in this embodiment, when a reverse current flows from the ground side to the drive power supply 18 side, this reverse current flows through the path passing through the charge capacitor 21 and the path passing through the resonance capacitor 15, and therefore the resonance. Capacitor 15
Also acts to charge the electric charge of the reverse current, and functions as a part of the charge capacitor 21.

Further, when comparing the circuit of FIG. 8 with the circuit of FIG. 9, the capacitance of the resonance capacitor 15 of FIG.
₁ ′, the capacitance of the charge capacitor 21 is C ₂ ′, the capacitance of the resonance capacitor 15 in FIG. 9 is C ₁ , and the capacitance of the charge capacitor 21 is C ₂ , then C ₁ = C
It can be seen that when ₁ ′ and C ₁ + C ₂ = C ₂ ′, the circuit operations of both FIG. 8 and FIG. 9 are completely equal. This means that the circuit of FIG. 9 can perform the same circuit operation even when the connection order of the first circuit block and the second circuit block is changed, which is convenient in handling.

FIG. 10 shows a seventh embodiment of the present invention. In this embodiment, a transistor 13 and a diode 14 which function as a first switching element are connected in series as a first circuit block to the winding start side of a low voltage coil 12,
A second circuit block consisting of a parallel circuit of a transistor 43 as a second switching element and a diode 20 is connected in series with the first circuit block, and a voltage doubler circuit 44 is provided on the high voltage side of the flyback transformer 11. The other structure is the same as that of the sixth embodiment.

In this embodiment, the first circuit block and the second circuit block
Resonant capacitor 15 in parallel with the series circuit of the circuit block
When the reverse current flows from the ground side to the drive power supply 18 side, the resonance capacitor 15 has a function as the charge capacitor 21 that charges the reverse current.

In this embodiment, the resonance capacitor 15 has an inductance of the low voltage coil 12 when a forward current flows from the drive power source 18 side to the ground side and when a reverse current flows from the ground side to the drive power source 18 side. And resonant capacitor
Resonance is caused by the capacitance of 15. At this time, the resonance frequency due to the forward current and the resonance frequency when the reverse current flows are the same.

FIG. 11 shows an eighth embodiment of the present invention. In this embodiment, a series circuit of a deflection yoke 41 functioning as an inductance element and an S-shaped capacitor 42 is connected in parallel with the first switch element 7, and other configurations are the same as those of the fourth switch shown in FIG. It is similar to the embodiment of.

In this way, by connecting the series circuit of the deflection yoke 41 and the S-shaped capacitor 42 in parallel with the first switch element 7, a circuit on the high voltage generation side and a circuit on the deflection side are integrated. Can be configured. In addition, by inserting an amorphous bead core on the connection line between the series circuit of the deflection yoke 41 and the S-shaped capacitor 42 and the first switch element 7, a slight amount of noise generated when the second switch element 8 is turned off. It almost completely prevents noise from being superimposed on the deflection current. A high frequency filter may be connected instead of the bead core. Such a configuration can be used in the circuits of FIGS. 7 and 8 as well.
In the circuit of 10, too, a circuit of the high voltage generating side and a circuit of the deflecting side are integrated into one by connecting a series circuit of a deflection yoke and an S-shaped capacitor in parallel to the first switch element 13 in the same manner. can do.

The present invention is not limited to the above-mentioned embodiments, and various embodiments can be adopted. For example, in each of the above embodiments, the first switch element is the transistor 13
And the second switch element is a MOS FET
Although it is composed of 17 and the transistor 43, the first switch element may be composed of a MOS FET, and these first and second switch elements should be composed of various switch elements other than this embodiment. You can

Although the diode 20 is connected in parallel with the second switch element, that is, the MOS FET 17, in each of the above embodiments, the diode 20 may be omitted.
In this case, the circuit needs to be changed by omitting the diode 20.

Further, the circuit for generating the drive pulse signal of the first switch element is not necessarily limited to the circuit of the embodiment, and the off timing of the second switch element increases as the amount of drop of the high voltage output voltage increases. A circuit other than that of this embodiment may be used as long as it is a circuit that can generate a signal that speeds up.

[0046]

According to the present invention, the off time of the second switch element is controlled during a period in which a reverse current flows from the low voltage coil side to the drive power source side by the resonance operation of the low voltage coil of the flyback transformer and the resonance capacitor. The ON period of the second switch element is controlled according to the amount of drop of the high voltage output voltage, thereby varying the period during which the reverse current flows through the charge capacitor to control the magnitude of the charge voltage and the peak value of the collector pulse. Since it is configured to stabilize the high voltage output voltage by adjusting, the large current does not flow in a closed loop when controlling the peak value of the collector pulse as in the conventional example. Power loss due to the return of current does not occur, and the circuit efficiency can be significantly increased.

Further, since the second switch element is turned off when the reverse current is flowing through the second switch element to the drive power source side, the zero voltage switch operation of the second switch element is achieved. Therefore, it is possible to suppress the power loss accompanying the switch operation, and the switch noise is hardly generated, so that the adverse effect of the switch noise on the screen can be minimized. Moreover, in the present invention, the OFF time of the second switch element can be arbitrarily set within the range of the period in which the reverse current flows from the low voltage coil side to the drive power source side, so that the correction range for the drop amount of the high voltage output voltage can be set. It is very wide, and can be applied to various current multi-scan type television receivers and display devices. Moreover, in the case of a type such as a single scan type television receiver or a display device which does not require much correction width of the high voltage output voltage drop, the off time of the second switch element is changed within the blanking period. In this case, it is possible to completely eliminate the adverse effect on the screen due to the switch noise.

Further, according to the present invention, when the high-voltage output voltage drops, the high-voltage output voltage is corrected in such a direction as to increase the peak value of the collector pulse as compared with the uncorrected state. Since the applied voltage on the primary side of the flyback transformer is increased, the voltage of the drive power supply and the step-up ratio of the flyback transformer can be reduced accordingly, and as a result, the heat generation of the flyback transformer can be reduced. At the same time, it is possible to reduce the load on the electronic components used in the circuit.

[Brief description of drawings]

FIG. 1 is a basic circuit diagram of a high voltage generating circuit according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of a high voltage generating circuit according to the present invention.

FIG. 3 is a time chart showing a waveform of each part of a circuit that produces a drive pulse signal to be applied to the second switch element in the example.

FIG. 4 is a time chart of a high voltage output voltage stabilizing operation in the embodiment.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 11 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a conventional high voltage generation circuit.

FIG. 13 is an explanatory diagram of a stabilizing operation of a high output voltage by a conventional high voltage generating circuit.

[Explanation of symbols]

 11 Flyback transformer 12 Low voltage coil 13 Transistor 14 Damper diode 15 Resonance capacitor 17 MOS FET 18 Drive power supply 20 Diode 21 Charge capacitor

Claims (4)

[Claims] 1. A high voltage in which one end of a low voltage coil of a flyback transformer is connected to the ground side and the other end is connected to a drive power source side, and the low voltage coil is connected to a first switch element and a resonance capacitor. In the generation circuit, a second switch element is provided on a path from the drive power source through the low voltage coil to the ground, and a charge charged by a reverse current flowing from the low voltage coil side to the drive power source during an off period of the second switch element. A high-voltage generation circuit, which is provided with a capacitor. 2. The high voltage generating circuit according to claim 1, wherein a part or all of the charge capacitor charged by the reverse current is also used as the resonance capacitor connected to the first switch element. 3. The high voltage generating circuit according to claim 1, wherein an inductance element is connected in parallel with the low voltage coil of the flyback transformer. 4. The high voltage generating circuit according to claim 1, wherein a series circuit of a deflection yoke as an inductance element and a capacitor is connected in parallel with the first switch element.