JPH0529951A - Re-sync pattern generating method and coding circuit device using the same - Google Patents

Abstract

PURPOSE:To realize the simple method generating a code string not in compliance with a (2, 7) RLL coding rule and the device using the method. CONSTITUTION:As an input of a coding circuit 6 coding a coded data DT based on the (2, 7) RLL coding rule, a prescribed data byte, '62' in hexadecimal notation as a re-SYNC byte is generated by a re-SYNC byte generating circuit 2 at an interval of a predetermined data byte number, the data is inserted to the coding data DT to make it proper for the collection and start of data bit sequence before and after re-SYNC period. Moreover, whether or not a data in a prescribed bit number added to an output of the coding circuit 6 is delayed is discriminated by a delay timing circuit 7 and inputted to a flip-flop 10 acting like a delay circuit in a proper timing. When the signal is not delayed, an output data from the coding circuit 6 is directly outputted from a delay/ bypass changeover gate circuit 8. Thus, the re-SYNC pattern not in existence in the (2, 7) RLL coding rule is generated and coding is implemented by using the pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data encoding circuit and a method thereof, and particularly to a (2,7) RLL (Ru (Ru) suitable for recording on a magneto-optical recording medium, for example.
n Length Limitation) An encoding circuit device for inserting and encoding a code pattern having a sequence outside the (2,7) RLL code encoding rule into a code string for encoding data according to the code encoding rule, and its encoding The present invention relates to a method of generating a resync pattern.

[0002]

2. Description of the Related Art When recording data on a recording medium such as an optical storage medium, a magnetic storage medium, or a magneto-optical recording medium, or when performing modulation in communication, the conditions of the modulation method are as follows. The inversion interval is long, the read signal does not contain DC components and low-frequency components, and there is little error propagation. In order to satisfy such a condition to some extent, it is necessary to generate a code word having an optimum combination of bits according to the bit pattern of the data word. In this case, instead of the "fixed word length" in which the ratio of the code word length and the data word length is constant, the "variable word length code" in which the bit length of the code word changes depending on the bit pattern (bit sequence) of the data word May be. As one of such variable length encoding methods, (2,
7) The RLL coding method is known, and the coding method is disclosed in, for example, Japanese Patent Application Laid-Open No. 50-142131.

When the code is read from a storage medium recorded with a code modulated with a variable word length, if the variable frequency generation circuit (VFO) used as a timing clock in the pulse discrimination circuit is out of synchronization, the code is detected. Sometimes the bit length is lost or changed, and the rule of word length change is lost, and bit decoding fails for a long time. In the (2,7) RLL code, a code bit error of 1 bit is limited to a data bit error of 4 bits after decoding, but if the VFO is out of synchronization, the decoded data bits are lost or increased, and decoding is performed sequentially. The data byte is divided into a certain number of bits and recognized at the boundary of the "byte", and the error propagates thereafter. In order to keep this error propagation within a certain range, a "resynchronization (resync)" section is provided for a certain data byte, and the error propagation of the data bit due to the code bit error before the resync section is terminated within the resync section. ，
Also, if the first data bit after the end of the resync section is the first bit of 1 byte (8 bits), the error propagation of the code bit before the resync section and the above-mentioned byte boundary error can be stopped in the "resync" section. It has been known.

Specifically, when encoding a data word,
A resync section is provided for each constant of the data byte, and a special code bit string (resync pattern) that does not exist in the coding rule is inserted at a position corresponding to the resync section of the coded code bit string. Since this special code bit string does not exist in the encoding rule, it can be clearly separated from the bit string that encodes the data. Therefore, the resync interval can be specified by monitoring and detecting this special code bit string during decoding. You can However,
Since the (2,7) RLL code is a variable word length code,
The boundary between the data byte and the resync byte at the time of encoding does not always become the boundary of the encoding bit string, and the encoding circuit for performing the encoding process described above is such that the input is preceded by 2 data bits and the code bit is Since it is output, the encoding cannot be terminated only by the data bytes themselves.

The leading bit sequence of the resync byte for termination of encoding is, for example, "3.5" shown in Table 1.
Inch magneto-optical recording medium standardization committee (ISO / IEC
JTC1 / SC23 / WG2) DP10091, PA
It is shown in "Termination of (2,7) RLL code by resync section" described in the item "RLL (2,7) close of RT4". Thus, NRZ (Non Return
to Zero) When the constant binary data "011" is added to any sequence (code string) of the remaining bits and the conversion rule shown in Table 2 is applied, the following result is obtained. (A) NRZ When there are no remaining bits, "0"
11 ", (b)" 0011 "in the case of" 0 ", (c)
In the case of “1”, “10” and “11”, in the case of (d) “00”, “000” and “11”, in the case of (f) “01”, “010” and “11”, (g ) In the case of "001", "0"
010 "and" 11 ". As described above, it is known that the encoding can always be terminated at the boundary between "011" and the next data bit in the resync byte.

Further, at the time of decoding, the code bit string corresponding to the head bit sequence of the data byte following the resync byte is decoded by the decoding rule together with the preceding 4 code bits, but the head bit sequence of the data byte is always the data byte. It must be determined only by its own code bit sequence (column), and the preceding 4 code bits use "0100" shown in Table 1. Furthermore, in encoding the data byte following the resync byte, in order to make the leading bit sequence of the data byte start from the beginning of one of the "data bit conversion table" (see Table 2) of the encoding rule, The two data bits that must be input prior to the encoding circuit that performs the encoding process must be the data bits that can terminate the encoding by themselves and, when encoded, have a code bit of "0100". I have to. On the other hand, the code bit sequence corresponding to the resync byte is a special sequence that has the above function at the time of decoding and does not exist in the coding rule when observing the entire code bit sequence. It is required that the “resync byte” can be specified by detecting it.

"ISO / IEC JTC1 / SC23 /
WG2 ”DP10091, PART4 RLL (2,
7) "RLL (2,
7) close by RESYNC Field
"d" is 16-bit "0010000000100100" as the special code bit sequence described above.
It is shown.

As described above, in the encoding process of the above-described encoding process, the resync is performed in the encoding process of the data byte string in which the resync byte, which is a code that is out of the (2,7) RLL code encoding rule, is inserted. A circuit for inserting the coding end bit sequence and the coding start bit sequence in the section into the data byte string and coding
A circuit for generating a resync code bit sequence (resync pattern) that does not exist in the coding rule and a switching circuit for inserting the resync pattern into the output signal of the coding circuit are required. In addition to the above-described coding method, there is a method of coding the coding rules into a table, constantly monitoring the data bit sequence to be coded, and referring to the code string suitable for the data bit sequence from the table. However, since this encoding method is not directly related to the present invention, its detailed description is omitted.

[0009]

Regarding the insertion of the resync byte, the generation of the resync pattern, and the insertion of the resync pattern described above, the leading sequence "011" of the resync byte for ending the coding of the data bit sequence before the resync byte is "011". Pattern generation circuit and insertion circuit, a circuit that initializes a coding circuit for determining a code bit sequence corresponding to a data bit following a resync byte only by the bit sequence of the data bit itself, a circuit that generates a resync pattern, Also, a circuit for inserting the resync pattern into the encoded code bit string must be provided, and providing these circuits individually makes the circuit added to the above-mentioned encoding circuit considerably complicated, and Problems such as obstructing the simplification of the characteristic circuit configuration And to cause. Therefore, it is an object of the present invention to provide a method capable of generating a resync pattern applied as an input to the above-mentioned coding circuit by a simple method, and a coding circuit device using the resync pattern generating method.

[0010]

[Means for Solving the Problems]
In order to achieve the above object, the resync pattern generation method of the present invention uses a resync pattern every predetermined number of data bytes as an input of a coding circuit that codes an input signal based on a predetermined RLL code coding rule. A predetermined data byte is inserted as a constant byte to optimize the end and start of the data bit sequence before and after the resync section, and whether or not to delay the predetermined bit data added to the output of the encoding circuit at an appropriate timing. Then, a resync pattern that does not exist in the above coding rule is generated. In addition, a predetermined RLL to which this resync pattern generation method is applied
The coding circuit device for inserting and coding a resync pattern, which is a code string deviating from the RLL code coding rule, into a code string generated by coding data according to the code coding rule is the above-mentioned predetermined RLL code coding. An encoding circuit that encodes an input signal according to a rule, a means that generates a resync byte of a code string that is out of the RLL code encoding rule, and the encoded input signal and the resync byte are switched at a predetermined timing. A signal switching means for outputting to the encoding circuit; a means for delaying the output data from the encoding circuit for a predetermined time; and a delay for applying the output data from the encoding circuit to the delay means at a predetermined timing, Signal detour switching means for bypassing the delay means at another timing. More specifically, according to the resync pattern generation method of the present invention, a code string obtained by encoding a coded binary data bit string according to a (2,7) RLL code coding rule is added to a (2,7) R code string.
16-bit binary resync pattern "001000000001" that is a code string that is out of the LL encoding rule
00100 "is inserted, and a special" 62 "is displayed in hexadecimal not depending on the bit sequence of the coded binary data bit string immediately before the resync pattern is inserted into the coded binary data bit string. The step of inserting data, and after the insertion of the special data, encoding is performed in accordance with the (2,7) RLL code encoding rule, and the inserted hexadecimal display data "62".
Is also encoded, and a part of the resync pattern "00100" from the beginning of the resync pattern
At the time when the data is encoded up to 0000 "and output, the output code string is delayed by 1 bit, and the encoded data is output, the 2-bit encoded data" 10 "following the partial resync pattern" 001000000 ". Is converted to “01” and a step of generating output data without delaying the remaining remaining code string “00100” by bypassing the delay after this delay.

[0011]

As an input of the above-mentioned encoding circuit, a constant byte code, for example, a data byte 62, is provided as a resync byte at every predetermined number of data bytes.
By inserting _(H) ((H) indicates hexadecimal notation (hex)), the end and start of the data bit sequence before and after the resync section is optimized, and the 1 bit added to the output of the encoding circuit described above. The resync pattern which does not exist in the coding rule is generated by appropriately timing whether or not the output signal is guided to the delay circuit, and the resync pattern is used for coding. Therefore, originally, the code string “0010000001000100” obtained by encoding the hexadecimal display data “62” is converted into the above (2
7) "0010" that does not exist in the RLL code encoding rule
The conversion to a resync pattern of "000000100100" can be realized by a simple method, and by using this resync pattern generating method, the encoding circuit device can be realized with a simple circuit configuration.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a resync pattern generation circuit and a resync pattern generation method of the present invention, a case where binary 16-bit data is stored in a magneto-optical storage medium will be described as an example. FIG. 1 is a configuration diagram of a resync pattern generation circuit according to an embodiment of the present invention, and FIG. 2 is a signal waveform diagram showing operation timing of the resync pattern generation circuit of FIG. The resync pattern generating circuit of the embodiment of the present invention comprises a resync timing circuit 1, a resync byte generating circuit 2, a clock generating circuit 3, a data / resync switching gate circuit 4, an AND gate 5, (2,7) RLL code encoding circuit. 6, the delay timing circuit 7, the delay / detour switching gate circuit 8, the inverter 9, the delay type flip-flop (DFF) 10, the inverter 55, and the inverter 56 are connected as shown. Since the resync pattern is input to the (2,7) RLL code coding circuit 6 serving as the coding circuit, the resync byte generating circuit 2 serves as the resync pattern generating circuit.
A resync timing circuit 1, a clock generation circuit 3, a data / resync switching gate circuit 4 are provided, and further,
In order to perform selective delay, delay timing circuit 7, delay /
Detour switching gate circuit 8 and delay type flip-flop 10
Circuits such as are provided.

The data DT shown in FIG. 1 is the data to be encoded, and the data transfer clock DTRFCK is sent to an external data transfer shift register (not shown), synchronizing with the rising edge of this data transfer clock DTRFCK. , The encoded data DT as shown in FIG.
Are obtained in series in time.

The resync timing circuit 1 is a circuit that counts the rising edges of the clock CK output from the clock generation circuit 3, and counts the number of bits or the number of bytes of the encoded data DT in response to this clock CK, and (2 , 7)
When the count value, which is the value to insert the resync byte RSBY with the code = 62 _(H) that deviates from the RLL code encoding rule, is reached, the resync timing signal RSTM is turned on for 8 bits (1 byte) (“high”). "level)
To After that, this operation is repeated for every fixed byte into which the resync byte RSBY should be inserted. The resync byte generating circuit 2 synchronizes with the rising edge of the clock CK while the resync timing signal RSTM is on, and the code that is out of the above (2,7) RLL code encoding rule =
It is a circuit for outputting the resync byte RSBY of 62 _(H) ("01100010" in binary display). (2,
7) Since the RLL code encoding circuit 6 itself is outside the scope of the direct object of the present invention, its details are omitted and only its block diagram and its function are described. (2,7) R
The LL code encoding circuit 6 uses the encoded input data DTIN
Is synchronized with the inverted clock CKI obtained by inverting the clock CK from the clock generation circuit 3 by the inverter 56 (2,
7) Converted to RLL code and encoded output data CDOU
Output as T.

The resync timing circuit 1 outputs a resync timing signal RSTM for switching the input to the (2,7) RLL code encoding circuit 6 for each constant byte from the encoded data DT to the resync byte RSBY.
It is sent to the data / resync switching gate circuit 4. data/
The resync switching gate circuit 4 includes an inverter 41 and an AND
It is composed of gates 42 and 43 and an OR gate 44. Then, when the resync timing signal RSTM is on, the AND gate 43 is energized and the resync byte RSBY from the resync byte generation circuit 2 is applied to the OR gate 44.
To the (2,7) RLL code encoding circuit 6. On the other hand, when the resync timing signal RSTM is off, the resync timing signal RSSM is output to the inverter 41.
Then, the AND gate 42 is activated to output the encoded data DT to the (2,7) RLL code encoding circuit 6 via the OR gate 44.

The resync byte RSBY serves as a timing signal for turning off the data transfer clock DTRFCK in order to stop the data transfer. The 2/7 code clock 2 / 7CK output from the clock generation circuit 3 is a reference clock for recognizing the encoded output data CDOUT. The delay timing circuit 7 has a (2,7) RLL code “001000000” for the resync byte “62 _(H) ” appearing in the encoded output data CDOUT when the resync timing signal RSTM is in the ON state.
A bit sequence of a part of "1000100" is sent to the delay flip-flop 10, a delay timing signal DLTM for changing to the (2,7) RLL code "0010000000100100" is generated, and sent to the delay / detour switching gate circuit 8.

The delay / detour switching gate circuit 8 comprises an inverter 81, AND gates 82 and 83, and an OR gate 84. This delay / detour switching gate circuit 8
Is the delay timing signal DL from the delay timing circuit 7.
When TM is on, the AND gate 83 is energized to output the encoded data CDOUT from the (2,7) RLL code encoding circuit 6 to the delay flip-flop 10 and the 2/7 clock 2 / 7CK. The result delayed by is input and output via the OR gate 84. On the other hand, when the delay timing signal DLTM from the delay timing circuit 7 is in the off state, the delay / detour switching gate circuit 8 inverts it by the inverter 81 to activate the AND gate 82 (2.
7) Coded data CD from the RLL code coding circuit 6
OUT is directly output via the OR gate 84.

In the present invention, as described above, the clock CK for synchronously controlling the entire circuit, the inverted clock CKI inverted by the inverter 56, and the clock generation circuit for generating the 2/7 code clock 2 / 7CK. With the configuration including 3, the data bit sequence before and after the resync byte and the encoding including the resync byte are performed (2, 7).
While following the RLL code encoding rules, (2,7)
The generation of a resync pattern that does not exist in the RLL code coding rule and the insertion into the (2,7) RLL code are realized by a simpler circuit and method. The operation of the resync pattern generation circuit of FIG. 1 will be described below with reference to FIG.

When the resync timing signal RSTM is turned on at time t1 in FIG. 2, the AND gate 5 is closed, so that the data transfer clock DTRFCK is held at "0 (low level)" and the transfer of the encoded data DT is stopped. . When the resync timing signal RSTM turns on, the AND gate 4 in the data / resync switching gate circuit 4
2 is closed (energized), the AND gate 43 is opened (energized), the encoded data DT is disconnected from the input path to the encoding circuit, and the resync byte RSBY from the resync byte generation circuit 2 becomes (2 , 7) is connected to the input of the RLL code encoding circuit 6. Resync timing signal R
The encoded input data DTIN for the (2,7) RLL code encoding circuit 6 output from the data / resync switching gate circuit 4 during the period when the STM is on, from the time t1 to the time t17, is encoded at the above timing. Data D
The signal has the resync byte RSBY inserted in T.

The encoded output data CDOUT from the time point t5 to the time point t21 in FIG. 2 is "00100" in which the code string "62 _(H) " which is the resync byte RSBY is coded.
00001000100 ". Encoded input data D
Switching (insertion) to the resync byte RSBY for TIN is performed from the time point t1 to the time point t17, whereas the resync byte R in the encoded output data CDOUT is changed.
The code string obtained by coding SBY is from time t5 to time t21, and a 2-bit delay occurs in the coded data DT.

The above data "0010000001000"
100 "is the resync pattern" 00100000 ".
In order to convert the data into “000100100”, it is necessary to change the data “10” from the time point t14 to the time point t16 to the data “01”. Therefore, the delay timing circuit 7 has the time point t when the resync timing signal RSTM turns on.
Count the number of rising edges of the inverted clock CKI from 1,
At time t14, the delay timing signal DLTM is turned on, the AND gate 82 in the delay / detour switching gate circuit 8 is closed, the AND gate 83 is opened, and the encoded output data CD
OUT is input to the D flip-flop 10 that functions as a delay circuit that delays 2/7 clock by 2/7 CK. Then, at time t16, the delay timing signal DLTM
Is turned off to open the AND gate 82 and
The D gate 83 is closed to bypass the flip-flop 10 and the encoded output data CDOUT is output as the code bit CB through the OR gate 84.

The flip-flop 10 outputs "1" of the encoded output data CDOUT from the time point t14 to the time point t15,
At the rising edge of the clock 2 / 7CK at time t15,
The encoded output data CD from time t15 to time t16
"0" of OUT is latched at the rising edge of clock 2 / 7CK at time t16, and delayed output data DLOUT
To occur. The delayed output data DLOUT and the detoured encoded output data CDOUT are added by the OR gate 84 to encode the encoded data DT into (2,7) RLL.
The resync pattern "001000000001" is added to the code.
The code bit CB in which "00100" is inserted is obtained. In this way, the resync pattern can be generated by a simple method.

In the above embodiment, an example in which a resync pattern is generated in the coding circuit when 16-bit data is stored in the magneto-optical storage medium has been described. However, the coding circuit device and the resync pattern generating method of the present invention are as described above. The present invention is not limited to the embodiment, and can be applied to other applications such as data modulation of other number of bits and optical storage devices and communication systems.

[0024]

As described above, in the resync pattern generation method of the present invention, for example, in the case of 16-bit data, a constant hexadecimal data byte "62 _(H) " is inserted as the resync byte. , It is said that it is possible to realize the termination and start of encoding before and after the resync byte, and the generation and insertion of the resync pattern in a simpler method compared to the conventional method by introducing two code bits to the delay circuit. Produce an effect. Further, the encoding circuit device of the present invention using the above resync pattern generating method has a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an encoding circuit device to which a resync pattern generating method according to an embodiment of the present invention is applied.

FIG. 2 is a timing diagram illustrating an operation of the encoding circuit device shown in FIG. 1 and a processing method of a resync pattern generating method.

[Explanation of symbols]

1 ... Resync timing circuit, 2 ... Resync byte generation circuit, 3 ... Clock generation circuit, 4 ... Data / resync switching gate circuit, 5 ... AND gate, 6 ...
(2,7) RLL code encoding circuit, 7 ... Delay timing circuit, 8 ... Delay / detour switching gate circuit, 9 ...
Inverter, delay flip-flop.

Claims (3)

[Claims] 1. A predetermined data byte is inserted as a resync byte at every predetermined number of data bytes as an input of a coding circuit for coding an input signal based on a predetermined RLL code coding rule. By optimizing the end and start of the data bit sequence before and after the resync section, and determining whether or not to delay the predetermined bit data added to the output of the encoding circuit at an appropriate timing, and the resync pattern that does not exist in the encoding rule. A method for generating a resync pattern, which comprises: 2. An encoding circuit device for inserting a resync pattern, which is a code string deviating from the RLL code coding rule, into a code string generated by coding data according to a predetermined RLL code coding rule and coding the code string. A coding circuit for coding an input signal according to the predetermined RLL code coding rule, a means for generating a resync byte of a code string deviating from the RLL code coding rule, the coded input signal and the above A signal switching means for switching the resync byte to a predetermined timing and outputting it to the encoding circuit, a means for delaying the output data from the encoding circuit for a predetermined time, and a predetermined timing for the output data from the encoding circuit. Signal delay switching means for applying a delay to the delay means and delaying the delay means at another timing. That coding circuit device. 3. A code string obtained by coding a coded binary data bit string according to a (2,7) RLL coding rule, and a 16-bit code string that is a code string that is out of the (2,7) RLL coding rule. A method for generating a resync pattern for inserting a binary resync pattern "0010000000100100", which is displayed in hexadecimal not depending on the bit sequence of the code binary data bit string immediately before the resync pattern is inserted into the code binary data bit string. "6
2 "special data is inserted, and after the special data is inserted, encoding is performed according to the (2, 7) RLL code encoding rule, and the inserted hexadecimal display data" 62 "is also encoded. When the part of the resync pattern from the beginning to 9 bits of the resync pattern "001000000" is coded and output, the output code string is delayed by 1 bit and the encoded and output one The 2-bit encoded data "10" following the partial resync pattern "001000000" is converted to "01", and the delay is bypassed after this delay without delaying the remaining code string "00100". And a step of generating output data, which is originally a code string "0010000001000" obtained by encoding the hexadecimal display data "62". 100 "is converted into a resync pattern of" 0010000000100100 "which does not exist in the above (2,7) RLL code encoding rule.