JPH05299343A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor chip, and obtain a semiconductor device which has small series resistance to a forward direction current and is easily manufactured, by a method wherein the occupied area of semiconductor region of the opposite conductivity type to semiconductor of a conductivity type on the semiconductor chip surface is made small. CONSTITUTION:By deposition growth, on semiconductor 2 of a conductivity type, a crystal mismatch region 6 is formed directly or via an amorphous layer or a polycrystalline layer or a layer wherein the above layers mixedly exists, and a single-crystal semiconductor region 7 is formed so as to be in contact with the region 6. Next the crystal mismatch region 6 is turned into an opposite conductivity type semiconductor region by conductivity type conversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a semiconductor device (2) having a rectifying function, such as a Schottky barrier rectifying semiconductor device, has been improved in various characteristics and structures including forward characteristics and reverse characteristics. There is.

1 and 2 are cross-sectional structural views illustrating a conventional structure. 1 is a high concentration one conductivity type semiconductor (for example, N
+), 2 is a semiconductor of one conductivity type (for example, N-), 3 is a semiconductor region of opposite conductivity type (for example, P +), 4 is an electrode metal, A is an anode, and C is a cathode.

According to the present inventors, the angle θ formed by the closest distance W of the one conductivity type semiconductor 2 sandwiched between the pair of opposite conductivity type semiconductor regions 3, the depth D of the opposite conductivity type semiconductor region and the tangent line.
In relation to the relationship between and, by inventing Japanese Patent Application No. 3-115341, Japanese Patent Application No. 3-133737, Japanese Patent Application No. 3-133738 and the like, and satisfying those conditions, reverse leakage current,
In addition, it was proposed to obtain a semiconductor device having a low forward voltage drop, high speed, and low loss.

In the formation of the conventional structure, the one-conductivity-type semiconductor 2 previously provided on the high-concentration one-conductivity-type semiconductor 1 is
A means by a vapor phase diffusion method for forming a reverse conductivity type semiconductor region 3 to a predetermined depth by ordinary thermal diffusion using a diffusion source of impurities of a reverse conductivity type, for example, BN or BCl ₃ . Means by an ion implantation diffusion method for implanting B + ions into a predetermined portion of the one conductivity type semiconductor 2 and further forming a reverse conductivity type semiconductor region 3 to a predetermined depth by thermal diffusion. Moreover, as shown in FIG.
Means by the trench method in which a recess having a predetermined depth and width is provided in advance on the surface of the one-conductivity-type semiconductor 2 and shallow diffusion is performed along the inner wall and the bottom of the recess. Etc. These are all structures of the semiconductor device in which the opposite conductivity type semiconductor region 3 is formed on the surface of the one conductivity type semiconductor 2 which is a single crystal semiconductor substrate by impurity introduction means such as implantation and diffusion.

As described in the above-mentioned prior invention of the present inventors, the structurally preferable formation condition of the reverse conductivity type semiconductor region 3 is that the angle θ formed by the tangent line is about 90 degrees, and in the case of 3, (3 ) To make the depth D of 3 sufficiently deeper than the closest distance W of the sandwiched one conductivity type semiconductor 2.

However, when the above-mentioned preferable structural conditions are applied to the conventional structure in which the opposite conductivity type semiconductor region 3 is formed on the surface of the one conductivity type single crystal semiconductor substrate by the impurity introducing means, the structure is necessarily reversed. The width WP of the conductive type semiconductor region 3 is increased, and accordingly, the area of the semiconductor chip is increased, which is uneconomical. Further, in order to obtain a preferable structure having a depth D = 2 μm and WP = 2 μm or less in any formation means of the reverse conductivity type semiconductor region 3 of the conventional structure,
Ultra-precision microfabrication is required, which is difficult in manufacturing.

[0008]

A problem to be solved is to form a plurality of opposite conductivity type semiconductor regions on the surface of one conductivity type semiconductor, and to form an electrode across the surface of one conductivity type semiconductor and the opposite conductivity type semiconductor region. In a semiconductor device provided with a metal,
In the conventional structure in which the opposite conductivity type semiconductor region is formed on the surface of one conductivity type semiconductor made of a single crystal semiconductor substrate by the impurity introduction means, the area occupied by the opposite conductivity type semiconductor region on the semiconductor chip surface becomes large, and the semiconductor chip area is accordingly increased. This is a big point. In addition, high precision microfabrication technology is required,
It's troublesome.

[0009]

As in the case where a crystal mismatched region of a deposited growth layer and a single crystal semiconductor region are arranged adjacent to each other on a semiconductor of one conductivity type, the crystal mismatched region is amorphous or polycrystalline. , Or through a mixed layer thereof, or directly, deposited and grown on one conductivity type semiconductor, and at the same time, the single crystal semiconductor region is directly formed on one conductivity type semiconductor by epitaxial growth and provided. Further, the main feature is that the crystal mismatched region is made into a semiconductor region of opposite conductivity type by converting the conductivity type, and a means for depositing and growing the crystal mismatched region on the amorphous dielectric layer, a crystal mismatched region is provided. It is possible to select and use a means for providing a concave portion in the portion of the one conductivity type (4) semiconductor to be deposited and grown, and a means for forming the concave portion into a V-shaped groove. In addition, by combining the above-mentioned prior inventions of the present inventors,
(EN) A semiconductor device having a small reverse leakage current and a low forward voltage drop, a high speed, and a low loss can be realized economically and easily manufactured.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a sectional structural view showing an embodiment of the present invention, wherein the reference numerals of the respective parts are the same in all drawings and the same reference numerals represent the same parts. Further, FIG. 4 is a manufacturing process diagram illustrating the manufacturing of the structure of the present invention.

The structure of the present invention will be described below with reference to the manufacturing process chart of FIG. Regarding FIG. 4 (a). A silicon single crystal substrate in which a low concentration one conductivity type semiconductor 2 is provided on a high concentration one conductivity type semiconductor 1 is prepared, and a recess H having a depth of 4000 Å and a width of about 1 μm is formed on the surface of 2. Thereafter, a silicon oxide film having a thickness of about 2000 angstrom is formed only on the bottom of the recess H. The silicon oxide film constitutes the amorphous dielectric layer 5.

Regarding FIG. 4B. Then, an epitaxial growth layer containing one conductivity type impurity having a thickness of about 2 μm is formed by a conventional means over the recess H in which the amorphous dielectric layer 5 is formed and the one conductivity type semiconductor 2 other than the recess H. To do. In this case, since the dielectric layer 5 is an amorphous silicon oxide film, a single crystal does not grow on it, but a single conductivity type polycrystal grows. Here, the growing polycrystal is a kind of region in which the boundaries of crystal grains exist in a mismatched state, and is indicated by a crystal mismatching region 6. Further, the epitaxially grown layer on the surface of the one-conductivity type semiconductor 2 other than the recess H that grows at the same time forms the one-conductivity type single crystal semiconductor region 7.

When the pattern of the amorphous dielectric layer 5 is merely formed and grown without forming the concave portion H, the polycrystalline crystal mismatch region 6 has a thickness of about 2 μm. In the stack (5), it did not grow vertically and spread to a width of about 3 to 4 μm above the width of about 1 μm at the bottom, and there is a high possibility of pattern collapse at the top of the stack, and in terms of performance. Cause problems. When the recess H is formed, the single crystal semiconductor region 7 growing on the surface of the one conductivity type semiconductor 2 other than the recess H is formed.
In this case, since the crystal mismatching region 6 that grows from the recess always grows first, the lateral spread of the deposition upper portion of 6 is suppressed from both side surfaces by 7 and, as a result, the single conductivity type single crystal is grown. The boundary of the one conductivity type crystal mismatch region 6 adjacent to the crystal semiconductor region 7 can be formed substantially perpendicular to the substrate surface of the one conductivity type semiconductor 2. When the recess H is not formed, it is necessary to suppress the lateral spread by some means.

Regarding FIG. 4C. An oxide film is formed on the surface of the crystal mismatched region 6 and the single crystal semiconductor region 7 of the deposited growth layer, and after opening a window only on the surface of 6, the vapor phase diffusion method of BN or BCl ₃ is used to obtain 950 ° C. Boron diffusion is performed in an N2 gas atmosphere. Boron diffusion in the polycrystal layer of the crystal mismatch region 6 has a diffusion coefficient about 10 to 30 times larger than that in the monocrystal layer, and the diffusion coefficient from the top surface to the bottom portion of the polycrystal layer, that is, amorphous A high-concentration reverse-conductivity type semiconductor region (P +) having substantially the same concentration can be formed up to the surface of the high-quality dielectric layer 5 to change the conductivity type. In addition, a P + N junction can be formed in the single crystal layer by selecting the diffusion concentration and time and proceeding the boron diffusion beyond the boundary between the adjacent single crystal semiconductor regions 7. As described above, the opposite conductivity type semiconductor region having a width of about 1 μm and a depth of about 2 μm can be provided adjacent to the single crystal semiconductor region. After that, the oxide film on the upper portion is removed, and the electrode metal 4 such as Ti, Cr, Mo, Al or Pt is formed by vapor deposition or sputtering. At this time, if the surface concentration of the opposite conductivity type semiconductor region P + is set to a high concentration of 5 × 10 ¹⁹ atoms / cm 3 or more, ohmic contact between the electrode metals 4 occurs, and
When the boron diffusion is controlled to a concentration lower than 5 × 10 ¹⁸ atoms / cm 3, Schottky contact is made with the electrode metal. Further, the contact between the single crystal semiconductor region 7 which is one conductivity type semiconductor and the electrode metal 4 is also controlled by adjusting the surface concentration of the one conductivity type semiconductor N −.
It can be either Schottky contact or ohmic contact. In addition, Schottky contact with the electrode metal 4, (6)-
As described in the above-mentioned prior invention, a semiconductor device having various characteristics can be constructed by selecting and combining the mic contacts.

The structure of the present invention shown in FIG. 3 will be described below in comparison with the conventional structure. In the conventional structure shown in FIG. 1, the shortest distance DN between the bottom of the opposite conductivity type semiconductor region 3 and the high concentration one conductivity type semiconductor 1 is set to be larger than the depletion layer width WB at the break down voltage. Functionally required. However, in the structure of the present invention shown in FIG. 3, since the amorphous dielectric layer 5 such as SiO2 exists at the bottom of the reverse conductivity type semiconductor region of the crystal mismatch region 7, the one conductivity type semiconductor 2 is applied when a reverse voltage is applied.
The dielectric layer 5 having a smaller dielectric constant can be formed to have a thickness that shares most of the voltage. As a result, the depletion layer width extending beyond the dielectric layer 5 is much smaller than the depletion layer width at the P + N- junction of FIG. 1 or remains within the thickness of the dielectric layer 5. The degree of the shared voltage depends on the film quality of the dielectric layer 5,
It depends on the film thickness, and the thermal oxide film bears a voltage of about 70 Volt at a thickness of 1000 angstroms. Therefore, in the structure of the present invention, the depletion layer width WB at the time of break-down can be substantially reduced, whereby the shortest distance D
N can be small.

This means that, in the forward current flowing from the anode A to the cathode C, the series resistance can be reduced by the thinner the one-conductivity type semiconductor 2 having high resistance. Therefore, the forward characteristic can be greatly improved.

Further, in the low breakdown voltage semiconductor device capable of increasing the voltage sharing to the amorphous dielectric layer 5, the shortest distance DN of the one conductivity type semiconductor 2 immediately below 5 can be made extremely small.
It is also possible to make it substantially zero. FIG. 5 is a sectional structural view showing another embodiment of the structure of the present invention thus formed.

As another embodiment of the structure of the present invention shown in FIG. 3, the amorphous dielectric layer 5 may be replaced by a polycrystalline, amorphous, or a mixed formation layer thereof. The one-conductivity-type half (7) conductor 2 is provided with a recess of, for example, about 5000 angstroms, and silicon atoms are provided at the bottom of 10 ²⁰ atoms / atom.
When high-concentration ion implantation of cm3 or more or boron ion ion implantation with high energy of 50 KeV or more is carried out, a polycrystalline layer with disordered silicon periodicity, an amorphous layer, or a mixed formation layer thereof is formed. When a deposition growth layer containing one conductivity type impurity is formed on the formation layer as in FIG. 4B, the one conductivity type crystal mismatched region 6 made of polycrystal is formed. Otherwise, the structure of the present invention is configured in the same manner as described with reference to FIGS. 3 and 4. When the formation layer is replaced with the amorphous dielectric layer 5, the conductivity type can be converted over the formation layer and the crystal mismatch region 6 to form an opposite conductivity type semiconductor region.

Next, FIG. 6 shows a sectional structural view showing another embodiment of the present invention together with manufacturing process drawings. That is,
(A), (b) is a manufacturing-process figure, (c) is a cross-section figure. Regarding FIG. 6 (a). The one conductivity type semiconductor 2 is used as the (111) surface of the silicon substrate, and fine photo processing is performed.
Prepare a 0.7 μm wide photoresist window. CCl ₂ F
5mtorr gas pressure with only ₂ gases, substrate temperature 75 ° C,
A sharp V-shaped groove is formed as a magnetron ion etching (MIE) process at an RF output of 2 KW for 20 seconds.

Regarding FIG. 6B. After removing the photoresist by a usual method, crystalline silicon by an epitaxial growth layer containing a one conductivity type impurity is deposited on the surface of the one conductivity type semiconductor 2 including the V-shaped groove by a usual method. The grown silicon layer on the inner surface of the V-shaped groove grows from the two surfaces of the inner surface of the V-shaped groove reflecting each crystal phase, and the crystal growth associates near the center line of the V-shaped groove. The crystallinity such as the crystal lattice constant does not match on this bounded boundary, and a large difference causes distortion, and the crystal mismatched region 6 is formed. In this case, the width of the crystal mismatch region 6 can be about 0.1 to 0.5 μm in the epitaxially grown layer having a thickness of about 2 μm.

Regarding FIG. 6 (c). In the crystal mismatched region 6 formed in (b) and in the vicinity (8) crystalline silicon, the conductivity type is converted by boron diffusion, and the reverse conductivity is extremely narrow with the crystal mismatched region 6 at the center. A type semiconductor region (P +) is formed. Then, similarly to the other examples, Schottky contact or ohmic contact is formed by the electrode metal 4 to obtain the semiconductor device having the structure of the present invention.

In FIG. 6A, an amorphous dielectric layer 5 is provided on the inner surface of the V-shaped groove, or as described in paragraph 0018, high-concentration ion implantation of silicon atoms or high-energy ions of boron atoms. By providing a formation layer by implantation, or by a plasma damage layer when forming a V-shaped groove,
Through the silicon deposition step of FIG. 6B, one conductivity type polycrystalline region can be formed in the V-shaped groove inner surface region. In this case, the crystal mismatching region 6 is formed by the formed polycrystalline region including the grown crystal association portion generated near the center line of the V-shaped groove. As a result, the crystal mismatch region 6 having a narrow width can be surely formed, and the semiconductor chip area can be reduced.

Although only the rectifying semiconductor device is shown in each of the embodiments, a plurality of opposite conductivity type semiconductor regions are formed on the one conductivity type semiconductor surface, and the one conductivity type semiconductor surface and the opposite conductivity type semiconductor region surface are spread over. It is obvious that the present invention can be applied to any semiconductor device provided with an electrode metal. Other,
Any modification, addition, conversion or the like change is included in the scope of the present invention as long as the constituent requirements of the present invention are satisfied.

[0024]

As described above, the area occupied by the opposite conductivity type semiconductor region required on the surface of one conductivity type semiconductor is small, and therefore the area of the semiconductor chip is reduced, and the series resistance is small. It is possible to easily obtain a semiconductor device having excellent directional characteristics, and it is possible to obtain a great industrial effect by using it in various devices such as power supply devices.

[Brief description of drawings]

 (9)

FIG. 1 is a sectional structural view of a conventional structure.

FIG. 2 is a sectional structural view of a conventional structure.

FIG. 3 is a sectional structural view showing an embodiment of the present invention.

FIG. 4 is a manufacturing process diagram showing the manufacturing example of FIG. 3;

FIG. 5 is a sectional structural view showing another embodiment of the present invention.

FIG. 6 is a manufacturing process diagram and a cross-sectional structure diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 High-concentration one conductivity type semiconductor 2 One conductivity type semiconductor 3 Reverse conductivity type semiconductor region 4 Electrode metal 5 Amorphous dielectric layer 6 Crystal mismatching region 7 Single crystal semiconductor region A Anode C Case H Recess D Depth of reverse conductivity type semiconductor region Minimum distance between bottom of DN 3 and 1 Closest distance of 2 sandwiched by W 3 Width of WP 3 θ Angle of tangent line of reverse conductivity type semiconductor region

Claims (4)

[Claims] 1. A semiconductor device in which a plurality of opposite conductivity type semiconductor regions are formed on a surface of one conductivity type semiconductor and an electrode metal is provided over the surface of the one conductivity type semiconductor surface and the surface of the opposite conductivity type semiconductor region. On the semiconductor, as the crystal mismatched region of the deposited growth layer and the single crystal semiconductor region are arranged adjacent to each other,
The crystal-mismatched region is formed by depositing and growing directly on one conductivity type semiconductor through an amorphous layer, a polycrystalline layer, or a mixed layer thereof, and at the same time, the single crystal semiconductor region is directly formed by one layer. A semiconductor device, wherein the semiconductor device is provided by being formed on a conductive type semiconductor by epitaxial growth, and the crystal mismatching region is made into a reverse conductive type semiconductor region by conductivity type conversion. 2. An amorphous dielectric layer is partially provided on a semiconductor of one conductivity type, a crystal mismatch region is formed on the amorphous dielectric layer, and an amorphous dielectric layer is formed. The semiconductor device according to claim 1, wherein a single crystal semiconductor region is formed in a non-existing portion. 3. The one-conductivity-type semiconductor is provided with a recess, a crystal mismatch region is formed on the recess, and a single crystal semiconductor region is formed on a portion other than the recess. 2 semiconductor devices. 4. A V-shaped groove is formed as a recess provided in one conductivity type semiconductor, and a crystal mismatch region is formed on a center line of the V-shaped groove.
4. The semiconductor device according to claim 1, wherein a single crystal semiconductor region is formed in the other region.