JPH05298135A - Processing system for cpu - Google Patents

Abstract

PURPOSE:To use a temporarily saved program again at the time of run-away by providing a history area to store the temporarily saved program for each block every time the processing of a working block is completed. CONSTITUTION:This system is provided with a register 2 to update the program for each block and to temporarily store it, program storage part 4A storing a basic program, and storage part 4 equipped with history areas 49 and 4, to successively store execution programs. In this case, after the arithmetic result or the values of program counter remaining in the respective registers of a CPU 1 are temporarily saved in the history areas 4B and 4C after the processing of the preceding working block is completed, they are read out to the register 2 again and used as the program of the next working block. After the lapse of prescribed time, the register 2 is reset. At the time of runaway, the register 2 is forcedly reset after the lapse of time as the destruction of the program counter, and data already stored in the history areas are read out to the register again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU processing system, and more particularly, to a CPU capable of self-recovering the runaway when the program runs out during execution of processing by a program registered in a register of the CPU. Regarding the processing method of.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 4, a CPU processing system of this type has a register 1 for temporarily storing a program.
2 and a CPU 11 having a processor 13 that performs processing for each work block according to the work procedure of the program, a storage unit 14 that externally stores the program and reads the program into a register 12, and a reset time for each end of the work block processing is monitored. It is composed of a watchdog timer 15 that is present. Next, the operation of the conventional example will be described with reference to the operation flow of FIGS.

FIG. 5A shows a normal operation flow without runaway,
(B) is a flow at the time of runaway. As a premise, the watchdog timer is 100 msec. In FIG. 5A, the work blocks a, b, and c have a processing time of 100 ms.
Divide so that it is within ec and execute the program. The timer starts counting down at the same time as the start of each work block. During normal operation, the value of the timer is reset after the end of each work block and is set to 100 msec again. If a runaway occurs during the execution of work block b, 100 ms is set.
Since the processing will not end within ec, the timer will be 10
Count 0 msec and time up. When the time is up, the watchdog timer will reset the CPU
CP that outputs an alarm signal to the terminal and receives it
U sets the IP register to 0. When the IP register becomes 0, the program execution is restarted from the beginning of the program. That is, assuming that the work block a is the head of the program, the process is executed from the work block a, and the watchdog timer also starts the countdown from 100 msec.

[0004]

Since the watchdog timer of the conventional CPU processing system does not particularly know whether or not a runaway is caused by a program error, even if the runaway work block is re-executed. It has the drawback that it cannot guarantee that it will not run away. In addition, since the program that executes each work block is not stored as a history each time, there is a drawback that it is not possible to determine whether or not the program is out of control due to a mistake in the program.

[0005]

According to the CPU processing method of the present invention, a program used each time the processing of a work block is completed is temporarily saved, and the saved program is read again for the next work block and temporarily saved. It has a means for storing and two history areas for storing the temporarily saved program for each work block.

[0006]

The present invention will be described below with reference to the drawings. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an operation flow of the present embodiment during normal operation, and FIG. 3 is an operation flow of the present embodiment during runaway. In the embodiment shown in FIG. 1, a CP having a register 2 for updating and temporarily storing a program for each work block, which will be described later, and a processor 13 similar to the conventional one.
U1 and a program storage unit 4A that stores a base program and a storage unit 4 that has history areas 4B and 4C that sequentially store the execution programs of the previous work blocks described later.

Next, the operation of this embodiment will be described with reference to FIGS. The flow of the normal operation procedure of FIG. 2 is as follows.

Step 21, the program of the previous work block is stored in the history area 1 from the register 2.

In step 22, a flag is set when registering in the history area 1.

Step 23: After the reset, the flag set up is confirmed, the program data stored from the history area 1 is returned to the register 2, and the processing of the work block a is executed by this program.

Step 24, the program that executed the work block a is written in the history area 2 from the register.

Step 25: The flag is set when registered in the history area 2.

Step 26: After checking the flag that has been reset, the program data stored from the history area 2 is returned to the register 2, and the processing of the work block b is executed by this program.

Thus, for each work block, after the previous work block processing is completed, the calculation result and the value of the program counter remaining in each register in the CPU are temporarily saved in the history area, and then read again in the register to read the next data. Use it as a work block program. The register is reset at each step after a predetermined time (for example, 100 ms) has elapsed.

Next, the operation flow at the time of runaway in FIG. 3 is as follows. Here, steps 21 to 23 are the same as the above-mentioned steps. In this embodiment, the register 2 is forcibly reset when a runaway time elapses, for example, when the program counter is destroyed for 100 ms. The program data of the history area 1 already stored in the register 2 is read again into the register 2 (step 23A), and the work block a
Re-execute the process of. In this way, the program of the previous work block is sequentially stored in the history area and left as a history, and is used for the processing of the next work block.

[0016]

As described above, the present invention is provided with the storage unit having the history area for storing the program for each work block and the register for using the program read from the history area for each work block. This has the effect of reusing the program that was temporarily saved during a runaway.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of a normal operation of this embodiment.

FIG. 3 is a flow chart of an abnormal operation of the present embodiment.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a flowchart illustrating an operation of a conventional example.

[Explanation of symbols]

 1, 11 CPU 2, 12 Register 4, 14 Storage unit 4A Program storage unit 4B, 4C History area 13 Processor 15 Watchdog timer

Claims (2)

[Claims] 1. A means for temporarily saving a program used each time a work block is processed, reading the saved program again for a next work block, and temporarily storing the program, and the temporarily saved program. A processing method of a CPU, comprising: a storage unit having two history areas for storing each work block. 2. The CPU processing method according to claim 1, wherein the register, which is means for temporarily storing, is forcibly reset from the outside at a cycle in which a normal processing time of each work block is held.