JPH05298092A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate the out-of-order execution speed of instructions. CONSTITUTION:A first buffer group 3 consisting of four entry buffers A, B, C, and D is provided in order to enable the out-of-order execution of instructions. A second buffer group 20 is provided so that entries of buffers C and D are saved in the case that instructions stored in buffers A and B in the first buffer group 3 have mutual flow depending relations and instructions stored in buffers C and D of the first buffer group 3 are already executed in advance. Thus, the succeeding instruction are stored into the first buffer group 3 and the execution in advance is available.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention enables pre-execution (hereinafter referred to as "out-of-order execution") of an instruction that does not have a flow dependency (read after writing) with respect to the preceding instruction. A buffer group having fields for storing control information and data information of instructions is provided as a meeting place, and the order of storing the results of executing the instructions in the buffer group in a register or data cache is the order in which the instructions appear in the object code. In-order information processing device.

[0002]

2. Description of the Related Art In recent years, a plurality of arithmetic processing units are provided and a plurality of instructions are out-of-or in one machine cycle.
Information processing apparatuses capable of executing der have been used.

FIG. 4 is provided with two arithmetic processing units and outputs up to two instructions out-of-o in one machine cycle.
The block configuration of an example of the conventional information processing apparatus which performs rder is shown. The information processing apparatus shown in the figure includes an instruction cache 1, a decoder 2, a buffer group 3, first and second arithmetic processing units 4, 5, a register group 6, and a data cache 7. There is. In the figure, 8 to 19 are
A bus for transferring instructions or data.

This information processing apparatus is constructed on the premise that each instruction consists of the following four fields. That is, the first field is the operation code of the instruction, the second and third fields are the numbers of the source registers in which the first and second source data to be processed by the instruction indicated by the operation code of the first field are stored, The fourth field is the number of the destination register that should store the processing result of the instruction.

The decoder 2 decodes two instructions issued simultaneously from the instruction cache 1. The first and second arithmetic processing units 4 and 5 perform address calculation, arithmetic operation and logical operation. Also, register group 6
Has a large number of registers that function as source registers and destination registers of the first and second arithmetic processing units 4 and 5.

The buffer group 3 for realizing the out-of-order execution of instructions is composed of four-entry buffers A, B, C, and D, and has a function of examining the data flow dependency between the stored instructions. Is to have.
Each entry A, B, C, D of the buffer group 3 has eight fields as shown in FIG.
In FIG. 5, PC is a field for storing the value of the program counter. Register numbers of the first and second source registers and the destination register are stored in S1, S2, and D, respectively. S1_LOCK,
Each field of S2_LOCK and D_LOCK indicates whether or not there is a flow dependency relationship. That is, when the first source register of the instruction of a certain entry uses the execution result of the preceding instruction, both the former S1_LOCK and the latter D_LOCK are set. If the second source register of the instruction of a certain entry uses the execution result of the preceding instruction, the former S2_LOCK
And the latter D_LOCK are set together. DATA
The execution result of the instruction is stored in the field of.

An information processing apparatus having such a configuration is
The out-of-order execution is performed as follows. Control dependencies are not taken into account for ease of explanation.

First, 2 issued from the instruction cache 1
The instruction is decoded by the decoder 2, and the decoder 2 reads the respective register numbers of the source register and the destination register of the issued first and second instructions, and reads them together with the values of the program counters of the first and second instructions. Store in buffer group 3. S1 and S in buffer group 3
Executed in the DATA field because the register number of the source register of the first and second instructions stored in the 2 field and the preceding instruction already stored in the buffer group 3 and not executed or being executed When the flow dependency is detected by matching the register number of the destination register stored in the D field of the entry in which the result is not stored, S1_LOCK or S2 of the corresponding entry is detected.
_LOCK and D_LOCK are set.

The first and second arithmetic processing units 4 and 5 execute only the instruction stored in the entry in which both S1_LOCK and S2_LOCK in the buffer group 3 are reset. Source data of an executable instruction is read from the register group 6 and address calculation, arithmetic operation or logical operation is performed according to the executed instruction. When a plurality of instructions can be executed at the same time, two entries are executed in ascending order of the value of the PC field in the buffer group 3.

The respective calculation results of the first and second calculation processing devices 4 and 5 are temporarily stored in the DATA field of the executed entry in the buffer group 3. At the same time, S1_locked by D_LOCK of the executed instruction for all entries in the buffer group 3.
LOCK and S2_LOCK are reset. The execution result once stored in the DATA field in the buffer group 3 is stored in the register group 6 or the data cache 7 according to the operation code of the instruction.

As described above, the instructions in the buffer group 3 are
As soon as the source data can be referenced from the register group 6 or the data cache 7, the execution of the instruction of that entry is started, so the instruction execution order is out-of-o.
Become rder.

[0012]

In the above conventional information processing apparatus, in the buffer group 3, the preceding instruction (first instruction) is given.
Is not executed or is being executed, another instruction (second instruction) having a flow dependency relationship with the preceding instruction is not executable, and further another instruction (third and fourth instructions) ) Has already been executed in advance, but is in a waiting state for storing the execution results of the first and second instructions in the register group 6 or the data cache 7,
Since there is no space in the buffer group 3, there is a problem that the preceding execution of further instructions (fifth and sixth instructions) following the fourth instruction cannot be realized.

The processing operation of the information processing apparatus when the following instructions are stored in the respective entries of the buffer group 3, that is, the buffers A, B, C and D will be described below. That is, And

The state of each field of the buffer group 3 is shown in FIG.
Shown inside. Further, the instruction to be executed next to the instruction stored in the buffer D is 110 ADD% 9,% 10,% 11 114 ADD% 9,% 12,% 13 118 ADD% 9,% 14,% 15 11C ADD% 9,% 16,% 17.

Since the destination register of the SUB instruction stored in the buffer A is% 3 and one of the source registers of the ADD instruction stored in the buffer B is% 3, data flows between these two instructions. It has a dependency relationship. Therefore, as shown in FIG. 5, the D_LOCK of the buffer A and the S1_LOCK of the buffer B are 1
Is set. Further, it is assumed that the instructions stored in the buffers C and D have already been executed in advance, and the execution results “10” and “20” of the instructions are stored in the DATA field, respectively.

For simplicity of explanation, there is no data dependency other than buffer A and buffer B, and the control dependency is not taken into consideration.

FIG. 6 shows buffers A, B, C, and
The processing operation of the instruction stored in D is shown. In the figure, -F, -L, -E after the numerical value representing PC,
-S indicates that the instruction of the PC is in the fetch stage,
It shows that it is in the load stage, execution stage, and store wait state. Those enclosed in a circle indicate that the value of the DATA field of the buffer at that stage is in the register group 6 or the data cache 7 depending on the operation code.
It shows that it is stored inside.

In this example, the ADD instruction stored in the buffer B can be executed only after the execution result of the operation of the SUB instruction stored in the buffer A is confirmed.

In the first stage, since S1_LOCK and S2_LOCK stored in the buffer A are reset, the SUB instruction becomes the execution stage,
The source data stored in the source registers% 1 and% 2 is read from the register group 6 to the buses 10 and 11 (see FIG. 4), respectively. Then, the subtraction according to the operation code SUB is performed in the first arithmetic processing unit 4 by using the read source data. After that, the calculation result is the bus 1
4 to the DATA field of the buffer A. Since S1_LOCK stored in the buffer B is set to 1, the ADD instruction does not enter the execution stage but remains in the load stage. The MOV instruction stored in the buffers C and D remains in the store wait state because the execution results of the instructions stored in the buffers A and B are not stored in the register group 6 or the data cache 7.

In the second stage, DATA of buffer A is
Since the calculation result is stored in the field, 1 set in D_LOCK of buffer A and S1_LOCK of buffer B is reset. And D in buffer A
The calculation result stored in the ATA field is read out to the bus 17 and stored in% 3 in the register group 6. The ADD instruction stored in the buffer B does not enter the execution stage because S1_LOCK is set when the second stage is started. The instructions stored in the buffers C and D remain in the store wait state.

At the third stage, since the buffer A is empty, the ADD instruction (PC = 110) is read from the instruction cache 1. S1_LOCK and S2 of buffer B
Since _LOCK and _LOCK are reset, the ADD instruction (P
C = 104) becomes the execution stage, and the source data stored in the source registers% 3 and% 2 in the register group 6 are read to the buses 10 and 11, respectively. Then, addition according to the operation code ADD is performed by the first arithmetic processing unit 4 using the read source data.
After that, the calculation result is stored in the DATA field of the buffer B through the bus 14. The instructions stored in the buffers C and D remain in the store wait state.

In the fourth stage, the decoder 2 receives the ADD instruction (PC = 110) read from the instruction cache 1.
And the register numbers% 9 and% 10 of the first and second source registers and the register number% 11 of the destination register are stored in the S1 and S2 fields of the buffer A, respectively. In this case, there is no flow dependency, so S1_LOCK and S2_LOCK of buffer A
Is not set. Then, DATA of buffers B and C
The calculation results stored in the field are transferred to the bus 17,
The data is read out to 18 and stored in% 4 and% 6 of the register group 6.
The instruction stored in the buffer D remains in the store wait state.

In the fifth stage, S1_L of buffer A
Since OCK and S2_LOCK are reset, A
The DD instruction (PC = 110) enters the execution stage, and the source data stored in the source registers% 9 and% 10 is read from the register group 6 to the buses 10 and 11, respectively. Then, addition according to the operation code ADD is performed by the first arithmetic processing unit 4 using the read source data. Since the buffers B and C are empty, two ADD instructions (PC = 114, 118) are read from the instruction cache 1. Then, the calculation result stored in the DATA field of the buffer D is read to the bus 17 and stored in% 8 of the register group 6.

Thus, in the above case, the buffer C,
The MOV instruction stored in D is already executed in advance and is waiting to be stored. However, since the instruction stored in the buffers A and B has not been executed yet, the instruction stored in the buffers A and B is Buffer group 3 until it is executed and the result is stored in register group 6 or data cache 7.
Since there is no empty space in the next ADD command (PC = 110)
Is not executed until the fifth stage.

An object of the present invention is to out-of-o instructions.
A buffer group for realizing rder execution has a plurality of predecessor instructions that have a flow dependency relationship with each other and are not executed or being executed, and store results of the plurality of predecessor instructions although they have been predecessor executed. By eliminating the situation of being occupied by a subsequent instruction in a waiting state, another instruction following the subsequent instruction can be executed in advance, thereby realizing high-speed execution of the instruction.

[0026]

To achieve the above object, the present invention provides a first buffer group and a second buffer group each having a field for storing control information and data information of an instruction, By saving the executed processing result of the first buffer group to the second buffer group, an empty space is created in the first buffer group, and subsequent instructions are stored in the first buffer group from the instruction cache. It is intended to process instructions.

Specifically, the solving means taken by the present invention comprises an instruction cache for supplying a plurality of instructions, a data cache, a plurality of arithmetic processing units, and a large number of registers capable of functioning as a source register and a destination register. A register group having the same, a decoder for decoding a plurality of instructions supplied from the instruction cache, and first and second buffer groups each having a field for storing control information and data information of the instruction decoded by the decoder. A pre-execution is carried out from an executable instruction of the instructions provided and stored in the first buffer group, and the processing result of the instruction stored in the first buffer group or the second buffer group is used as a register group or a data cache. In the information processing device, the order of storing in Entries containing the first buffer group of executed as the result is obtained by the to be saved in the second buffer group.

[0028]

According to the present invention, since the executed processing result of the first buffer group is saved in the second buffer group, an empty space is created in the first buffer group, so that the flow dependence relationships are established. A first buffer group including a plurality of predecessor instructions which are in execution and are being executed, and a succeeding instruction which is in a waiting state for storing the results of the plurality of predecessor instructions even though the predecessor instructions have already been executed. The situation in which the As a result, another instruction following the subsequent instruction can be stored in the first buffer group, the other instruction can be executed in advance, and high-speed execution of the instruction can be realized.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of an information processing apparatus according to this embodiment. In this embodiment, an information processing apparatus including two arithmetic processing devices will be described as an example.

The information processing apparatus of the present embodiment comprises an instruction cache 1, a decoder 2, a first buffer group 3, first and second arithmetic processing units 4, 5, a register group 6, and a data cache. 7 and a second buffer group 20. In the figure, 8 to 19 and 21 to 24 are buses for transferring instructions or data.

The commands handled by this information processing apparatus are also shown in FIG.
As in the case of, from the operation opcode (first field), the first and second source register numbers (second and third fields), and the destination register number (fourth field) Is supposed to be.

The decoder 2 decodes two instructions issued simultaneously from the instruction cache 1. The first and second arithmetic processing units 4 and 5 perform address calculation, arithmetic operation and logical operation. Also, register group 6
Has a large number of registers that function as source registers and destination registers of the first and second arithmetic processing units 4 and 5.

The first buffer group 3 for realizing out-of-order execution of instructions is composed of four-entry buffers A, B, C, and D, and the data flow dependence relationship between the stored instructions. It has a function of examining. Each entry A, B, C of the first buffer group 3
Each D has eight fields, as shown in FIG. PC is a field for storing the value of the program counter. Register numbers of the first and second source registers and the destination register are stored in S1, S2, and D, respectively. S1_LOCK,
Each field of S2_LOCK and D_LOCK indicates whether or not there is a flow dependency relationship. That is, when the first source register of the instruction of a certain entry uses the execution result of the preceding instruction, both the former S1_LOCK and the latter D_LOCK are set. If the second source register of the instruction of a certain entry uses the execution result of the preceding instruction, the former S2_LOCK
And the latter D_LOCK are set together. DATA
The execution result of the instruction is stored in the field of.

The second buffer group 20 is provided to save the store-waiting entries in the first buffer group 3, and as shown in FIG. It consists of four-entry buffers E, F, G, and H having the same field structure as in the case of

In the information processing apparatus having the above configuration, the processing operation when the next instruction is stored in each entry in the first buffer group 3, that is, the buffers A, B, C and D will be described. .. That is, And

The state of each field of the first buffer group 3 is shown in FIG. Further, the instruction to be executed next to the instruction stored in the buffer D is 110 ADD% 9,% 10,% 11 114 ADD% 9,% 12,% 13 118 ADD% 9,% 14,% 15 11C ADD% 9,% 16,% 17.

Since the destination register of the SUB instruction stored in the buffer A is% 3 and one of the source registers of the ADD instruction stored in the buffer B is% 3, data flows between these two instructions. It has a dependency relationship. Therefore, as shown in FIG. 2, D_LOCK of buffer A and S1_LOCK of buffer B are 1
Is set. Further, it is assumed that the instructions stored in the buffers C and D have already been executed in advance, and the execution results “10” and “20” of the instructions are stored in the DATA field, respectively. At this point, the second buffer group 20
Each entry E, F, G, H of is empty.

For simplicity of explanation, there is no data dependency other than buffer A and buffer B, and the control dependency is not taken into consideration.

FIG. 3 shows buffers A, B, C, and
The processing operations of the instructions stored in D, E, F, G, and H are shown. In the figure, after the numerical value representing PC
F, -L, -E, and -S indicate that the instruction of the PC is in the fetch stage, load stage, execution stage, and store wait state, respectively. What is surrounded by a square in the first buffer group 3 indicates that the value of each field is saved in the second buffer group 20 at that stage. What is circled indicates that the value of the DATA field of the buffer is stored in the register group 6 or the data cache 7 at that stage depending on the operation code.

In this example, the ADD instruction stored in the buffer B can be executed only after the execution result of the operation of the SUB instruction stored in the buffer A is confirmed.

In the first stage, since S1_LOCK and S2_LOCK stored in the buffer A are reset, the SUB instruction becomes the execution stage,
Source data stored in the source registers% 1 and% 2 is read from the register group 6 to the buses 10 and 11 (see FIG. 1), respectively. Then, the subtraction according to the operation code SUB is performed in the first arithmetic processing unit 4 by using the read source data. After that, the calculation result is the bus 1
4 to the DATA field of the buffer A. Since S1_LOCK stored in the buffer B is set to 1, the ADD instruction does not enter the execution stage but remains in the load stage. The MOV instruction stored in buffers C and D is waiting for store, so bus 2
4, the values of the fields of the buffers C and D in the first buffer group 3 are saved in the buffers E and F in the second buffer group 20, respectively.

In the second stage, DATA of buffer A is
Since the calculation result is stored in the field, 1 set in D_LOCK of buffer A and S1_LOCK of buffer B is reset. Then, the calculation result stored in the DATA field of the buffer A is read to the bus 17 and stored in% 3 of the register group 6. The ADD instruction stored in the buffer B does not enter the execution stage because S1_LOCK is set to 1 when the second stage is started. Buffers C and D are empty, so two ADD instructions (PC = 110, 114)
From the instruction cache 1. The entries in the buffers E and F are still waiting to be stored.

In the third stage, since the buffer A is empty, the ADD instruction (PC = 118) is read from the instruction cache 1. S1_LOCK and S2 of buffer B
Since _LOCK and _LOCK are reset, the ADD instruction (P
C = 104) becomes the execution stage, and the source data stored in the source registers% 3 and% 2 is read from the register group 6 to the buses 10 and 11, respectively. Then, addition according to the operation code ADD is performed by the first arithmetic processing unit 4 using the read source data. After that, the calculation result is transferred to the DA of the buffer B through the bus 14.
It is stored in the TA field. Two ADD instructions read from instruction cache 1 (PC = 110, 114)
Is decoded by the decoder 2 and one ADD instruction (PC =
110) the register numbers% 9 and% 10 of the first and second source registers and the register number% 11 of the destination register in the S1 and S2 fields of the buffer C, and the other ADD instruction (PC = 114) 1st and 2nd
The source register register numbers% 9 and% 12 and the destination register register number% 13 are stored in the S1 and S2 fields of the buffer D, respectively. In this case, there is no flow dependency, so S1_ of buffers C and D
LOCK and S2_LOCK are not set. The entries in the buffers E and F are still waiting to be stored.

In the fourth stage, the decoder 2 receives the ADD instruction (PC = 118) read from the instruction cache 1.
And the register numbers% 9 and% 14 of the first and second source registers and the register number% 15 of the destination register are stored in the S1 and S2 fields of the buffer A, respectively. In this case, there is no flow dependency, so S1_LOCK and S2_LOCK of buffer A
Is not set. Then, the calculation result stored in the DATA field of the buffer B is read out to the bus 17 and stored in% 4 of the register group 6. As for the instructions stored in the buffers C and D, since S1_LOCK and S2_LOCK are reset, two ADD instructions (PC = 11
(0, 114) is the execution stage, and the source data stored in the source registers% 9 and% 10 from the register group 6 are transferred to the buses 10 and 11, respectively.
The source data stored in 9 and% 12 are read to the buses 12 and 13, respectively. And the opcode ADD
Is added in each of the first and second arithmetic processing units 4 and 5 using the read source data. After that, the calculation result is stored in the DATA field of the buffers C and D through the buses 14 and 15. The entries in the buffers E and F are still waiting to be stored.

In the fifth stage, S1_L of buffer A
Since OCK and S2_LOCK are reset, A
The DD instruction (PC = 118) becomes the execution stage, and the source data stored in the source registers% 9 and% 14 are read from the register group 6 to the buses 10 and 11, respectively. Then, addition according to the operation code ADD is performed by the first arithmetic processing unit 4 using the read source data. Since the buffer B is empty, the ADD instruction (PC = 11C) is read from the instruction cache 1. The operation result stored in the DATA field of the buffers C and D remains in the store wait state. DAT of buffers E and F
The calculation results stored in the A field are stored in the bus 2 respectively.
The data is read out to 1 and 22 and stored in% 6 and% 8 of the register group 6.

As described above, in this embodiment, the buffers A and B are
If the instructions stored in C have a flow dependency relationship and the instructions stored in the buffers C and D have already been executed in advance, the entries of the executed buffers C and D are transferred to the buffers E and F. By saving the instruction, the subsequent instruction can be executed in advance, and the instruction execution speed is improved.

[0047]

As described above, the information processing apparatus of the present invention is provided with the first buffer group and the second buffer group each having the field for storing the control information and the data information of the instruction. By saving the executed entry of the first buffer group to the second buffer group, the instruction subsequent to the instruction in the first buffer group can be stored in the first buffer group from the instruction cache, and the preceding instruction of the instruction can be stored. Execution becomes possible. Therefore, according to the present invention, high-speed execution of instructions can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a field structure of first and second buffer groups in FIG.

FIG. 3 is a diagram showing a processing operation in the information processing apparatus of FIG.

FIG. 4 is a block diagram of a conventional information processing device.

5 is a diagram showing a field structure of a buffer group in FIG.

6 is a diagram showing a processing operation in the information processing apparatus of FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 instruction cache 2 decoder 3 1st buffer group 4 1st arithmetic processing unit 5 2nd arithmetic processing unit 6 register group 7 data cache 20 2nd buffer group

Claims (1)

[Claims] 1. An instruction cache that supplies a plurality of instructions, a data cache, a plurality of arithmetic processing units, a register group having a large number of registers that can function as a source register and a destination register, and a supply from the instruction cache. And second decoders each having a field for storing control information and data information of the instruction decoded by the decoder.
Of the instructions stored in the first buffer group, the preceding execution is performed from the executable instruction, and the instructions stored in the first buffer group or the second buffer group are processed. The order in which the result is stored in the register group or the data cache is an information processing apparatus that is faithful to the order in which instructions appear in the object code, and the entry including the executed processing result of the first buffer group is the second An information processing device characterized by being saved in a buffer group of.