JPH05297406A - Active matrix display device - Google Patents

Abstract

PURPOSE:To efficiently arrange pixels by forming a gate line connected to an (n+1) th row and a gate line connected to an (n-1) th row between a couple of gate lines connected to pixels in an (n) th row in parallel to those gate lines. CONSTITUTION:A transfer gate circuit is formed by connecting gate lines Xn and Xn' to respective TFTs of the pixels in the (n) th row, and auxiliary capacitances C1 and C2 are formed by making pixel electrodes of the transfer gate circuit overlap so as to connect gate lines Xn-1' (connected to the TFT of the pixels in the (n-1) th row) and Tn+1 (connected to the TFTs of the pixels in the (n-1) th row) between the gate lines Xn and Xn-1. Further, the gate electric conductors which form those auxiliary capacitances function as not electric conductors dedicated to the auxiliary capacitances, but the gate electrodes of other pixels. Namely, no extra electric conductor is provided, so the aperture rate does not decrease. Ideal hexagonal or honeycomb-shaped structure is obtained without specially bending the electric conductors so as to improve the mixture of colors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic display device such as an active matrix liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, active matrices for driving liquid crystal displays have been extensively studied and put into practical use. In a conventional active matrix circuit, a capacitor sandwiching a liquid crystal is formed between a pixel electrode and a counter electrode, and a thin film transistor (TFT) controls an electric charge which flows in and out of the capacitor. In order to display images stably, it was required that the voltage of both electrodes of this capacitor be kept constant, but it was difficult for several reasons.

One problem is a phenomenon (ΔV) in which the gate signal is capacitively coupled with the pixel potential due to the parasitic capacitance between the gate electrode of the TFT and the pixel electrode, and the voltage fluctuates. That is, the gate pulse (signal voltage) is V _G and the pixel capacitance is C
_LC, the parasitic capacitance of the gate electrode and the pixel electrode C 'when _{A, ΔV = C'V G / (C} LC + C' occurs when the variation of the voltage represented by) ... is removed the gate pulse did. The magnitude of this ΔV is theoretically the same regardless of the magnitude or polarity of the signal applied to the data line Y _m .

In order to solve this problem, C _{LC is changed} to C '
Therefore, it is possible to reduce the parasitic capacitance by making the source / drain in self-alignment by inserting the auxiliary capacitance in parallel with the pixel capacitance, and apparently the denominator of the above equation. Has been made larger.

Recently, a CMO as shown in FIG.
It has been attempted to solve this problem by using an S transfer gate circuit (see, for example, Japanese Patent Laid-Open No. Hei 2
-178632). That is, in such a transfer gate circuit, when a negative pulse is simultaneously applied to the gate electrode of the PMOS and a positive pulse (each pulse height is V _G ) is applied to the gate electrode of the NMOS, [Delta] V _{is, ΔV = (C 1 -C 2} ) V G / (C 1 + C 2 + C LC) ··· ( here, the C _1, C _2, capacitance between the respective TFT and the pixel capacitor Therefore, ΔV can be set to 0 by making C ₁ and C ₂ equal.

In addition, since at least two TFTs exist for one pixel, even if one TFT does not operate due to a defect, it can be supplemented by another TFT. Of course, in this case, depending on the degree of failure,
Since the equation does not apply and the usual active matrix equation is applied, ΔV becomes very large when the parasitic capacitance is extremely large.

Generally, in an active matrix circuit,
Electric charges are discharged from the pixel electrode through the TFT. Therefore, although the conventional TFT has been provided with an auxiliary capacitance to suppress the discharge of the charges, the auxiliary gate is also provided in the transfer gate type circuit of FIG. 1 to suppress the discharge of the charges. .. And in that case,
Taking advantage of the characteristic of the transfer gate circuit that ΔV is 0 if C ₁ and C ₂ are equal, the pixel electrodes are overlapped with the gate lines (X _n , X _{n + 1} ) as shown in FIG. 1B. Then, it was attempted to use this as the auxiliary capacitance (C ₁ , C ₂ ). That is, the gate line has the same level as the ground level except during the application of the pulse. Therefore, for example, it has been expected that a high image quality can be obtained while maintaining the aperture ratio without the need to newly provide a ground wire.

[0008]

However, as shown in FIG.
In forming the auxiliary capacitance as shown in (B), it became difficult to make C ₁ and C ₂ exactly equal, especially when the size of the auxiliary capacitance became large. For example, the parasitic capacitance per TFT when the source / drain is formed by the self-alignment method can be set within 10% of the pixel capacitance, and the variation in the parasitic capacitance between the two TFTs is further 30.
It can be within%. That is, (C ₁ -C ₂ ) in the equation can be within 3% of the pixel capacity.

On the other hand, when the capacitance is artificially set in addition to the parasitic capacitance which is naturally formed, the size of one auxiliary capacitance is required to be about the same as the pixel capacitance. Therefore, even if the difference between the _two auxiliary capacitances C ₁ and C ₂ is within 10%, (C ₁ -C ₂ ) in the equation is 10 to 20% of the pixel capacitance. Actually, a larger variation occurs due to a subtle difference in the width of the gate line, a shift in the overlap of the pixel electrodes, and the like, and the auxiliary capacitance is required to be 10 times larger than the pixel capacitance. In some cases, ΔV may become extremely large.

[0010]

In order to solve this problem, the present invention proposes a circuit arrangement as shown in FIG. That is, in the present invention, each TFT of the pixel in the nth row is
, The gate lines X _n and X _n 'are connected to form a transfer gate circuit, and the gate lines X _n-1 ' (connected to the TFTs of the pixels in the (n-1) th row) and X _{n in between are formed. In +1} (connected to the TFT of the pixel in the (n + 1) th row), the pixel electrodes of this transfer gate circuit are overlapped to form auxiliary capacitors C ₁ and C ₂ . Further, as is clear from the figure, the gate wirings that form these auxiliary capacitances do not function as wirings dedicated to the auxiliary capacitances, but function as gate electrodes of other pixels. That is, since no extra wiring is provided, the aperture ratio does not decrease.

FIG. 2 shows a circuit diagram and a configuration for explaining the present invention. In the case of adopting such a configuration, if one data line (for example, Y _m ) is focused on, it is efficient to maintain the aperture ratio if the pixels are alternately arranged so as to sandwich the data line. is there. In addition, such a structure is also preferable for performing color display.

That is, conventionally, in order to improve the color mixing property, the arrangement of pixels has been made into a honeycomb shape or a hexagonal shape, but at that time, the wiring is bent accordingly. This leads to an increase in wiring resistance, and also causes defects due to the difficulty of fabrication. However, according to the present invention, an ideal hexagonal structure can be obtained without the need to bend the wiring.

In the present invention, C ₁ and C ₂ in the equation (note that they are different from C ₁ and C _{2 in} FIG. 2) are substantially parasitic capacitances of each TFT, which is also clear from the figure. As described above, the pixel electrodes are not overlapped with each gate line. Therefore, in the formula, the numerator is extremely small, and the denominator C _LC is substantially large by adding the auxiliary capacitances C ₁ and C ₂ in addition to the pixel capacitance.

It should be noted here that the auxiliary capacitance is formed with the gate lines X _n-1 'and X _{n + 1} as one of the electrodes, so that the potential of the pixel electrode is the potential of these gate lines. Strongly influenced by. That is, pulses are periodically applied to these gate lines. However, this is only temporary and returns to its original state immediately with little visual impact. This is because the pulse is applied to these gate lines only for a short time in one frame. Hereinafter, the present invention will be described in more detail with reference to examples.

[0015]

EXAMPLE FIG. 3 shows a structural example of the active matrix of the present invention. This circuit is substantially the same as the circuit diagram shown in FIG. No special technique is required to fabricate this circuit, and conventional TFT fabrication techniques are used. FIG. 4 shows an example of manufacturing steps for manufacturing the circuit of the present invention. Figures (A-1), (B-1), (C-1),
(D-1) is a cross-sectional view, (A-2), (B-2),
(C-2) and (D-2) are top views. For details of each process, see Japanese Patent Application Nos. 4-30220 and 4-3.
Since it is described in 8637 and 3-273377,
No particular description is given here.

First, the underlying silicon oxide film 2 is formed on the substrate 1. This may be a multilayer film of silicon oxide and silicon nitride. Then, the island-shaped semiconductor regions 3 and 3 ′ are formed. Further, a gate insulating film (silicon oxide) 4 was formed, and gate wirings 6, 6'and 7 were formed of aluminum. (Fig. 4 (A
-1) and (A-2))

After that, anodic oxidation was performed to form aluminum oxide coatings 8, 8'and 9 around the gate wiring. The thickness was 350 nm. And a known CMOS
Impurity implantation was performed using the formation technique to form impurity regions (source / drain) 10 and 10 '. (Fig. 4
(B-1) and (B-2))

Then, a silicon oxide interlayer insulator is formed to a thickness of 50.
Only 0 nm was formed. Here, silicon oxide is left only at the intersections of the data lines and the gate lines, and the rest is removed to form silicon oxide regions 11a, 11b, and 11c. At this time, the silicon oxide film formed as the gate oxide film is also removed to expose the impurity semiconductor region. (Fig. 4
(C-1) and (C-2))

A capacitance is generated at the intersection of the data line and the gate line, and this capacitance causes a delay of the gate signal and data. In order to reduce the capacitance, it is preferable to form the interlayer insulator thick as described above, but for the other portions, such an interlayer insulator is not particularly required. In particular, when the silicon oxide layer formed up to the one formed as the gate insulating film is removed as in the present example, the conventional contact hole is unnecessary, and therefore the contact failure is significantly reduced. did it.

In such a process, a mask is required for the silicon oxide regions 11a, 11b and 11c, but a mask is not required for the other portions. This is because the aluminum oxide formed as the anodic oxide film has extremely strong corrosion resistance, and the etching rate, for example, in etching with buffer hydrofluoric acid is sufficiently slower than the etching rate of silicon oxide.

Therefore, with respect to the gate electrode portion, the silicon oxide film can be etched in a self-aligned manner. conventionally,
Fine mask alignment was necessary to form the contact hole of the TFT, but this is not necessary in this example. Of course, a method of forming a contact hole may be adopted as in the conventional case.

Finally, the data line 12 and the electrodes 13 and 13 'are formed of aluminum or chrome, and ITO is used.
Then, the pixel electrode 14 was formed. At this time, by arranging the pixel electrode so as to overlap the central gate wiring 7, an auxiliary capacitance could be formed between them. Especially in this case,
Although aluminum oxide (anodic oxide) having a thickness of 350 nm is formed between the gate wiring and the pixel electrode, its permittivity is about three times larger than that of ordinary silicon oxide, which is effective. (Fig. 4 (D-1) and (D-2))

In the present embodiment, the structure of the cross section of the auxiliary capacitor has a structure of metal wiring (aluminum) / anodic oxide (aluminum oxide) / pixel electrode (ITO). In this case, aluminum oxide has a relative dielectric constant of
Since it is larger than silicon oxide, it contributes to increase the auxiliary capacitance. When a larger auxiliary capacitance is required, tantalum or titanium may be used for the gate line, anodic oxidation may be performed, and those oxides may be used as the dielectric of the auxiliary capacitance.

Alternatively, a method of metal wiring / oxide (which can be formed by a CVD method or a sputtering method such as silicon oxide or silicon nitride) which is conventionally used, without taking such a manufacturing method / structure is used. May be used.

[0025]

As described above, according to the present invention, the pixels can be efficiently arranged. Such a pixel arrangement not only secures the auxiliary capacitance without lowering the aperture ratio and is capable of performing stable display, but is also effective in performing color display. The above description relates to a planar type TFT often used for polysilicon TF, but an inverted stagger type TFT often used for amorphous silicon TFT.
However, it is clear that the same effect can be obtained.

Further, although the present invention does not describe a specific operating method of the active matrix, in addition to the conventional analog gray scale method, the digital gray scale method (for example, the special gray scale method) which is the invention of the present inventors. There is no problem in performing gradation display according to Japanese Patent Application No. 3-163873).

[Brief description of drawings]

FIG. 1 is a circuit diagram / configuration diagram of a conventional active matrix.

FIG. 2 shows a circuit diagram of an active matrix of the present invention.

FIG. 3 shows a structure of an active matrix of the present invention.

FIG. 4 shows an example of steps for manufacturing a circuit according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Base silicon oxide layer 3, 3'island semiconductor region 4 Gate insulating film 6, 6 ', 7 Gate electrode / wiring 8, 8', 9 Anodized film 10, 10 'Impurity region 11a, 11b, 11c Interlayer Insulator 12 Data line 13, 13 'Metal electrode 14 Pixel electrode

Claims (3)

[Claims] 1. In an active matrix display device, each pixel has at least one set of TFTs having different conductivity types, a gate electrode of each TFT is connected to a gate line, and a source or a drain of each TFT. One of the gate lines is connected to the data line, and the other one of the source and the drain is connected to the pixel, and the gate line is connected between the pair of gate lines connected to the pixel in the nth row. And the gate line connected to the (n + 1) th row in parallel with
-1) A display device having gate lines connected to rows. 2. An N-type or P-type first display connected to a first gate line in an active matrix display device.
Second field effect semiconductor element having a conductivity type opposite to that of the first field effect semiconductor element and the first semiconductor element connected to the second gate line, the pixel electrode, and the third and fourth gate lines. And a pixel electrode having an electrostatic capacitance between them as an auxiliary capacitance. 3. In the active matrix display device, the TFT of the pixel on the i-th row and the j-th column is (2i + 1) th pixel.
The gate line of the row and the gate line of the (2i + 4) th row are connected,
The TFT of the pixel in the (i + 1) th row and the jth column is (2i +
The gate line in the 3rd row is connected to the gate line in the (2i + 6) th row, and the pixel in the i-th row and the j-th column and the pixel in the (i + 1) -th row and the j-th column are opposite to each other across the data line. Display device characterized by being in.