JPH05292086A - Heavy load test system - Google Patents

Abstract

PURPOSE:To make it possible to test a line storage device in the same heavy load state as the actual operation as much as possible, regarding the heavy load test system in an exchange connecting plural line storage devices storing communication lines to each other via a bus. CONSTITUTION:A test object line storage device 200-1 and plural line storage devices 200-2 other than the test object are provided with a test data transmission means 201 for transmitting test data and a test data retransmission means 202 returning the received test data returned to its own device from line storage devices other than respective test objects to the line storage devices other than the test object of a transmission origin when the test data is received, and with a test data return means 203 for returning the received test data transmitted from the test object line storage device to the line storage device where the test data is made the test object when the test data is received, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high load test system for an exchange in which a plurality of line accommodating devices respectively accommodating communication lines are mutually connected via a bus.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an example of an exchange to which the present invention is applied, FIG. 8 is a diagram showing an example of a conventional line system control device, and FIG. 9 is a bus communication test process in FIG. 10 is a diagram showing an example of the line communication test process in FIG. 8, and FIG. 11 is a diagram showing an example of the buffer accumulation state in FIG. 9.

The exchange shown in FIG. 7 is common to a plurality of line system controllers 2 each accommodating a communication line 1 and transmitting and receiving required data via each communication line 1. And a redundant system management device 3 for controlling data transfer between the line control devices 2 and a dual system bus 4 for connecting the line control devices 2 and the system management devices 3 to each other. It is equipped with.

The conventional line control device shown in FIG. 8 includes a processing unit (CPU) 21, a storage unit (MM) 22, and a DM.
An A control unit (DMC) 23, a line control unit (LIC) 24, and a line control unit (LIC) 24 are provided, and a processing unit (CPU) 21 controls the whole line control device 2.
The storage unit (MM) 22 stores various programs and data, and the DMA control unit (DMC) 23 stores the storage unit (MM) 2
2 and the line control unit (LIC) 24, or the data transfer between the bus storage unit (MM) 22 and the control unit (BIC) 25 is controlled, and the line control unit (LIC) 24 is controlled.
Transmits and receives data to and from the communication line 1, and the bus control unit (BIC) 25 transmits and receives data to and from the system bus 4.

The line control unit 2 is a bus control unit (BIC)
When testing the bus communication function for transmitting / receiving data to / from another line control device 2 via 25, after storing the test program (TP ₁ ) in the storage unit (MM) 22, the processing unit The test program (TP
By executing ₁ ), the test is executed in the process as shown in FIG.

In FIGS. 8, 9 and 11, the processing unit (CPU) 21 for executing the test program (TP ₁ ) is
After storing predetermined test data D in the storage unit (MM) 22, the DMA transfer start signal a is transmitted to the DMA control unit (DMC) 23, and the transmission data loopback instruction signal is sent to the bus control unit (BIC) 25. b is transmitted.

The bus control unit (BIC) 25 that has received the transmission data loopback instruction signal b is transferred to the DMA control unit (DMC) 2
3, the DMA control unit (DMC) 23 transfers the extraction signal d to the storage unit (MM) 22 to transfer the test data D from the storage unit (MM) 22. It is extracted and transferred to the bus control unit (BIC) 25.

The bus control unit (BIC) 25 sends the test data D transferred from the DMA control unit (DMC) 23 to the bus control unit (BIC) 2 without sending it to the system bus 4.
Buffer memory (BM) that is received back in 5 and built-in
251 is stored.

The DMA control unit (DMC) 23 extracts the test data D already stored in the buffer memory (BM) 251 in the bus control unit (BIC) 25, stores it in the storage unit (MM) 22, and then stores it in the bus. The storage confirmation signals e and f are returned to the control unit (BIC) 25.

The bus control unit (B which receives the storage confirmation signal f
The IC 25 sends the end notification signal g to the processing unit (CPU) 21.
To convey. The processing unit (CP which has received the end notification signal g
U) 21 is the test data D stored in the storage unit (MM) 22 by the processing unit (CPU) 21 during transmission, and the test data D stored in the storage unit (MM) 22 by the DMA control unit (DMC) 23 during reception. By collating with and, the normality of the bus communication function in the state where the bus control unit (BIC) 25 loops back is confirmed.

Next, the line control unit 2 operates the line control unit (L
In the case of testing the line communication function of transmitting and receiving data to and from the communication line 1 via the IC) 24, the storage unit (MM) 22
After storing the test program (TP ₂ ) in the processing unit (C
By executing the test program (TP ₂ ) by the PU 21, the test is executed in the process shown in FIG.

In FIGS. 8 and 10, the processing unit (CPU) 21 for executing the test program (TP ₂ ) stores the predetermined test data D in the storage unit (MM) 22, and then DM
The DMA transfer activation signal n is transmitted to the A control unit (DMC) 23, and the transmission data loopback instruction signal o is transmitted to the line control unit (LIC) 24.

The line control unit (LIC) 24, which has received the transmission data loopback instruction signal o, operates as a DMA control unit (DMC) 2.
When the transfer request signal p is transmitted to the memory controller 3, the DMA control unit (DMC) 23 transmits the extraction signal q to the storage unit (MM) 22 to transfer the test data D from the storage unit (MM) 22. It is extracted and transferred to the line control unit (LIC) 24.

The line control unit (LIC) 24 receives the test data D transferred from the DMA control unit (DMC) 23 back to the line control unit (LIC) 24 without sending it to the communication line 1, and incorporates it. The data is stored in a buffer memory (not shown).

The DMA control unit (DMC) 23 extracts the test data D stored in the buffer memory in the line control unit (LIC) 24, stores it in the storage unit (MM) 22, and then the line control unit (LIC). ) 24, the storage confirmation signals r and s are returned.

Upon receiving the storage confirmation signal s, the line control unit (L
The IC) 24 sends the end notification signal t to the processing unit (CPU) 21.
To convey. The processing unit (CP that received the end notification signal t
U) 21 is the test data D stored in the storage unit (MM) 22 by the processing unit (CPU) 21 during transmission, and the test data D stored in the storage unit (MM) 22 by the DMA control unit (DMC) 23 during reception. By collating with and, the normality of the line communication function in the state returned by the line control unit (LIC) 24 is confirmed.

[0017]

As is apparent from the above description, in the conventional line system control device, when the bus communication function of the line system control device 2 is tested, it is stored in the storage unit (MM) 22. By storing the test program (TP ₁ ) and then executing it by the processing unit (CPU) 21,
A test of looping back and transferring the test data D in the bus control unit (BIC) 25 was executed.

However, according to this test process, the bus control unit (BIC) 25 only returns the test data D internally and does not transfer it to another line system control device 2 via the system bus 4. Therefore, there is a problem that it is impossible to sufficiently test the bus communication function originally included in the bus control unit (BIC) 25.

The buffer memory (BM) 251 built in the bus control unit (BIC) 25 is usually a buffer memory (BM) 251 capable of accumulating data that can be transferred at one time.
A plurality of (four in FIG. 11) are provided, the data intensively transferred from a plurality of other line system control devices 2 are temporarily stored, and the DMA control unit (DMC) 23 extracts them on a first-come-first-served basis. The test program (T
In the conventional test process of executing P ₁ ), the test data D transmitted from the storage unit (MM) 22 to the bus control unit (BIC) 25 by the DMA control unit (DMC) 23 is stored in the buffer memory (BM) 251 (one unit). ) Is received by the storage unit (MM) 22 by the DMA control unit (DMC) 23, one test data D is always transmitted and received via one buffer memory (BM) 251. Therefore, there is a problem that a test cannot be performed in a high load state in which a plurality of data are stored in the plurality of buffer memories (BM) 251 as described above.

The above problems are caused by the test program (TP ₂ )
The same occurs in the test process of executing. Further, since the line control device 2 in the operating state uses the bus communication function and the line communication function in parallel, the processing unit (CP
U) 21, storage unit (MM) 22 and DMA control unit (D)
The MC) 23 is shared by both functions and becomes a kind of high load state. However, in the conventional line system control device 2, the processing unit (CPU) 21 has the test programs (TP ₁ ) and (T ₁ ).
Since P ₂ ) is individually executed, the same test as the actual operation state was not executed.

An object of the present invention is to make it possible to test the line accommodation device under the high load condition as in actual operation as much as possible.

[0022]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, reference numeral 200 denotes a line accommodating apparatus to which the present invention is applied, 100 denotes a communication line accommodated in each line accommodating apparatus 200, and 300 denotes a bus connecting the plurality of line accommodating apparatuses 200 to each other. The line accommodation device to be tested is referred to as 200-1, and the line accommodation device other than the test target is referred to as 200-2.

Reference numeral 201 is a test data delivery means provided in the line accommodation device 200-1 to be tested by the present invention. Reference numeral 202 is a test data retransmitting unit provided in the line accommodation device 200-1 to be tested according to the present invention.

Reference numeral 203 is a test data returning means provided in each line accommodation device 200-2 other than the test object according to the present invention.

[0025]

The test data delivery means 201 delivers the test data to each of the line accommodating devices 200-2 other than the test target.

The test data retransmitting means 202 includes the line accommodating devices 200-2 other than the test target to the own line accommodating device 20.
When the test data returned to 0-1 is received, the received test data is returned to the line accommodating apparatus 200-2 other than the test target of the transmission source.

Upon receiving the test data delivered from the line accommodation device 200-1 to be tested, the test data returning means 203 returns the received test data to the line accommodation device 200-1 to be tested. To do.

The line accommodation device 200 to be tested
1 is the line accommodating device 20 whose test data is other than each test target
Prior to delivery to 0-2, test data return means 203
Is set in the line accommodation device 200-2 other than each test target.

The line accommodation device 200 to be tested
It is considered that after the test data is returned from the line accommodating apparatus 200-2 other than each test target, the test data retransmitting unit 202 starts the reception processing of each test data returned.

Therefore, in the line accommodation device to be tested,
Since the test data is sent back from the other plural line accommodation devices at the same time, the test can be performed under the high load condition similar to the case of the actual operation, and the reliability of the exchange is greatly improved.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a line control device according to an embodiment of the present invention. FIG. 2 (a) shows a device under test, FIG. 2 (b) shows a device other than the test target, and FIG. It is a figure which shows an example of the test operation | movement of a test object apparatus, FIG. 4 is a figure which shows an example of the test operation of the apparatus other than the test object in FIG.
FIG. 5 is a diagram showing an example of the buffer accumulation state in FIG. 2, and FIG. 6 is a diagram showing a comprehensive test process according to an embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings. The target exchange is as shown in FIG.

In the following description, among the plurality of line system controllers 2 constituting the exchange shown in FIG. 7, the line system controller 2 to be tested is the line system controller 2-1 to be tested. The line system control device 2 other than the line system control device 2 which is the test target device is referred to as the non-test line system control device 2-2 (abbreviation, non-test target device).

In FIG. 7, the communication line 1 in FIG.
00, the line accommodating device 200, and the communication line 1 as the bus 300, the line system controller 2 and the system bus 4, and the test program (T) as the test data delivery unit 201 and the test data retransmitting unit 202 in FIG.
P ₃ ) is stored in the storage unit (MM) 22 of the test target device, and the test program (TP ₄ ) is stored in the storage unit (MM) 22 of the test target device as the test data returning means 203 in FIG. In addition, the test program (TP ₄ ) is shown stored in the storage unit (MM) 22 of the device other than the test target.

The test programs (TP ₅ ) and (T ₅ ) stored in the memory unit (MM) 22 of the device under test are stored.
P ₆ ) is a storage unit (MM) of the conventional line system control device 2.
It is equivalent to the test programs (TP ₁ ) and (TP ₂ ) stored in 22.

In FIGS. 2 to 5, when the bus communication function is tested by using the arbitrary line system control device 2 as the device under test (2-1), the test program (TP ₃ ) is stored in the memory unit (MM) 22. After storing (TP ₄ ) and (TP ₄ ), the processing unit (CPU) 21 starts executing the test program (TP ₃ ).

The processing unit (CPU) 21 that executes the test program (TP ₃ ) extracts the test program (TP ₄ ) stored in the storage unit (MM) 22, and the DMA control unit (DMC) 23 and the bus. Through the control unit (BIC) 25 and the system bus 4, the data is sequentially transferred to all non-test target line system control devices 2-2 (step S31 in FIG. 3).

In the line control device 2-2 other than each test target, the processing unit (CPU) 21 transfers the test program (TP ₄ ) transferred via the system bus 4 to the bus control unit (BIC) 25. And DMA controller (DMC) 23
After being stored in the storage unit (MM) 22 via the, the test program (TP ₄ ) is started to be executed.

On the other hand, in the test target line control device 2-1, when the processing unit (CPU) 21 finishes transferring the test program (TP ₄ ) to all the non-test target line control devices 2-2, After transmitting the command to the DMA control unit (DMC) 23 and stopping the data receiving function of the test target line system control device 2-1 (step S32), the storage unit (MM) 22.
The test data D stored together with the test program (TP ₃ ) are extracted, and all the test data D other than the test target is passed through the DMA control unit (DMC) 23, the bus control unit (BIC) 25, and the system bus 4. After sequentially transferring to the line control device 2-2 (step S33), a command is transmitted to the DMA control unit (DMC) 23 to restart the data receiving function stopped in step S32 (step S33).
34).

In the line control device 2-2 other than the test targets, the bus control unit (BIC) 25 is used for the system bus 4
After receiving the test data D transferred via the, and temporarily storing in the built-in buffer memory (BM) 251, DM
The control unit (DMC) 23 stores it in the storage unit (MM) 22 and notifies the processing unit (CPU) 21 that the test data D transferred from the test target line system control device 2 is received.

When the processing unit (CPU) 21 is notified that the test data D transferred from the test target line control device 2-1 is received (step S41 in FIG. 4), the test program (TP ₄ ) is executed. By executing, the storage unit (M
M) 22 to extract the test data D received from the DMA control unit (DMC) 23 and the bus control unit (BIC) 25,
Then, the data is returned to the transfer source test target line control device 2-1 via the system bus 4 (step S42).

In the test target line system control device 2-1, the bus control unit (BIC) 25 returns the test data D returned from the non-test target line system control device 2-2 via the system bus 4. When received, the four built-in buffer memories (BM) 251 are stored in the order of arrival, but when the first four test data D _{1 to} D ₄ are stored in all the buffer memories (BM) 251, The test data D _{5 and} thereafter that arrive thereafter cannot be stored in the buffer memory (BM) 251 and are discarded, and the line control device 2-2 other than the test subject of the return source is requested to retransmit.

From the above, the line control device under test 2-
In the first bus control unit (BIC) 25, the first-arrival test data D _{1 to} D ₄ are already stored in the four built-in buffer memories (BM) 251, and the later-arrival test data D _{5 and} subsequent data are retransmitted. Is abandoned, which is a so-called high load state.

The DMA control unit (DMC) 23 that has resumed the data receiving function extracts the first-arrival unit (D ₁ ) from the test data D stored in the buffer memory (BM) 251, and the storage unit (MM) 22. After being transferred and stored in the processing unit (CPU) 21, the non-test target line system control device 2-2
The reception of the test data D ₁ transferred from is notified.

The processing unit (CPU) 21 that executes the test program (TP ₃ ) is a line system control device 2-other than the test target.
2 is notified of the reception of the test data D ₁ returned from the device 2 (step S35), the test data D ₁ received from the storage unit (MM) 22 is extracted, and the DMA control unit (DMC) 23
And the bus control unit (BIC) 25 and the system bus 4, and the line system control device 2 other than the test target of the transfer source
-2 (step S36).

D in the line control device 2-1 to be tested
The MA control unit (DMC) 23 is a buffer memory (BM)
Test data D ₁ extracted from 251 ₁ is stored in the storage unit (MM).
When the data has been transferred to 22, the buffer memory (BM) 2
The test data D _{2 and the} subsequent data stored in the data 51 _{2 and} subsequent data are sequentially extracted, and the test data D ₁ and the sequential storage unit (MM)
22 to 22.

Further, the bus control unit (BIC) 25 in the test target line control device 2-1 is the DMA control unit (DMC) 2
3 sequentially extracts the test data D from the buffer memory (BM) 251, and as soon as the buffer memory (BM) 251 becomes empty, it receives the test data D _{5 and} after repeatedly sent back, and becomes the empty buffer memory. (BM) 2
The data is sequentially accumulated at 51.

On the other hand, the line control device 2-other than each test target
2 is the test data D from the line control device 2-1 to be tested.
Is returned to the test target line control device 2-1 in the same process as described above (steps S41 and S).
42).

As is apparent from the above description, according to the embodiment illustrated in FIGS. 2 to 5, the test target line system control device 2-1 includes a plurality of non-test target line system control devices 2-2.
After transferring the test program (TP ₄ ) to the device, the transfer function of the received data is temporarily stopped, and then the test data D is delivered to the line control device 2 other than each test target, and the line control other than each test target is performed. When the test data D is returned from the device 2 and becomes in a high load state, the data receiving function is restarted, the receiving process of the test data D is executed, and the received test data D is again returned from the test object other than the test target. Line system controller 2
-2, the bus communication function of the test target line system control device 2-1 can be tested under a high load condition.

Next, referring to FIGS. 2A and 6, when the line control device 2 tests the bus communication function and the line communication function, the test program (T) is stored in the memory unit (MM) 22.
After storing P ₅ ) and (TP ₅ ), the processing unit (CP
U) 21 test programs (TP ₃ ) and (TP ₆ )
To start executing in parallel.

The processing unit (CPU) 21 executes the test programs (TP ₅ ) and (TP ₆ ) in parallel, thereby bus-controlling the test data D to be sent to the system bus 4 as shown in FIG. Of the test data D which is returned by the BIC unit 25 and sent to the communication line 1.
C) Perform the tests looped back at 24 in parallel.

As is apparent from the above description, according to the embodiment shown in FIGS. 2 (a) and 6, the test target line system controller 2 has the test programs (TP ₅ ) and (TP ₆ ).
The parallel line control device 2 executes the test programs (TP ₁ ) and (TP ₂ ) independently of each other by executing the above processes in parallel. Functions can be tested in parallel.

2 to 7 are merely examples of the present invention until now, for example, the communication line 100, the line accommodation device 2
00 and the bus 300 are not limited to the communication line 1, the line control device 2 and the system bus 4 shown in the figure, and many other modifications can be considered. In any case, the effect of the present invention is obtained. does not change. Also, the test data delivery means 20
1. The test data resending unit 202 and the test data returning unit 203 are not limited to the processing unit (CPU) 21 that executes the illustrated test programs (TP ₃ ) and (TP ₄ ), and many other units are available. Deformation is considered, but the effect of the present invention does not change in any case. Further, it goes without saying that the exchange to which the present invention is applied is not limited to the illustrated one.

[0053]

As described above, according to the present invention, in the exchange, the test data is simultaneously returned from the plurality of line accommodation devices to be tested to the line accommodation device to be tested. Tests can be performed under high load conditions, greatly improving the reliability of the exchange.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing a line control device according to an embodiment of the present invention. FIG. 2 (a) shows a device under test and FIG. 2 (b) shows a device other than the test target.

FIG. 3 is a diagram showing an example of a test operation of the device under test in FIG.

FIG. 4 is a diagram showing an example of a test operation of a device other than the test target in FIG.

5 is a diagram showing an example of a buffer accumulation state in FIG.

FIG. 6 is a diagram showing a comprehensive test process according to an embodiment of the present invention.

FIG. 7 is a diagram showing an example of an exchange subject to the present invention.

FIG. 8 is a diagram showing an example of a conventional line control device.

9 is a diagram showing an example of a bus communication test process in FIG.

FIG. 10 is a diagram showing an example of a line communication test process in FIG.

FIG. 11 is a diagram showing an example of a buffer accumulation state in FIG. 9.

[Explanation of symbols]

 1, 100 communication line 2 line control device 3 system management device 4 system bus 21 processing unit (CPU) 22 storage unit (MM) 23 DMA control unit (DMC) 24 line control unit (LIC) 25 bus control unit (BIC) 200 line accommodation device 201 test data delivery means 202 test data retransmitting means 203 test data returning means 251 buffer memory (BM) 300 bus

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Abe Inventor Hideo Abe 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Within Fujitsu Communication Systems Limited (72) Inventor Yoshihito Fukui Shin-yokohama, Kohoku-ku, Yokohama-shi, Kanagawa 3-9-18 Fujitsu Communication Systems Ltd. (72) Inventor Kinsei Yamamoto 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture 3-9-18 Fujitsu Communication Systems Ltd. (72) Inventor Junichi Moriuchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (4)

[Claims] 1. An exchange that connects a plurality of line accommodating devices (200) each accommodating a communication line (100) to each other via a bus (300), and the line accommodating device (200- 1),
A test data delivery means (20) for delivering test data to each of the plurality of line accommodation devices (200-2) other than the test target.
1) and the test data returned to the own line accommodation device (200-1) from the line accommodation device (200-2) other than the above-mentioned test target, the received test data is tested by the sender. A test data retransmitting means (202) for returning to the line accommodation device (200-2) other than the target is provided, and the line accommodation device (200-2) other than each of the test targets is provided with:
When the test data delivered from the line accommodation device (200-1) to be tested is received, the received line data is the line accommodation device (200-
A high load test system characterized in that a test data returning means (203) for returning to 1) is provided. 2. The line accommodation device (20) to be tested.
0-1) sends the test data to the line accommodating device (200-2) other than each of the test targets and causes the test data returning means (203) to send the test data to the line accommodating device (200) other than the test target. -2) is set, The high load test method according to claim 1. 3. The line accommodation device (20) to be tested.
0-1) are line accommodation devices (20
The high load test method according to claim 1, wherein after the test data is returned from 0-2), the reception processing of each of the returned test data by the test data retransmitting means (202) is started. .. 4. The line accommodation device (20) to be tested.
0-1) are line accommodation devices (20
0-2) and the test of transmitting the test data to and from the communication line (100-1) accommodated in the own line accommodation device (200-1) at the same time. The high-load test method according to claim 1, wherein the high-load test method is performed as follows.