JPH05291962A - Digital signal transmitter - Google Patents

Abstract

PURPOSE:To reduce a level difference of an adjacent signal and to utilize effectively a bit number by replacing data in response to a frequency of an input signal before a digital signal is converted into a DPCM signal. CONSTITUTION:An analog audio signal is converted into a digital signal by an A/D converter circuit and written in a data recording circuit 16. An A/D conversion output is given to a waveform detection circuit 17, in which a frequency of data is detected and the result is inputted to a ROM by using a high-order bit signal of an address control circuit 19. The result of a sampling pulse frequency-divided by an address counter 18 is inputted to low-order bits. The circuit 19 revises the address read from the recording circuit 16 based on the data frequency. The data whose sequence is revised are subject to quasi- momentary compression by a compression circuit and the result is inputted to a signal multiplexer circuit. Moreover, an output of the detection circuit 17 is inputted to the signal multiplexer circuit. Thus, correlation is produced in the adjacent signal to extend the dynamic range of the signal with a high signal frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission device which uses a DPCM signal when transmitting and recording and reproducing a digital signal such as an audio signal in a limited band.

[0002]

2. Description of the Related Art For example, in a digital signal transmission device for transmitting a digital audio signal such as satellite broadcasting,
Sync data, control data, audio data to be transmitted,
An error correction code is added and transmission is performed by two transmission methods of A mode (4 channels) and B mode (2 channels).

The above-mentioned transmission modes of the A mode and the B mode have different data capacities of original signals, but the sampling frequency and the number of bits are changed to cope with this. In the satellite broadcasting for high-definition, FIG. As shown in, the A mode is a DPC with 8 bits and a sampling frequency of 32 kHz.
11 bits in M and B modes, sampling frequency 48k
I am using a DPCM of Hz. Both methods perform quasi-instantaneous companding to obtain a high dynamic range with a limited number of bits.

By the way, the above-mentioned quasi-instantaneous companding means that audio data is divided every 1 ms (therefore, the number of samplings included in one block is 32 or 48, respectively), and among them, the maximum level The frequency of the maximum level is detected, and as shown in FIG. 9, it is determined whether or not the maximum level of the audio signal overflows,
When it overflows, the maximum level of the transmission system is sent according to the maximum level of the audio signal.

FIG. 9 shows that the maximum level of the audio signal is higher by 2 bits (12 dB) than the maximum level of the transmission system, so that the maximum level of the transmission system is increased (compressed) by 2 bits. The amount of compression (the number of bits) at this time is written in the range bits. However, the compression also increases the noise level.

[0006]

However, the above-described conventional digital signal transmission device has a problem that the higher the signal frequency, the smaller the dynamic range in the high frequency range and the higher the noise level.

For example, _assume that the maximum level of an analog audio signal is 1 V _Pp and the digital audio data input to the compression circuit is linearly quantized into 16 bits. When modulated in the A mode, the minimum level of digital audio data is 15.2 μV, so the minimum level of DPCM without compression is also 15.2.
It becomes μV. The number of bits of data modulated in A mode is 8
Since it is a bit, the maximum level is 3.9 mV.

Therefore, as shown in FIG. 10, if the level difference (L) between sampling points (for example, between x (t) and x (t + τ)) is 3.9 mV or less, compression is not necessary.

However, if the level difference (L) is 9 mV, the maximum level is 3.
Since it is 9 mV, it cannot be transmitted. Therefore,
In this case, by increasing the maximum level by 2 bits (12 dB) to 15.6 mV, it becomes possible to transmit 8-bit data, but by increasing the maximum level by 2 bits, the minimum level can be reduced. Level is 2 bits and 6
This is 0.8 μV, which causes an increase in noise level.

As described above, the conventional digital signal transmission apparatus can obtain a high dynamic range with a limited number of bits by performing the quasi-instantaneous companding, as shown in FIG. In the case of a signal having a high frequency and a large level, the noise level is also increased by performing the compression.

Therefore, according to the present invention, data is rearranged according to the signal frequency for the purpose of providing a digital signal transmission apparatus which does not narrow the dynamic range even if the signal has a high signal frequency and a large level. This ensures a dynamic range.

[0012]

SUMMARY OF THE INVENTION The present invention has been invented in view of the above-mentioned drawbacks of the prior art. A frequency detection circuit for detecting the signal frequency of an analog input signal and an A for converting the input signal into a digital signal are provided. A data recording circuit for temporarily storing the digital signals from the D / D conversion circuit and rearranging the digital signals, and a method for rearranging the digital signals by the data recording circuit according to the frequency of the input signal detected by the frequency detecting circuit. The present invention provides a digital signal transmission device comprising an address control circuit for changing the. Further, in the present invention, the data recording circuit is formed by RAM and the address control circuit is formed by ROM.

[0013]

According to the above arrangement, by exchanging the signals, the correlation between adjacent signals occurs, the level difference between adjacent signals is reduced, and the number of bits is effectively used, as compared with the case of performing DPCM. Everything goes out.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. A digital signal transmission apparatus according to this embodiment includes a transmission system A that digitizes and transmits an audio signal,
The receiving system B receives a digital audio signal and converts it into an analog signal. The transmission system is, as shown in FIG.
It has a D conversion circuit 1. The above analog audio signal is composed of two-channel audio signals of L (left) and R (right), and the A / D conversion circuit 1 converts the input audio signal of each channel into sampling frequencies of 48 kHz and 16 kHz. It is converted into a linearly quantized digital signal of bits.

Each output terminal of the A / D conversion circuit 1 is connected to the modulation circuit 2, which is shown in FIG.
As shown in FIG. 1, a data recording circuit 16 including a RAM, a waveform detecting circuit 17 including a counter, and an address counter 1
8, an address control circuit 19 including a ROM.

However, FIG. 2 shows half of the circuit,
There are two data recording circuits 16 and two address control circuits 19 as a whole. When one data recording circuit 16 is writing data, the other data recording circuit 16 is configured to read data.

The data input in the above configuration is written in the data recording circuit 16. The writing order at this time is from the beginning of the RAM. On the other hand, the MSB of the data input to the data recording circuit 16 is also input to the waveform detection circuit 17.

The waveform detection circuit 17 is composed of a counter as described above. Since the MSB of the data represents the polarity of the analog signal, the MS of the counter is detected.
By determining the polarity of B, the frequency of data can be known.

Then, the output data of the waveform detection circuit 17 is input to the ROM as a high-order bit signal of the address control circuit 19, and the address control circuit 1
The lower bit of 9 is input with the sampling pulse divided by the address counter 18. The lower 6-bit signal is also used as an address when the data recording circuit 16 writes data.

The contents of the address control circuit 19 are as shown in FIG. 3, and the read address from the data recording circuit 16 is changed according to the data frequency. That is, at 1 kHz or less (see ROW of "00" and "01"), the writing order and the reading order are the same, but in the range of 2 kHz to 9 kHz ("02").
(See ROW of "0A"), the reading order is changed so that the nodes and valleys of the signal waveform, which have a high correlation, match.

In the DPCM, the signal is divided every 1 ms to detect its level. Therefore, a signal of 1 kHz or less has a period of 1 ms or more, and the correlation cannot be detected within 1 ms. The same address as when writing is read out as it is.

The data whose data order has been changed in this way is input to the compression circuit 3 for performing quasi-instantaneous companding, and the output of the waveform detection circuit 17 showing the method of changing the data is signal multiplexed. It is input to the circuit 4.

In the compression circuit 3, as shown in FIG. 4, the input data is subjected to quasi-instantaneous companding to generate 11-bit DPCM.
11 × 96 bits (Lch: 11 × 4)
8 bits, Rch: 11 × 48 bits) audio data and 16 range bits are output. As shown in FIG. 1, the compression circuit 3 is connected to a signal multiplexing circuit 4, and the signal multiplexing circuit 4 inputs the 112-bit data and the 22-bit control signal of FIG. 3 to the input DPCM signal. It is designed to be inserted.

Here, 4 bits out of 112 bits of data are inserted as data indicating the reading order of the data recording circuit 16. The signal multiplexing circuit 4 is connected to a bit interleave circuit 6 via a correction code addition circuit 5 that forms an error correction code of 8 × 16 bits, and the interleave circuit 6 has some data missing. In this case, the data in other parts are replaced to repair the missing data.

The interleave circuit 6 is connected to the frame synchronization adding circuit 7. The frame synchronization adding circuit 7 adds 16-bit frame synchronization data and outputs it as a multiplexed signal. ..

Next, the receiving system B of the digital signal transmission device
As shown in FIG. 1, a control code detection circuit 8 for reading out a control signal in a multiplex signal and a bit interleave circuit 9 for returning the exchange of data performed at the time of transmission to the original order.
And a frame synchronization detection circuit 10 for detecting synchronization and determining a clock to be output to each circuit. Each of these circuits 8, 9 and 10 has a multiplex output from the above transmission system. The signals are input at the same time.

The bit interleave circuit 9 is connected to an error correction circuit 11 which detects an error in the data generated in the transmission system and corrects the correctable data. The error correction circuit 11 is connected to a signal separation circuit 12 and a decompression circuit 13 to which the control code detection circuit 8 described above is connected. The signal separation circuit 12 separates audio data and range bits from a multiplexed signal. It is like this. The decompression circuit 13 linearly quantizes the multiplexed signal and outputs it.

The expansion circuit 13 is connected to the demodulation circuit 14. This demodulation circuit 14 is, as shown in FIG.
It consists of address control and data recording, and performs data rearrangement opposite to that of the modulation circuit 2.

The demodulation circuit 14 is connected to a D / A conversion circuit 15 as shown in FIG.
The conversion circuit 15 converts the audio signals L and R into analog signals and outputs them as analog audio signals.

Next, the order of reading data from the data recording circuit 16 in the modulation circuit 2 will be described. This order is determined for two reasons. One is Figure 5
As shown in, when the signal is a single sine wave, the level difference is small when comparing the differences between the nodes or the valleys of the waves. Therefore, this characteristic is used to lower the level of transmission. Since the actual signal is not a single frequency sine wave, it is done for the highest level signal frequency.

The other is the influence on the phase difference. In the present invention, the order of reading from the memory is changed every 1 kHz, but the frequency of the signal is not necessarily input every 1 kHz. .. Therefore, a level difference occurs due to the difference between the frequency of the signal and the frequency of the signal detected by the waveform detection circuit 17.

As shown in FIG. 6, when the data having a signal frequency of 1 kHz is set to 2 kHz and the data is rearranged, a level difference of α occurs (1
The data from kHz to 2 kHz is rearranged as 2 kHz).

On the other hand, as shown in FIG. 7, the signal frequency 7
When the data of the kHz is set to 8 kHz and the data is rearranged, a level difference of β occurs. The magnitude of this level difference is determined by the phase difference of the signals. In FIG. 6, the phase difference is 180 degrees (1 kHz / 2 kHz).
Is 315 degrees (7 kHz / 8 kHz), so
The higher the frequency, the smaller the phase difference and the smaller the level difference.

This means that a signal having a high frequency has a small level difference when the frequencies are deviated, and a DPCM for quantizing the level difference requires a small number of bits. When the frequencies for rearranging the data are the same, there is no level difference at any frequency.) It is possible to widen the dynamic range in the high range.

[0035]

As described above, the digital signal transmission apparatus of the present invention can widen the dynamic range of a signal having a high signal frequency by rearranging the data according to the signal frequency of the input signal. It is possible to compensate for the decrease in the dynamic range of the signal frequency, which occurs as a characteristic of.

[Brief description of drawings]

FIG. 1 is a block-like electric circuit diagram showing an embodiment of a digital signal transmission device according to the present invention.

FIG. 2 is an electric circuit diagram showing a specific circuit example of a modulation circuit in the digital signal transmission device according to the present invention.

FIG. 3 is a diagram showing a reading order of a memory set in an address control circuit in a digital signal transmission device according to the present invention.

FIG. 4 is a diagram showing an output format of a compression circuit in the digital transmission device according to the present invention.

FIG. 5 is a waveform chart of signals used for explaining the present invention.

FIG. 6 is a waveform diagram of signals used for explaining the present invention.

FIG. 7 is a waveform chart of signals used for explaining the present invention.

FIG. 8 is a diagram showing a format of a signal in the related art.

FIG. 9 is a diagram provided for explaining a frequency band of a conventional technique.

FIG. 10 is a waveform diagram of a signal used for explaining the conventional technique.

[Explanation of symbols]

 1 A / D conversion circuit 2 Modulation circuit 3 Compression circuit 4 Signal multiplexing circuit 5 Correction code addition circuit 6 Bit interleave circuit 7 Frame synchronization addition circuit 16 Data recording circuit 17 Waveform detection circuit 19 Address control circuit

Claims (2)

[Claims] 1. A digital signal transmission device for converting a digital signal into a DPCM signal for transmission, recording and reproduction, and a frequency detection circuit for detecting a signal frequency of an analog input signal, and an A / A for converting the input signal into a digital signal. A D conversion circuit and a digital signal from the A / D conversion circuit are temporarily stored,
A digital signal transmission device comprising a data recording circuit capable of rearranging the digital signals and an address control circuit capable of changing the rearrangement of the digital signals by the data recording circuit according to the frequency of the input signal detected by the frequency detecting circuit. .. 2. The digital signal transmission device according to claim 1, wherein the data recording circuit comprises a RAM, and the address control circuit comprises a ROM.