JPH05291856A - Generating circuit for agc signal - Google Patents

Abstract

PURPOSE:To provide the generating circuit for an AGC signal with excellent disturbing characteristic and not giving effect onto a main signal system. CONSTITUTION:An emitter of a 1st transistor(TR) Q11 connects to a collector of a 2nd TR Q12 of the same conduction polarity. An emitter of the 2nd TR Q12 connects to ground. A load R11 connects to a collector of the 1st TR Q11. The 1st and 2nd TRS Q11, Q12 are biased for the class AB or class B. An intermediate frequency signal S3 is fed to a base of the 1st TR Q11. A collector output of the 1st TR Q11 is fed to the base of the 2nd TR Q12. The collector output of the 1st TR Q11 is fed to a low pass filter 14 to extract a DC component VDC of the collector output. The DC component VDC is outputted as an AGC signal.

Description

Detailed Description of the Invention

[0001]

This invention relates to an AG suitable for IC integration.
The present invention relates to a C signal forming circuit.

[0002]

2. Description of the Related Art An FM receiving circuit is constructed, for example, as shown in FIG. That is, the broadcast wave signal received by the antenna 1 is supplied to the high frequency amplifier 2 and is subjected to high frequency amplification, and at the same time, the tuning circuit (not shown) included in the high frequency amplifier 2 broadcasts the broadcast wave signal of a target frequency. Is selected.

Then, the selected broadcast wave signal is supplied to the mixer circuit 3, and the local oscillation signal from the local oscillation circuit 4 causes an intermediate frequency signal (intermediate frequency frequency is, for example,
10.7 MHz), and the intermediate frequency signal is supplied to the FM demodulation circuit 8 through the signal line of the buffer amplifier 5 → intermediate frequency filter 6 composed of, for example, a ceramic filter → intermediate frequency amplifier 7 to demodulate the audio signal. To be done.

Further, in this case, a part of the intermediate frequency signal of the intermediate frequency amplifier 7 is supplied to the AGC signal forming circuit 9 to form an AGC signal, and this AGC signal is supplied to the high frequency amplifier 2 to perform AGC. Be seen.

[0005]

By the way, in the AGC forming circuit 9, the AGC signal (AGC voltage) is obtained by detecting and smoothing the FM intermediate frequency signal. That is, the forming circuit 9 detects the FM intermediate frequency signal having a relatively high frequency of 10.7 MHz. Therefore, the load effect of the detection circuit causes the forming circuit 9 to give a loss to the intermediate frequency signal of the original FM intermediate frequency signal system.

Further, when the AGC signal is formed from the output signal of the intermediate frequency amplifier 7 as in the receiving circuit of FIG. 6, even if there is an unnecessary signal at a frequency near the target broadcast wave signal. Since the output signal of the intermediate frequency amplifier 7 has only the intermediate frequency signal frequency-converted from the target broadcast wave signal, the AGC signal changes corresponding to only the level of the target broadcast wave signal and is unnecessary. Even if the level of such a signal is large, the AGC signal does not change.

Therefore, if there is an unnecessary signal with a large level at a frequency near the target broadcast wave signal, the unnecessary signal is supplied from the high frequency amplifier 2 to the mixer circuit 3 almost as it is. The broadcast wave signal is subject to interference. That is, when the AGC signal is formed from the output signal of the intermediate frequency amplifier 7, the interference characteristic is deteriorated.

Further, in a receiving circuit using a battery as a power source, it is required that the current consumption thereof be as small as possible.

The present invention is intended to solve the above problems.

[0010]

Therefore, in the present invention, when the reference numerals of the respective parts correspond to the embodiments described later, the emitter of the first transistor Q11 has the same polarity as that of the first transistor Q11. The collector of the second transistor Q12 is connected, the emitter of the second transistor Q12 is grounded, and the load R11 is connected to the collector of the first transistor Q11.
11 and Q12 are biased to class AB or class B, the intermediate frequency signal S3 is supplied to the base of the first transistor Q11, and the collector output of the first transistor Q11 is supplied to the base of the second transistor Q12. Along with the first
The collector output of the transistor Q11 is supplied to the low-pass filter 14, the DC component VDC of the collector output is taken out, and this DC component VDC is output as the AGC signal.

[0011]

Function: The SRPP circuit 1 is constituted by the transistors Q11 and Q12.
1 is configured. And at this time, the transistor Q1
Since 1 and Q12 are biased to class AB or class B, the low-pass filter 14 connected to the SRPP circuit 11 outputs a DC voltage VDC having a magnitude proportional to the level of the intermediate frequency signal S3. Therefore, AGC is performed using this DC voltage VDC.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, the area shown by the chain line is an IC, and T11 and T12 are external connection terminals (pins). Then, the FM intermediate frequency signal S from the mixer circuit 3
3 is supplied to the base of the transistor Q11 through the capacitor C11.

The transistor Q11 constitutes the SRPP circuit 11 together with the transistor Q12 having the same polarity as that of the transistor Q11. The collector of the transistor Q11 is connected to the power supply terminal T13 through the resistor R11 and the emitter thereof is the transistor Q12.
Of the transistor Q12 is grounded, and the base of the transistor Q12 is connected to the collector of the transistor Q11 through the capacitor C12.

Further, the transistor Q11 operates also as the buffer circuit 5 of FIG. 6, and its emitter is
It is connected to a terminal T11 through a resistor R10 for impedance matching, and a ceramic filter as an intermediate frequency filter 6 is externally attached between the terminals T11 and T12. The terminal T12 is connected to the intermediate frequency amplifier 7.

The output voltage V12 of the constant voltage circuit 12 is
It is supplied to the transistor Q11 as its base bias voltage through the resistor R21. In addition, transistor Q12
The base bias voltage is supplied by configuring the current mirror circuit 13. That is, the output terminal of the constant voltage circuit 12 is connected to the transistor Q through the resistor R22.
It is connected to the collector of 21 and the resistor R
23 is connected to the base of the transistor Q21, the connection point of the resistors R22 and R23 is connected to the base of the transistor Q12 through the resistor R24 (= R23), and the emitter of the transistor Q21 is grounded. Then, by selecting the value of the resistor R22, the transistors Q11 and Q12 are
Class B (or class B) bias is applied, and the direct current flowing through transistors Q11 and Q12 when there is no signal is 100 to 300 μA.
It is considered as a degree.

Further, the collector of the transistor Q11,
A series circuit of a resistor R12 and a capacitor C13 is connected between the terminal T13 and the terminal T13 to form a low-pass filter 14 for removing a DC component by removing an intermediate frequency component (10.7 MHz component) and its element R12, The connection point of C13 is connected to the base of the transistor Q13. The collector of the transistor Q13 is connected to the terminal T13, and the emitter of the transistor Q13 is connected to the collector of the transistor Q22 through the resistor R13.

This transistor Q22 constitutes a constant current source, and its emitter is a resistor R25 (= R13).
Through the constant voltage circuit 12, the resistor R26 and the diode-connected emitter and base of the transistor Q23 are connected in series to the constant voltage circuit 12, and these elements R26,
The connection point of Q23 is connected to the base of the transistor Q22. The transistor Q23 is the transistors Q11 to Q13.
And the opposite polarity.

Further, the connection point between the resistor R13 and the collector of the transistor Q23 is connected to the base of the transistor Q14, its emitter is connected to the terminal T13 through the resistor R14, and its collector is the output end of the AGC current. ..
The transistor Q14 also has the opposite polarity to the transistors Q11 to Q13.

In such a structure, for simplicity, it is assumed that the transistors Q11 and Q12 are biased in class A.

Then, the transistors Q11 and Q12 are SRP.
Since the P circuit 11 is configured, at the connection point between the emitter of the transistor Q11 and the collector of the transistor Q12, the intermediate frequency signal S3 supplied to the base of the transistor Q11 and the intermediate frequency signal of the same phase and the same level are extracted. And
The extracted intermediate frequency signal is supplied to the ceramic filter 6 for the intermediate frequency filter through the resistor R10.

In this case, the transistor Q11 is
It works as an emitter follower and its output impedance is low, so resistor R10 for impedance matching is used.
The value of is almost equal to the input impedance of the ceramic filter 6. The input impedance of the ceramic filter 6 for the intermediate frequency filter is generally about 300Ω, and therefore R10 = 300.
Ω.

If the peak level of the intermediate frequency signal S3 at the maximum input is 1V, the transistor Q11
The peak level of the intermediate frequency signal taken out by the emitter of is also 1V at the maximum input.

Therefore, at the maximum input, the peak level of the signal current flowing through the transistors Q11 and Q12 is 1.67 m.
It becomes A (= 1V / (300Ω + 300Ω)).

In order to pass a signal current of such a magnitude, it is necessary to pass a direct current of 2 mA or more through the transistors Q11 and Q12 in consideration of the distortion characteristics and the like. However, it is necessary to pass a direct current of 1 mA or more through the transistors Q11 and Q12.

The value of this DC current needs to be increased as the dynamic range of the intermediate frequency amplifier 7 is increased, which increases the current consumption of the circuit. The increase in current consumption is not preferable for the battery-powered receiver circuit.

However, in the present invention, the transistors Q11 and Q12 are biased to class AB (or class B), and the value I0 of the direct current IDC flowing through the transistors Q11 and Q12 when there is no signal is about 100 to 300 μA. It is said that.

Therefore, the waveforms of the signal currents flowing through the transistors Q11 and Q12 are as shown in FIG. That is, FIG. 2A shows the input voltage waveform of the intermediate frequency signal S3,
When the peak level of the intermediate frequency signal S3 is small, as shown in FIG. 2B, the peak values of the signal currents i11 and i12 flowing through the transistors Q11 and Q12 do not exceed the value I0 and the transistor Q11 and the transistor Q11 when viewed from the signal S3. Q12 is in class A operation.

However, when the peak level of the intermediate frequency signal S3 increases, as shown in FIG. 2C, the transistor Q
The peaks of the signal currents i11 and i12 flowing through 11 and Q12 are clipped. That is, the transistor Q11 is turned on during the positive half cycle of the signal S3 and is turned off during the negative half cycle, and the transistor Q12 is turned on the contrary to the signal S3.
It is almost off during the positive half-cycle of 3, and on during the negative half-cycle.

Therefore, the peak value of the signal current i11 is i
If p, then the value of the DC current (average current) IDC flowing through the transistor Q11 at this time is IMAX, then IMAX = ip / π. Then, if the peak level of the intermediate frequency signal S3 at the maximum input is 1 V as described above, ip = 1.67 mA
Therefore, IMAX = 531 μA, and this value IMAX is larger than the value I0 (= 100 to 300 μA) when there is no signal.

FIG. 3 shows how the current IDC increases. The solid line characteristic is when the value I0 is set small, and the broken line characteristic is when the value I0 is set large. In these characteristics, the region where the current IDC does not change with respect to the level of the intermediate frequency signal S3 is the region where the transistors Q11 and Q12 perform class A operation (FIG. 2B), and the intermediate frequency signal S3 The region in which the current IDC increases in proportion to the level of is the region in which the transistors Q11 and Q12 perform class AB operation (FIG. 2C). Therefore, if the direct current IDC is extracted from the current flowing through the transistor Q11 (or Q12), it can be used as the AGC signal.

In the circuit of FIG. 1, the resistor R
A voltage proportional to the current flowing through the transistor Q11 is obtained at both ends of 11, and this voltage is supplied to the low-pass filter 14, so that the DC voltage VDC proportional to the DC current IDC is extracted from this filter 14. Then, this voltage VDC is supplied to the transistor Q14 through the transistor Q13.
Is supplied to the collector of the transistor Q14,
Amplified current IDC, that is, AGC signal current IAGC
Is output and this AGC signal current IAGC is supplied to the high frequency amplifier 2 to perform AGC.

Thus, according to the present invention, an AGC signal is formed. In this case, in particular, according to the present invention,
SRP by transistors Q11 and Q12 operating in class AB
A P circuit 11 is constituted, and this SRPP circuit 11 is operated as a buffer circuit 5 for the ceramic filter 6, and a direct current I flowing through its transistor Q11.
Since DC is detected to obtain the signal current IAGC for AGC, the AGC signal forming circuit 9 does not give a loss to the intermediate frequency signal of the original intermediate frequency signal system.

Further, the SRPP circuit 11 for the buffer is
Since it also operates as a detection circuit for the AGC signal, it is not necessary to newly provide a detection circuit for the intermediate frequency signal S3, and the configuration of the AGC circuit is simplified.

Further, the direct current IDC of the SRPP circuit 11 is
Since the AGC signal IAGC is formed from the AGC signal, the interference characteristic can be improved. That is, since the tuning circuit provided in the high frequency amplifier 2 has a wider band than the ceramic filter 6 and the like, if there is an unnecessary signal in the vicinity of the frequency of the target broadcast wave signal, the output signal of the mixer circuit 3 is used. Includes a signal whose frequency is converted from the unnecessary signal.

Since the AGC signal forming circuit 9 forms the AGC signal IAGC from such an output signal, the level of the AGC signal IAGC corresponds to the level of the target broadcast wave signal and is unnecessary. It also supports various signal levels.

Therefore, if there is an unnecessary signal having a large level at a frequency near the intended broadcast wave signal, AGC is performed corresponding to the level of the unnecessary signal, so that the unnecessary signal is low. It is supplied to the mixer circuit 3 at a level and is less susceptible to interference. That is, the interference characteristic can be improved.

Further, as is apparent from FIG. 3, when the level of the intermediate frequency signal S3 is small, the DC current IDC does not change, so that the AGC signal current IAGC does not change at this time, and therefore this AGC When the AGC is performed by the signal current IAGC, the delay AGC is performed. That is, the delayed AGC can be achieved without performing signal processing for the delayed AGC. Particularly, as in the present invention, an AG for improving the interference characteristic at the time of strong input
In the case of C, a delayed AGC is required, but even if the signal processing for the delayed AGC is not performed, it becomes the delayed AGC.
It is even more convenient. Then, the delay amount can be changed by changing the magnitude of the direct current IDC.

Further, even if the base-emitter voltage of the transistor Q14 changes due to the temperature, it is not affected. That is, since the transistor Q23 has the same polarity as the transistor Q14, the base-emitter voltage V23 of the transistor Q23 is equal to the base-emitter voltage of the transistor Q14. Since the transistor Q22 is biased by the voltage V23 and the emitter current of the transistor Q22 is also the emitter current of the transistor Q13, the voltage V13 between the base of the transistor Q13 and the base of the transistor Q14 becomes the voltage V23. Will be equal.

Therefore, depending on the temperature, the transistor Q14
When the base-emitter voltage of the
Since 13 also changes similarly, even if the temperature changes, the collector current of the transistor Q14, that is, the AGC signal current I
AGC does not change.

Further, even if the magnitude of the DC voltage VDC generated in the resistor R14 by the DC current IDC is about 100 mV,
Since the transistors Q13 and Q14 operate normally, the terminal T
The power supply voltage Vcc of 13 can be lowered, which is advantageous for battery-powered ICs.

In the example shown in FIG. 4, the transistor Q
24 is added, its base is supplied with a constant voltage V12, its emitter is grounded through a resistor R27, and its collector is connected to the collector of a transistor Q14.

Therefore, since the transistor Q24 operates as a sink type constant current source, the transistor Q24
If the collector current of is I24, the transistor Q14
Even if the AGC signal current IAGC is output from the collector of
The DC component I24 among them is sucked into the collector of the transistor Q24. Therefore, when IAGC <I24,
Since AGC is not performed, the AGC signal current IAGC supplied to the high frequency amplifier 2 becomes a delayed AGC signal, and its delay amount can be changed according to the magnitude of the current I24. Then, even if the delay amount is changed, the current consumption does not change.

In the example shown in FIG. 5, the DC voltage VDC extracted by the low-pass filter 14 is directly supplied to the transistor Q14 to obtain the AGC signal current IAGC. Therefore, according to this example, the configuration is simpler.

[0044]

According to the present invention, the SRPP circuit 11 is constituted by the transistors Q11 and Q12 operating in the class AB, and this SRPP circuit 11 is operated as the buffer circuit 5 for the ceramic filter 6 and the transistor Q11 is AG that detects the flowing DC current IDC
Since the C signal current IAGC is obtained, the AGC signal forming circuit 9 does not give a loss to the intermediate frequency signal of the original intermediate frequency signal system.

Further, the SRPP circuit 11 for the buffer is
Since it also operates as a detection circuit for the AGC signal, it is not necessary to newly provide a detection circuit for the intermediate frequency signal S3, and the configuration of the AGC circuit is simplified.

Further, the direct current IDC of the SRPP circuit 11 is
Since the AGC signal IAGC is formed from the AGC signal, the interference characteristic can be improved. That is, since the tuning circuit provided in the high frequency amplifier 2 has a wider band than the ceramic filter 6 and the like, if there is an unnecessary signal in the vicinity of the frequency of the target broadcast wave signal, the output signal of the mixer circuit 3 is used. Includes a signal whose frequency is converted from the unnecessary signal.

Since the AGC signal forming circuit 9 forms the AGC signal IAGC from such an output signal, the level of the AGC signal IAGC corresponds to the level of the target broadcast wave signal and is unnecessary. It also supports various signal levels.

Therefore, if there is an unnecessary signal having a large level at a frequency near the intended broadcast wave signal, AGC is performed corresponding to the level of the unnecessary signal, so that the unnecessary signal is low. It is supplied to the mixer circuit 3 at a level and is less susceptible to interference. That is, the interference characteristic can be improved.

Further, as is apparent from FIG. 3, when the level of the intermediate frequency signal S3 is small, the direct current IDC does not change, and at this time, the AGC signal current IAGC does not change, and therefore this AGC When the AGC is performed by the signal current IAGC, the delay AGC is performed. That is, the delayed AGC can be achieved without performing signal processing for the delayed AGC. Particularly, as in the present invention, an AG for improving the interference characteristic at the time of strong input
In the case of C, a delayed AGC is required, but even if the signal processing for the delayed AGC is not performed, it becomes the delayed AGC.
It is even more convenient. Then, the delay amount can be changed by changing the magnitude of the direct current IDC.

Further, even if the base-emitter voltage of the transistor Q14 changes due to the temperature, it is not affected. That is, since the transistor Q23 has the same polarity as the transistor Q14, the base-emitter voltage V23 of the transistor Q23 is equal to the base-emitter voltage of the transistor Q14. Since the transistor Q22 is biased by the voltage V23 and the emitter current of the transistor Q22 is also the emitter current of the transistor Q13, the voltage V13 between the base of the transistor Q13 and the base of the transistor Q14 becomes the voltage V23. Will be equal.

Therefore, depending on the temperature, the transistor Q14
When the base-emitter voltage of the
Since 13 also changes similarly, even if the temperature changes, the collector current of the transistor Q14, that is, the AGC signal current I
AGC does not change.

Further, even if the magnitude of the DC voltage VDC generated in the resistor R14 by the DC current IDC is about 100 mV,
Since the transistors Q13 and Q14 operate normally, the terminal T
The power supply voltage Vcc of 13 can be lowered, which is advantageous for battery-powered ICs.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an example of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the circuit of FIG.

FIG. 3 is a characteristic diagram for explaining the operation of the circuit of FIG.

FIG. 4 is a connection diagram showing another of the present invention.

FIG. 5 is a connection diagram showing still another example of the present invention.

FIG. 6 is a system diagram showing an example of an FM receiving circuit.

[Explanation of symbols]

 2 high frequency amplifier 3 mixer circuit 4 local oscillation circuit 5 buffer circuit 6 intermediate frequency filter 7 intermediate frequency amplifier 8 FM demodulation circuit 9 AGC signal forming circuit 11 SRPP circuit 12 constant voltage circuit 13 current mirror circuit 14 low pass filter

Claims (2)

[Claims] 1. An emitter of a first transistor is connected to a collector of a second transistor of the same polarity as the first transistor, an emitter of the second transistor is grounded, and a collector of the first transistor is connected. A load is connected to the first and second transistors, the first and second transistors are biased to class AB or class B, an intermediate frequency signal is supplied to the base of the first transistor, and the collector output of the first transistor is While being supplied to the base of the second transistor, the collector output of the first transistor is supplied to a low-pass filter to extract the direct current component of the collector output, and the direct current component is output as an AGC signal. A
GC signal forming circuit. 2. The emitter of the first transistor is connected to the collector of a second transistor of the same polarity as the first transistor, the emitter of the second transistor is grounded, and the collector of the first transistor is A load is connected to the first and second transistors, the first and second transistors are biased to class AB or class B, and the intermediate frequency signal from the mixer circuit is supplied to the base of the first transistor. The signal obtained at the connection point between the emitter of the second transistor and the collector of the second transistor is supplied to the intermediate frequency filter, the collector output of the first transistor is supplied to the base of the second transistor, and The collector output of the first transistor is supplied to the low-pass filter and the direct current component of the collector output is collected. Issued, the DC component is to be output as an AGC signal A
GC signal forming circuit.